Code Size Optimization for Embedded Processors

Code Size Optimization for Embedded Processors Neil Edward Johnson Robinson College This dissertation is submitted for the degree of Doctor of Philosophy at the University of Cambridge c May 2004 Neil Edward Johnson Copyright ii Statement of Originality This dissertation is the result of my own work and includes nothing which is the outcome of work done in collaboration except where specifically indicated in the text I confirm that this thesis, including tables and footnotes, but excluding appendices, bibliography, photographs and diagrams, does not exceed the permitted length Signed, Neil Edward Johnson, May 2004 iv Author Publications Parts of this research have been published in the following papers (in chronological order): Prior to the Value State Dependence Graph we considered a three-instruction virtual machine intermediate language, which is described in a laboratory Technical Report: • J OHNSON , N triVM Intermediate Language Reference Manual Technical Report, University of Cambridge Computer Laboratory, UCAM-CL-TR-529, 2002 The Value State Dependence Graph (Chapter 3), together with our combined Register Allocation and Code Motion algorithm (Chapter 6) was presented at the 2003 International Conference on Compiler Construction: • J OHNSON , N AND M YCROFT, A Combined Code Motion and Register Allocation using the Value State Dependence Graph Proc 12th International Conference on Compiler Construction 2003 (LNCS 2622), April 2003, 1–16 The use of Multiple Memory Access instructions for reducing code size (Chapter 5) was presented in a paper at the 2004 International Conference on Compiler Construction: • J OHNSON , N AND M YCROFT, A Using Multiple Memory Access Instructions for Reducing Code Size Proc 13th International Conference on Compiler Construction 2004 (LNCS 2985), April 2004, 265–280 vi Abstract This thesis studies the problem of reducing code size produced by an optimizing compiler We develop the Value State Dependence Graph (VSDG) as a powerful intermediate form Nodes represent computation, and edges represent value (data) and state (control) dependencies between nodes The edges specify a partial ordering of the nodes—sufficient ordering to maintain the I/O semantics of the source program, while allowing optimizers greater freedom to move nodes within the program to achieve better (smaller) code Optimizations, both classical and new, transform the graph through graph rewriting rules prior to code generation Additional (semantically inessential) state edges are added to transform the VSDG into a Control Flow Graph, from which target code is generated We show how procedural abstraction can be advantageously applied to the VSDG Graph patterns are extracted from a program’s VSDG We then select repeated patterns giving the greatest size reduction, generate new functions from these patterns, and replace all occurrences of the patterns in the original VSDG with calls to these abstracted functions Several embedded processors have load- and store-multiple instructions, representing several loads (or stores) as one instruction We present a method, benefiting from the VSDG form, for using these instructions to reduce code size by provisionally combining loads and stores before code generation The final contribution of this thesis is a combined register allocation and code motion (RACM) algorithm We show that our RACM algorithm formulates these two previously antagonistic phases as one combined pass over the VSDG, transforming the graph (moving or cloning nodes, or spilling edges) to fit within the physical resources of the target processor We have implemented our ideas within a prototype C compiler and suite of VSDG optimizers, generating code for the Thumb 32-bit processor Our results show improvements for each optimization and that we can achieve code sizes comparable to, and in some cases better than, that produced by commercial compilers with significant investments in optimization technology viii Acknowledgements This thesis is the culmination of over three years of my life In that time I have had the pleasure of knowing and working with many wonderful people, both in the lab, and elsewhere First and foremost, my thanks go to my supervisors, Alan Mycroft and Martin Richards, without whose sage advice and guidance this thesis would have not been written Secondly, thanks go to my colleagues and friends in the Cambridge Programming Research Group, most notably Richard Sharp, Eben Upton, David Scott, Robert Ennals and Simon Frankau And to other members of the lab at large, for tea breaks, chocolate biscuits, and keeping me sane The majority of my time at the lab was sponsored by ARM Ltd, to whom I extend my greatest thanks for their generosity Thanks go especially to Lee Smith for his patience and his insights into the commercial realities of compilers and their development Of course, none of this would have been possible without the love and support of my parents, Ros and John, and brother, Ian And finally, my deepest gratitude to my wonderful wife Yuliya, whose smile and humour kept me going to the end Neil x ... the current state of the art in code size optimization, and present a new dependence-based program graph, together with three optimizations for reducing code size We begin this introductory chapter... program 1.2 Size Reducing Optimizations This thesis presents three optimizations for compacting embedded systems target code: patternbased procedural abstraction, multiple-memory access optimization, ... 2.5 2.6 2.2.1 Best Graph for Control Flow Optimization 21 2.2.2 Best Graph for Loop Optimization 21 2.2.3 Best Graph for Expression Optimization