PROGRAMMING LIST of EXERCISES

FIGURE 1 Basic 8086 and 8088 systems 2. (a) The 8086 system, illustrating the 16bit data bus, the 20bit address bus, and the control bus. (b) The 8088 system, illustrating the 8bit data bus, the 20bit address bus, and the control bus.

8051 PROGRAMMING Prof Yung-Sheng Chen Department of Electrical Engineering Yuan Ze University 135 Yuan-Tung Road, Nei-Li Taoyuan, Taiwan 320, Republic of China Tel: (03) 463-8800 ext 409 Fax: (03) 463-9355 E-mail: eeyschen@ee.yzit.edu.tw August 1997 TABLE of CONTENTS CHAPTER INTRODUCTION TO MICROCOMPUTER SYSTEM TIME TABLE OF M ICROPROCESSOR (µP) [1] BASIC M IRCOPROCESSOR A RCHITECTURE BASIC DIAGRAM OF A M ICROCOMPUTER SYSTEM CPU BEHAVIOR .10 M EMORY INTERFACE 13 INPUT /OUTPUT INTERFACE 15 ONE-CHIP M ICROCOMPUTER SYSTEM (MCS-51, 8051 CORE ) .17 CHAPTER 8051 ARCHITECTURAL OVERIEW 18 PIN DESCRIPTIONS .18 M EMORY STRUCTURE AND HARDWARE CONFIGURATION 21 REGISTER DESCRIPTIONS 24 SUMMARY OF THE 8051 ON-CHIP DATA M EMORY .28 CHAPTER PROGRAMMER’S GUIDE AND INSTRUCTION SET 29 PROGRAM STATUS W ORD 29 A DDRESSING M ODES 29 A RITHMETIC INSTRUCTIONS 30 LOGICAL INSTRUCTIONS .31 DATA TRANSFERS .33 BOOLEAN INST RUCTIONS 35 JUMP INSTRUCTIONS 37 8051 INSTRUCTION SET SUMMARY 40 CHAPTER BASIC EXERCISES 47 CHAPTER INTERRUPTS 65 INTERRUPT ENABLES 66 INTERRUPT PRIORITIES 67 OPERATION 68 EXERCISES FOR INTERRUPTS 69 CHAPTER TIMER/COUNTERS 71 MODE 72 MODE 74 MODE 75 MODE 78 TIMER SET -UP 79 CHAPTER SERIAL INTERFACE 80 M ODE 80 M ODE 86 M ODE AND 86 BAUD RATES 86 SERIAL PORT SET -UP 91 EXERCISES FOR M ODES 1, 2, AND 92 CHAPTER REFERENCES 95 LIST of FIGURES FIGURE BASIC 8086 AND 8088 SYSTEMS [2] (A) THE 8086 SYSTEM, ILLUSTRATING THE 16-BIT DATA BUS, THE 20-BIT ADDRESS BUS, AND THE CONTROL BUS (B) THE 8088 SYSTEM, ILLUSTRATING THE 8-BIT DATA BUS, THE 20-BIT ADDRESS BUS, AND THE CONTROL BUS FIGURE STRUCTURE OF THE INTEL 8085 MICROPROCESSOR [3] FIGURE 68020-BASED MICROCOMPUTER WITH FLOATING-POINT COPROCESSOR [3] FIGURE BUS ACTIVITY FOR AN OPCODE FETCH CYCLE 10 FIGURE OVERVIEW OF CPU BEHAVIOR [3] 11 FIGURE (A) A SIMPLE ACCUMULATOR-BASED CPU (B) OPERATION OF THE CPU OF (A) [3] 12 FIGURE SIMPLIFIED 8086/8088 READ BUS CYCLE [2] .13 FIGURE A PSEUDO-MEMORY COMPONENT ILLUSTRATING THE ADDRESS, DATA, AND CONTROL CONNECTIONS [2] 13 FIGURE (A) THE PINOUT OF THE 2716, 2K×8 EPROM (B) PINOUT DIAGRAM OF THE 62256, 32K×8 STATIC RAM (C) A SIMPLE NAND GATE DECODER USED TO SELECT A 2716 EPROM MEMORY COMPONENT FOR MEMORY LOCATIONS FF800H-FFFFFH 14 FIGURE 10 THE BASIC INPUT INTERFACE ILLUSTRATING THE CONNECTION OF EIGHT SWITCHES NOTE THAT THE 74ALS244 IS A THREE-STATE BUFFER THAT CONTROLS THE APPLICATION OF THE SWITCH DATA T O THE DATA BUS [2] .15 FIGURE 11 THE BASIC OUTPUT INTERFACE CONNECTED TO A SET OF LED DISPLAYS [2] .15 FIGURE 12 A PORT DECODER THAT DECODES 8-BIT I/O PORTS THIS DECODER GENERATES ACTIVE LOW OUTPUTS FOR PORTS F0H-F7H [2] 16 FIGURE 13 BLOCK DIAGRAM OF THE 8051 CORE [4] 17 FIGURE 14 (A) PINOUTS OF 8051 (B) SPECIAL FEATURES OF P ORT (C) OSCILLATOR CONNECTIONS 18 FIGURE 15 A MORE DETAIL BLOCK DIAGRAM OF 8051 20 FIGURE 16 MCS-51 MEMORY STRUCTURE 21 FIGURE 17 (A) MCS-51 PROGRAM M EMORY (B) EXECUTING FROM EXTERNAL PROGRAM M EMORY 22 FIGURE 18 (A) A CCESSING EXTERNAL DATA M EMORY OF P2 ARE AVAILABLE AS I/O IF THE PROGRAM M EMORY IS INTERNAL, THE OTHER BITS (B) INTERNAL DATA M EMORY (C) THE LOWER 128 BYTES OF INTERNAL RAM (D) SFR (SPECIAL FUNCTION REGISTERS) SPACE 23 FIGURE 19 (A) REGISTERS’ LOCATIONS, AND (B) THE SFR MAP IN MCS-51 24 FIGURE 20 128 BYTES OF RAM DIRECT AND INDIRECT ADDRESSABLE 25 FIGURE 21 (A) CONTAINS A LIST OF ALL THE SFRS AND THEIR ADDRESSES, (B) LISTS THE CONTENTS OF EACH SFR AFTER POWER-ON OR A HARDWARE RESET NOTE THAT , ALL OF THE SFRS THAT ARE BYTE AND BIT ADDRESSABLE ARE LOCATED ON THE FIRST COLUMN OF THE DIAGRAM IN FIG 19(B) 26 FIGURE 22 PSW: PROGRAM STATUS W ORD REGISTER 27 FIGURE 23 SUMMARY OF THE 8051 ON-CHIP DATA MEMORY 28 FIGURE 24 A LIST OF THE MCS-51 ARITHMETIC INSTRUCTIONS 31 FIGURE 25 A LIST OF THE MCS-51 LOGICAL INSTRUCTIONS 32 FIGURE 26 A LIST OF THE MCS-51 DATA TRANSFER INSTRUCTIONS THAT ACCESS INTERNAL DATA M EMORY SPACE .33 FIGURE 27 SHIFTING A BCD NUMBER TWO DIGITS TO THE RIGHT .34 FIGURE 28 A LIST OF THE MCS-51 DATA TRANSFER INSTRUCTIONS THAT ACCESS EXTERNAL DATA M EMORY SPACE .34 FIGURE 29 THE MCS-51 LOOKUP TABLES READ INSTRUCTIONS 35 FIGURE 30 A LIST OF THE MCS-51 BOOLEAN INSTRUCTIONS .36 FIGURE 31 UNCONDITIONAL JUMPS IN MCS-51 DEVICE 37 FIGURE 32 CONDITIONAL JUMPS IN MCS-51 DEVICE 38 FIGURE 33 THE FIRST CIRCUIT HAVING 8-LED DISPLAY 47 FIGURE 34 DATA SHEET OF TTL’245 [5] .48 FIGURE 35 BOUNCING SIGNAL 51 FIGURE 36 A × KEY 55 FIGURE 37 THE ASCII (A MERICAN STANDARD CODE FOR INFORMATION INTERCHANGE ) CODE [2] 58 FIGURE 38 7-SEGMENT DISPLAY FOR ONE-DIGIT 59 FIGURE 39 7-SEGMENT DISPLAY FOR TWO-DIGIT .60 FIGURE 40 8051 INTERRUPT CONTROL SY STEM 65 FIGURE 41 IE (INTERRUPT ENABLE) REGISTER IN THE 8051 .66 FIGURE 42 IP (INTERRUPT PRIORITY) REGISTER IN THE 8051 67 FIGURE 43 INTERRUPT RESPONSE TIMING DIAGRAM 68 FIGURE 44 TMOD: TIMER/COUNTER MODE CONTROL REGISTER 71 FIGURE 45 TIMER/COUNTER M ODE 0: 13-BIT COUNTER 72 FIGURE 46 TCON: TIMER/COUNTER CONTROL REGISTER 72 FIGURE 47 TIMER/COUNTER M ODE 2: 8-BIT AUTO-RELOAD 75 FIGURE 48 TIMER/COUNTER M ODE 3: TWO 8-BIT COUNTERS 78 FIGURE 49 SETUP OF TIMER/COUNTER .79 FIGURE 50 SETUP OF TIMER/COUNTER .79 FIGURE 51 SCON: SERIAL PORT CONTROL REGISTER 80 FIGURE 52 SERIAL PORT M ODE 81 FIGURE 53 (A) THE DIAGRAM USING SIPO, AND (B) THE FLOWCHART OF THIS PROGRAM .83 FIGURE 54 (A) THE DIAGRAM USING PISO, AND (B) THE FLOWCHART OF THIS PROGRAM .84 FIGURE 55 SERIAL PORT M ODE TCLK, RCLK AND TIMER ARE PRESENTED IN THE 8052 ONLY 87 FIGURE 56 SERIAL PORT M ODE2 88 FIGURE 57 SERIAL PORT M ODE TCLK, RCLK, AND TIMER ARE PRESENT IN THE 8052 ONLY 89 FIGURE 58 PCON: POWER CONTROL REGISTER 90 FIGURE 59 TIMER GENERATED COMMONLY USED BAUD RATES 91 FIGURE 60 (A) THE DIAGRAM, AND (B) THE FLOWCHART OF THIS PROGRAM 92 LIST of EXERCISES EXERCISE NAND, NOR, XOR GATES 49 EXERCISE 20 MSEC TIME DELAY S UBROUTINE [DELAY1] 50 EXERCISE 8-LED ON-OFF DISPLAY WITH S EC DELAY 51 EXERCISE KEY-PRESSED COUNT 51 EXERCISE RUNNING LEDS WITH S HIFT INSTRUCTIONS 53 EXERCISE RUNNING LEDS WITH LOOKUP TABLES 54 EXERCISE 4-BY-4 KEY S CAN 55 EXERCISE 7-S EGMENT DISPLAY FOR ONE-DIGIT 59 EXERCISE 7-S EGMENT DISPLAY FOR TW O -DIGIT 60 EXERCISE 10 THE USE OF “DIV AB” INSTRUCTION 62 EXERCISE 11 THE USE OF “MUL AB” INSTRUCTION 63 EXERCISE 12 THE USE OF “DA A” INSTRUCTION 64 EXERCISE 13 EXTERNAL INTERRUPT 69 EXERCISE 14 EXTERNAL INTERRUPTS AND 70 EXERCISE 15 FOR MODE 73 EXERCISE 16 FOR MODE 74 EXERCISE 17 FOR MODE 75 EXERCISE 18 MEASURING THE CYCLE TIME OF A S QUARE-WAVE 76 EXERCISE 19 EXERCISE FOR MODE 0: S ERIAL-IN-PARALLEL -OUT (SIPO, 74LS164) 82 EXERCISE 20 EXERCISE FOR MODE 0: PARALLEL -IN-S ERIAL-OUT (PISO, 74LS165) 84 EXERCISE 21 TRANSMIT AND RECEIVE DATA BY USING S ERIAL PORT MODE 92 EXERCISE 22 TRANSMIT AND RECEIVE DATA BY USING S ERIAL PORT MODE OR 94 Chapter INTRODUCTION TO MICROCOMPUTER SYSTEM Time Table of Microprocessor (µP) [1] Time µP Bits 1971 Intel 4004 (↓ 4-bit MHz) 1972 Intel 8008 8-BIT 1974 Intel 8080 (2 MHz) 8-bit (16-bit addressing) 1974 Motorola 6800 N/A 1975 Zilog Z80 (2.5 8-bit (16-bit MHz) addressing) 1976 MOS Tech 6502 16-bit 1978 Intel 8086 16-bit 1979 Intel 8088 16-bit (8-bit bus) 1979 Motorola 68000 32-bit 1982 Intel 286 (bus 16-bit clocks, 8~12 MHz) 1985 INTEL 386 32-bit (4 GB addressing) 1986 MIPS R2000 N/A 1987 SunSPARC N/A 1989 Intel 486 32-bit 1993 Intel Pentium 32-bit 1993 IBM/Motorola PowerPC 601 Intel Pentium Pro N/A 1995 Transistors Others 2,300 l First MicroProcessor (µP) l 45 instructions 3,500 First 8-bit MicroProcessor 6,000 The Kernel of the first MicroComputer, MITS Altair 4,000 N/A 8,500 Used in the first O.S., CP/M 9,000 Apple II, Graphic & games 29,000 X86 INSTRUCTIONS SET 29,000 PC & DOS 68,000 Platform of UNIX and Machintosh 134,000 Protected mode, Virtual memory, and PC-AT 275,000 l MS Windows & OS/2 l IBM compatible 185,000 RISC µP 50,000 RISC Workstation 1,200,000 l Internal Floating Processor Unit (PU) and Kbytes Cache 3,100,000 l Super Vector Structure l Two pipelines, two instructions can be executed at the same time l integer PU and floating PU l Windows 95 2,800,000 The first µP of executing out-of-order instructions 5,500,000 l SUPER VECTOR STRUCTURE l Three instructions can be executed at the same time l The Level cache (256 kbytes or 512 kbytes) is included 32-bit Basic Mircoprocessor Architecture FIGURE Basic 8086 and 8088 systems [2] (a) The 8086 system, illustrating the 16-bit data bus, the 20-bit address bus, and the control bus (b) The 8088 system, illustrating the 8-bit data bus, the 20-bit address bus, and the control bus FIGURE Structure of the Intel 8085 microprocessor [3] Basic Diagram of a Microcomputer System FIGURE 68020-based microcomputer with floating-point coprocessor [3] FIGURE 52 Serial Port Mode 81 EXERCISE 19 Exercise for Mode 0: Serial-In-Parallel-Out (SIPO, 74LS164) A Up-Count is running and the content is displayed by the SIPO The simple diagram is shown in Fig 53(a) And the operation flowchart is given in Fig 53(b) 82 FIGURE 53 (a) The diagram using SIPO, and (b) the flowchart of this program BUFFER EQU ORG JMP 30H 0H START START: MOV MOV CLR SETB SCON, #00000000B BUFFER, #0H P1.0 P1.0 MOV JBC JMP SBUF, BUFFER TI, TRANSMIT_OK ; Transmit the 8-bit data WAIT LOOP: WAIT: TRANSMIT_OK: CLR MOV CALL INC JMP TI R5, #10 delay1 BUFFER LOOP ; Clear TTL’164 ; Enable TTL’164 for shift ; Clear TI for next data ; Delay 0.2 sec 83 EXERCISE 20 Exercise for Mode 0: Parallel-In-Serial-Out (PISO, 74LS165) A data transfer is performed by reading a 8-bit data from the PISO and showing them on one port The simple diagram is shown in Fig 54(a) And the operation flowchart is given in Fig 54(b) FIGURE 54 (a) The diagram using PISO, and (b) the flowchart of this program 84 ORG JMP 0H START START: MOV SCON, #00010000B ; Set Mode 0, REN = for serial reception LOOP: CLR SETB CLR P2.0 P2.0 RI ; Load DIPSW data in TTL’165 ; Enable TTL’165 for shift ; Clear RI WAIT: JBC JMP RI, RECEIVE_OK WAIT ; Receive the 8-bit data MOV MOV CALL JMP P1, SBUF R5, #25 delay1 LOOP RECEIVE_OK: ; Delay 0.5 sec 85 Mode 10 bits are transmitted (through TXD) or received (through RXD): a start bit (0), data bits (LSB first), and a stop bit (1) On receive, the stop bit goes into RB8 in SCON The baud rate is variable and is determined by the Timer overflow rate Fig 55 shows a simplified functional diagram of the serial port in Mode 1, and associated timings for transmit receive Mode and 11 bits are transmitted (through TXD) or received (through RXD): a start bit (0), data bits (LSB first), a programmable 9th data bit, and a stop bit (1) On transmit, the 9th data bit (TB8 in SCON) can assigned the value of or Or, for example, the parity bit (P, in the PSW) could be moved into TB8 On receive, the 9th data bit goes into RB8 in SCON, while the stop bit is ignored The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency In fact, Mode is the same as Mode in all respects except the baud rate The baud rate in Mode is variable and is determined by the Timer overflow rate Fig 56 and 57 show a simplified functional diagram of the serial port in Modes and 3, respectively Baud Rates MODE BAUD RATE The baud rate in Mode is fixed: Mode Baud Rate = Oscillator Frequency 12 MODE BAUD RATE The baud rate in Mode depends on the value of bit SMOD in Special Function Register PCON shown in Fig 58 If SMOD = (which is the value on reset), the baud rate 1/64 the oscillator frequency If SMOD = 1, the baud rate is 1/32 the oscillator frequency Mode Baud Rate = 2SMOD × (Oscillato r Frequency) 64 86 FIGURE 55 Serial Port Mode TCLK, RCLK and Timer are presented in the 8052 only 87 FIGURE 56 Serial Port Mode2 88 FIGURE 57 Serial Port Mode TCLK, RCLK, and Timer are present in the 8052 only 89 FIGURE 58 PCON: Power Control Register MODE AND BAUD RATES The baud rates in Modes and are determined by the Timer overflow rate Modes 1, Baud Rate = SMOD × (Time Overflow Rate) 32 The Timer interrupt should be disabled in this application The Timer itself can be configured for either “timer” or “counter” operation, and in any of its running modes In the most typical applications, it is configured for “timer” operation, in the auto-reload mode (high nibble of TMOD = 0010B) In that case, the baud rate is given by the formula Modes 1, Baud Rate = SMOD Oscillator Frequency × 32 12 × [ 256 - (TH1) ] One can achieve very low baud rates with Timer by leaving the Timer interrupt enabled, and configuring the Timer to run as 16-bit timer (high nibble of TMOD = 0001B), and using Timer interrupt to a 16-bit software reload Fig 59 lists various commonly used baud rates and how they can be obtained from Timer 90 FIGURE 59 Timer generated commonly used baud rates Serial Port Set-Up NOTE A behavior of multporcessor system is as follows: When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave An address byte differs from a data byte in that the 9th bit is in an address byte and in a data byte With SM2 = 1, no slave will be interrupted by a data byte An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming The slaves that weren’t being addressed leave their SM2s set and go on about their business, ignoring the coming data bytes 91 Exercises for Modes 1, 2, and EXERCISE 21 Transmit and Receive Data by Using Serial Port Mode A Up-Count is running and the content is displayed on port1 The simple diagram is shown in Fig 60(a) And the operation flowchart is given in Fig 60(b) In this exercise, delay is performed by Timer Mode 1, baud rate 9600 is decided by Timer Mode 2, and transmit/receive is performed by serial port mode FIGURE 60 (a) The diagram, and (b) the flowchart of this program 92 BUFFER START: LOOP: WAIT1: EQU ORG JMP MOV ANL MOV MOV SETB MOV CLR CLR 30H 0H START TMOD, #00100001B PCON, #01111111B TH1, #FDH SCON, #01010000B TR1 BUFFER, #00H RI TI MOV JBC JMP SBUF, BUFFER RI, RECEIVE_OK WAIT1 CLR CLR MOV MOV MOV CALL INC JMP RI TI A, SBUF P1, A R7, #10 DELAY BUFFER LOOP MOV MOV SETB JBC JMP CLR CLR DJNZ RET END TL0, #176 TH0, #60 TR0 TF0, TIMEOVER WAIT2 TF0 TR0 R7, DELAY ; Set Timer Mode 1, Timer Mode ; SMOD = ; 9600 at OSC = 11.059 MHz ; Serial Port Mode 1, REN = ; Enable Timer to start ; After this instruction, transmit start ; Transmit and Receive simultaneously RECEIVE_OK: DELAY: WAIT2: TIMEOVER: ; Delay 10 × 50 msec = 0.5 sec ; Delay 50 msec ; Start Timer for Count ; Count until Timer overflow ; Clear Timer overflow flag ; Disable Timer for count 93 EXERCISE 22 Transmit and Receive Data by Using Serial Port Mode or This exercise is the same as exercise 22 Since the serial port Mode is used, the TB8 and RB8 in SCON will be used as the 9th transmitted data bit and received data bit, respectively And SM2 may be further considered to test the operation that if SM2 = (in multiprocessor communication) then RI will not be activated if the received 9th data bit (RB8) is BUFFER START: LOOP: WAIT1: EQU ORG JMP MOV ANL MOV MOV 30H 0H START TMOD, #00100001B PCON, #01111111B TH1, #FDH SCON, #11110000B SETB MOV CLR CLR TR1 BUFFER, #00H RI TI MOV JBC JMP SBUF, BUFFER ; After this instruction, transmit start TI, TRANSMIT_OK ; Transmit and Receive simultaneously WAIT1 TRANSMIT_OK: JNB CLR MOV MOV REJECT_DATA: CLR MOV CALL INC CPL JMP ; Set Timer Mode 1, Timer Mode ; SMOD = ; 9600 at OSC = 11.059 MHz ; Serial Port Mode 3, REN = 1, SM2 = ; TB8 = ; Enable Timer to start RI, REJECT_DATA ; RB8 = 0, reject data RI A, SBUF ; Accept data P1, A TI R7, #10 DELAY BUFFER TB8 LOOP ; Delay 10 × 50 msec = 0.5 sec ; Complement the 9th transmitted bit 94 Chapter REFERENCES [1] PC Magazine, Vol 15, No 22, p 147, (1997) [2] Barry B Brey, The Intel Micorprocessors: 8086/8088, 80186, 80286, 80386, and 80486 Architecture, Programming and Interfacing, 3rd edition, Prentice Hall, Inc., New Jersey, 1994 [3] John P Hayes, Computer Architecture and Organization, 2nd edition, McGraw-Hill, Co., New York, 1988 [4] Embedded Microcontrollers and Processors, Vol 1, Intel, 1993 [5] The TTL Data Book, Volume 3, Texas Instruments, Inc., 1984 95 ... 24 FIGURE 20 128 BYTES OF RAM DIRECT AND INDIRECT ADDRESSABLE 25 FIGURE 21 (A) CONTAINS A LIST OF ALL THE SFRS AND THEIR ADDRESSES, (B) LISTS THE CONTENTS OF EACH SFR AFTER POWER-ON... 27 FIGURE 23 SUMMARY OF THE 8051 ON-CHIP DATA MEMORY 28 FIGURE 24 A LIST OF THE MCS-51 ARITHMETIC INSTRUCTIONS 31 FIGURE 25 A LIST OF THE MCS-51 LOGICAL INSTRUCTIONS... FLOWCHART OF THIS PROGRAM 92 LIST of EXERCISES EXERCISE NAND, NOR, XOR GATES 49 EXERCISE 20 MSEC TIME DELAY S UBROUTINE [DELAY1] 50 EXERCISE 8-LED ON-OFF DISPLAY