Cryptographic hardware and embedded systems – CHES 2016 18th international conference

649 232 0
Cryptographic hardware and embedded systems – CHES 2016   18th international conference

Đang tải... (xem toàn văn)

Tài liệu hạn chế xem trước, để xem đầy đủ mời bạn chọn Tải xuống

Thông tin tài liệu

LNCS 9813 Benedikt Gierlichs Axel Y Poschmann (Eds.) Cryptographic Hardware and Embedded Systems – CHES 2016 18th International Conference Santa Barbara, CA, USA, August 17–19, 2016 Proceedings 123 Lecture Notes in Computer Science Commenced Publication in 1973 Founding and Former Series Editors: Gerhard Goos, Juris Hartmanis, and Jan van Leeuwen Editorial Board David Hutchison Lancaster University, Lancaster, UK Takeo Kanade Carnegie Mellon University, Pittsburgh, PA, USA Josef Kittler University of Surrey, Guildford, UK Jon M Kleinberg Cornell University, Ithaca, NY, USA Friedemann Mattern ETH Zurich, Zürich, Switzerland John C Mitchell Stanford University, Stanford, CA, USA Moni Naor Weizmann Institute of Science, Rehovot, Israel C Pandu Rangan Indian Institute of Technology, Madras, India Bernhard Steffen TU Dortmund University, Dortmund, Germany Demetri Terzopoulos University of California, Los Angeles, CA, USA Doug Tygar University of California, Berkeley, CA, USA Gerhard Weikum Max Planck Institute for Informatics, Saarbrücken, Germany 9813 More information about this series at http://www.springer.com/series/7410 Benedikt Gierlichs Axel Y Poschmann (Eds.) • Cryptographic Hardware and Embedded Systems – CHES 2016 18th International Conference Santa Barbara, CA, USA, August 17–19, 2016 Proceedings 123 Editors Benedikt Gierlichs KU Leuven Leuven Belgium Axel Y Poschmann NXP Semiconductors Germany GmbH Hamburg Germany ISSN 0302-9743 ISSN 1611-3349 (electronic) Lecture Notes in Computer Science ISBN 978-3-662-53139-6 ISBN 978-3-662-53140-2 (eBook) DOI 10.1007/978-3-662-53140-2 Library of Congress Control Number: 2016946628 LNCS Sublibrary: SL4 – Security and Cryptology © International Association for Cryptologic Research 2016 This work is subject to copyright All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed The use of general descriptive names, registered names, trademarks, service marks, etc in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication Neither the publisher nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made Printed on acid-free paper This Springer imprint is published by Springer Nature The registered company is Springer-Verlag GmbH Berlin Heidelberg Preface The 18th Conference on Cryptographic Hardware and Embedded Systems (CHES 2016) was held at the University of California at Santa Barbara, California, USA, August 17–19, 2016 The conference was sponsored by the International Association for Cryptologic Research and—after 2010 and 2013—it was the third time that CHES was co-located with CRYPTO CHES 2016 received a record 148 submissions Each paper was anonymously reviewed by at least four Program Committee members in a double-blind peer-review process Submissions co-authored by PC members received at least five reviews With the help of 210 external reviewers our 47 Program Committee members wrote an impressive total of 623 reviews This year CHES continued the policy that submissions needed to closely match the final versions published by Springer in length and format Additionally, we implemented a new paper submission policy whereby authors needed to indicate conflicts of interest with Program Committee members This mutual indication process led to the upfront identification of roughly five times more conflicts of interest, and, consequently, to a more fair and smooth review process The Program Committee selected 30 papers for publication in these proceedings, corresponding to a 20% acceptance rate Several papers were nominated for the CHES 2016 best paper award After voting, the Program Committee gave the award to Differential Computation Analysis: Hiding Your White-Box Designs Is Not Enough by Joppe W Bos, Charles Hubain, Wil Michiels, and Philippe Teuwen The runners-up were Cache Attacks Enable Bulk Key Recovery on the Cloud by Mehmet S Inci, Berk Gulmezoglu, Gorka Irazoqui, Thomas Eisenbarth, and Berk Sunar, and Software Implementation of Koblitz Curves Over Quadratic Fields by Thomaz Oliveira, Julio López, Francisco Rodríguez-Henríquez All three were invited to submit extended versions to the Journal of Cryptology The technical program was completed by a panel discussion that provided valuable feedback to the academic and industrial communities, and by an excellent invited talk (jointly with CRYPTO 2016) by Paul Kocher from Cryptography Research, a Division of Rambus As a continued tradition, CHES 2016 also featured a poster session and we are very grateful to Billy Bob Brumley for chairing this aspect of the program In addition, two tutorials were given on the day preceding the conference: one by Victor Lomné on Common Criteria Certification of a Smartcard: A Technical Overview and one by Yuval Yarom on Micro-Architectural Side-Channel Attacks For the second time a CHES challenge was organized We are very grateful to Ryad Benadjila, Emmanuel Prouff, and Adrian Thillard for chairing the challenge selection process, and to Colin O’Flynn for running the CHES 2016 challenge The review process was a challenging and time-consuming task We sincerely thank the Program Committee members as well as their external reviewers for the hard work and many hours spent reviewing, assessing, and discussing The submission process, VI Preface the review process, and the editing of the final proceedings were greatly simplified by the software written by Shai Halevi and we thank him for his kind and immediate support throughout the whole process We would also like to thank the General Chairs, ầetin Kaya Koỗ and Erkay Sava, local organizers Sally Vito and Whitney Morris (of UCSB Conference Services), Juan Manuel Escalante, who designed the CHES 2016 memorabilia, and the webmaster, Thomas Eisenbarth Our thanks also go out to Matt Robshaw and Jonathan Katz, the Program Chairs of CRYPTO 2016, for the successful collaboration and alignment of the programs of CHES and CRYPTO We are very grateful for the financial support received from our many generous sponsors Finally, among the numerous people that contributed to the success of CHES 2016, above all others are the authors who submitted their research papers to the conference Without them, this conference would not exist We enjoyed chairing the Program Committee and we hope you will enjoy these proceedings June 2016 Benedikt Gierlichs Axel Y Poschmann CHES 2016 18th Conference on Cryptographic Hardware and Embedded Systems Santa Barbara, California, USA August 17–19, 2016 Sponsored by the International Association for Cryptologic Research General Chairs Çetin Kaya Koỗ Erkay Sava University of California at Santa Barbara, USA Sabanci University, Turkey Program Chairs Benedikt Gierlichs Axel Y Poschmann KU Leuven, Belgium NXP Semiconductors, Germany Program Committee Josep Balasch Lejla Batina Daniel J Bernstein Guido Bertoni Chen-Mou Cheng Hermann Drexler Orr Dunkelman Junfeng Fan Sebastian Faust Viktor Fischer Wieland Fischer Henri Gilbert Christophe Giraud Daniel Holcomb Naofumi Homma Michael Hutter Kimmo Järvinen Marc Joye Lars R Knudsen Kerstin Lemke-Rust Tancrède Lepoint KU Leuven, Belgium Radboud University, The Netherlands University of Illinois at Chicago, USA and Technische Universiteit Eindhoven, The Netherlands STMicroelectronics, Italy National Taiwan University, Taiwan Giesecke & Devrient, Germany University of Haifa, Israel Open Security Research, China Ruhr-Universität Bochum, Germany Jean Monnet University Saint-Etienne, France Infineon Technologies, Germany ANSSI, France Oberthur Technologies, France University of Massachusetts Amherst, USA Tohoku University, Japan Cryptography Research, USA Aalto University, Finland Technicolor, France Technical University of Denmark, Denmark Bonn-Rhein-Sieg University of Applied Sciences, Germany CryptoExperts, France VIII CHES 2016 Yang Li Roel Maes Mitsuru Matsui Marcel Medwed Amir Moradi Debdeep Mukhopadhyay Elke De Mulder David Naccache Elisabeth Oswald Daniel Page Thomas Peyrin Emmanuel Prouff Francesco Regazzoni Matthieu Rivain Alexander Schlösser Sergei Skorobogatov Meltem Sönmez Turan Marc Stöttinger Berk Sunar Hugues Thiebeauld Olivier Thomas Mehdi Tibouchi Steve Trimberger Ingrid Verbauwhede Andre Weimerskirch Brecht Wyseur Nanjing University of Aeronautics and Astronautics, China Intrinsic-ID, The Netherlands Mitsubishi Electric, Japan NXP Semiconductors, Austria Ruhr-Universität Bochum, Germany Indian Institute of Technology Kharagpur, India Cryptography Research, USA École normale supérieure, France University of Bristol, UK University of Bristol, UK Nanyang Technological University, Singapore Safran Identity & Security, France ALaRI, Lugano, Switzerland CryptoExperts, France NXP Semiconductors, Germany University of Cambridge, UK NIST, USA Continental Teves, Germany Worcester Polytechnic Institute, USA eshard, France Texplained, France NTT Secure Platform Laboratories, Japan Xilinx, USA KU Leuven, Belgium University of Michigan, USA NAGRA, Switzerland External Reviewers Martin R Albrecht Guilherme Almeida Gilles Van Assche Jean-Philippe Aumasson Aydin Aysu Reza Azarderakhsh Florian Bache Thomas Baignères Subhadeep Banik Guillaume Barbu Guy Barwell Alberto Battistello Sven Bauer Georg T Becker Steffen Becker Sonia Belaïd Ryad Benadjila Florent Bernard Régis Bevan Shivam Bhasin Sarani Bhattacharya Russ Bielawski Begül Bilgin Markus Bockes Joppe Bos Lilian Bossuet Claudio Bozzato Jakub Breier Billy Bob Brumley Samuel Burri Martin Butkus Rodrigo Portella Canto Claude Carlet Pierre-Louis Cayrel Gizem Selcan Cetin Thomas Chabrier Rajat Subhra Chakraborty Ayantika Chatterjee Urbi Chatterjee Ricardo Chaves Chien-Ning Chen Cong Chen Abdelkarim Cherkaoui Jean-Michel Cioranesco Ruan de Clercq CHES 2016 Thomas De Cnudde Brice Colombier Jean-Sébastien Coron Guillaume Dabosville Joan Daemen Wei Dai Poulami Das Nicolas Debande Jeroen Delvaux Jintai Ding Yarkin Doroz Emmanuelle Dottax Baris Ege Thomas Eisenbarth Guangjun Fan Claudio Favi Peter Felber Magnus Gausdal Find Matthieu Finiasz Daisuke Fujimoto Georges Gagnerot Adriano Gaibotti Jake Longo Galea Benoit Gerard Cezary Glowacz Gilbert Goodwill Louis Goubin Aurélien Greuet Vincent Grosso Daniel Gruss Frank K Gürkaynak Mike Hamburg Ghaith Hammouri Bill Hass Wei He Annelie Heuser Lars Hoffmann Yuan-Che Hsu Ilia Iliashenko Gorka Irazoki Dirmanto Jap Eliane Jaulmes Tommi Junttila Elif Bilge Kavun Osnat Keren Mehran Mozaffari Kermani Ilya Kizhvatov Patrick Klapper Miroslav Knezevic Markus Kuhn Tanja Lange Sam Lauzon Jenwei Lee Gaëtan Leurent Wen-Ding Li Zhe Liu Zheng Liu Susanne Lohmann Cuauhtemoc Mancillas Lopez Atul Luykx Pieter Maene Houssem Maghrebi Cedric Marchand Daniel Martin Marco Martinoli Daniel Masny Pedro Maat Massolino Luke Mather Sanu Mathew Ingo von Maurich Silvia Mella Filippo Melzani Bart Mennink Rafael Misoczki Nicolas Moro Zakari Najm Ousmane Ndiaye Ventzislav Nikov Tobias Nink Tobias Oder Brisbane Ovilla Erdinc Ozturk Clara Paglialonga Paolo Palmieri Louiza Papachristodoulou Kostas Papagiannopoulos IX Sikhar Patranabis Sylvain Pelissier Hervé Pelletier Jan Pelzl Bo-Yuan Peng Peter Pessl Antonio de la Piedra Thomas Prest Christian Pilato Gilles Piret Thomas Plos Ilia Polian Thomas Pöppelmann Frédéric de Portzamparc Jürgen Pulkus Christof Rempel Joost Renes Oscar Reparaz Thomas Ricosset Lionel Riviere Molka ben Romdhane Franck Rondepierre Debapriya Basu Roy Sujoy Sinha Roy Markku-Juhani O Saarinen Durga Prasad Sahoo Kazuo Sakiyama Peter Samarin Fabrizio De Santis Pascal Sasdrich Falk Schellenberg Werner Schindler Tobias Schneider Okan Seker Hwajeong Seo Siang Meng Sim Daniel Smith-Tone Martijn Stam Francois-Xavier Standaert Takeshi Sugawara Ruggero Susella Daisuke Suzuki Pawel Swierczynski A Design Methodology for Stealthy Parametric Trojans 635 Constraint on Delay of Each Gate Next we provide the genetic algorithm with a hint that helps it to discover reasonable delays for each gate In this step, we use di to represent the nominal delay of the ith gate on chosen path π, and si to represent the a slack metric associated with the same gate Each slack parameter si describes how much delay can be added to the corresponding gate without causing the path to exceed the clock period Because the targeted path delay D does exceed the clock period, gate delays are allowed to exceed their computed slack The slack for each gate is computed as a function of the nominal delay of the gate, data dependency, and the clock period [10,25] The following equation shows the constraint on delay of gate i, where c is a constant di + si − c ≤ di ≤ di + si + c (2) Fitness Function Simply stated, the cost function that we want to minimize is the probability of causing an error when random input vectors are applied to the circuit Because there is no simple closed-form expression for this, we use random simulation to evaluate the cost of any delay assignment When the genetic algorithm in Matlab needs to evaluate the cost of a particular delay assignment, it does so by executing a timing simulator The timing simulator, in our case ModelSim, applies random vectors to the circuit-under-evaluation and a golden copy of the circuit and compares the respective outputs to count the number of errors that occur These errors are caused by the delay assignments in the circuit-under-evaluation The cost that is returned from the simulator is the percentage of inputs that caused an error for this delay assignment As the genetic algorithm proceeds through more and more generations of solutions, the quality of the solutions improve Matlab’s genetic algorithm implementation comes with a stopping criterion, so we simply allow the algorithm to run until completion Experimental Results We now evaluate the effectiveness of our method of designing Trojans, using a 32 × 32 Wallace tree multiplier as a test case The circuit has a nominal critical path of length 128, and the delay of this path is 2520 ps 5.1 Evaluation of Phase I (Path Selection) To evaluate the ability of our path selection algorithm (Sect 4.1) to find a rare path, we compare the stealthiness of the path selected by the algorithm against the stealthiness of 750 randomly chosen paths For each of these paths, we seek to find how often an error would occur under random inputs if the path delay is increased We measure this by uniformly increasing the delay of each gate on the path such that the total delay of the path is 5040 ps, which is twice the delay of the nominal critical path After the delay modification, 10,000 random vectors are applied and the number of error-causing vectors is counted The histogram 636 S Ghandali et al of Fig shows the result; the x-axis represents error rates, and the y-axis shows how many of the paths have each error rate The result shows that a majority of paths would cause frequent errors if their delay is increased, and these paths are thus unsuitable for stealthy Trojans The rare path (RP) selected by our algorithm caused an error for only of 10,000 vectors By comparison, the best of the random paths caused an error in 174 of 10,000 vectors In this experiment, the path chosen by the path selection algorithm is 43x less likely to cause an error than the best of 750 random paths Note that this experiment is conservative in that the amount of additional delay added is very large, and the delay is not smartly distributed along the path to minimize detection 5.2 Evaluation of Phase II (Delay Distribution) To evaluate the effectiveness of our delay distribution method, we apply the proposed method (Sect 4.2) on 10 paths from the multiplier These 10 paths are the rare path chosen by the path selection algorithm, and paths randomly selected from the set of all paths that caused less than 10 % error rates in Fig For each of these paths, we use the genetic algorithm to optimally allocate a total delay of 3276 ps (i.e 1.3 times of the delay of the nominal critical path) over the path, and then evaluate the error probability using random simulation with 5,000,000 vectors Figure shows the error probability of each path before and after applying our proposed delay distribution method In each case, the optimization step reduces the probability of causing an error by at least 3.5x For the rare path (RP), just one error in 5,000,000 vectors is caused after delay Fig Fault simulation of rare path and 750 random paths of 32 × 32 Wallace tree multiplier A Design Methodology for Stealthy Parametric Trojans 637 Fig Error probability of circuit before and after optimizing delay assignment of rare path and other paths in a 32 × 32 Wallace tree multiplier distribution This result shows that, for a given total path delay, optimizing the delay assignment along the path can reduce the probability of having an error when random vectors are applied It is important to note that this improvement in stealthiness comes from minimizing the side effects of the added delay, and does not impact triggerability when vectors are applied that actually sensitize the entire chosen path 5.3 Overall Evaluation We evaluate our overall methodology comprising path selection and delay distribution on the 32 × 32 Wallace Tree multiplier circuit Instead of assuming a particular clock frequency, here we examine whether it is possible to add delay to the chosen rare path such that the circuit will (1) exceed the nominal critical path delay of 2520 ps when the applied input sensitizes the rare path, and (2) always have delay of less than 2520 ps otherwise We first distribute delay uniformly over the path, and then apply the same total delay to the path but distribute it using the genetic algorithm (Sect 4.2) The results are shown in Table Despite simulating 260 million random vectors, we are unable to randomly discover any vectors in which the circuit delay exceeds 2520 ps Yet, when applying a vector pair produced by our SAT-based sensitization check, we observe that the chosen path delay does exceed 2520 ps As simulating 260 million vectors on a circuit this size already used more than 240 h of computation on an AMD Opteron (TM) Processor running at 2.3 GHz with cores and 64 GB RAM, it will become quite expensive to check increasing numbers of vectors beyond 260 million This highlights a significant challenge: given a space of 2128 possible vector pairs that might cause an error, it is very hard to estimate the probability of an error that is sufficiently rare If the probability of error is around or above roughly 2−26 , then random simulation will suffice to find a few errors and estimate the error probability If the probability of error is below roughly 2−98 it would be possible to use SAT to exhaustively enumerate all 230 vectors that would cause an error Unfortunately, for very interesting region of error probabilities between 2−26 and 2−98 there is no clear solution for estimating the error probabilities 638 S Ghandali et al Table Probability of exceeding the nominal critical path delay in a 32 × 32 Wallace Tree Multiplier after adding delay to the rare path When uniformly distributing the delay over the path, the longest delay exceeds 2520 ps for 57 of 200,000 random applied vectors After using genetic algorithm (Sect 4.2) to distribute the delay, the circuit delay never exceeds 2520 ps in 260 million random vectors Delay distribution Uniform GA Num of times exceeding 2520 ps 57 Num of random vectors applied 200,000 260M Prob of exceeding 2520 ps < 2−26 0.0003 Fig Increasing the rare path delay increases the probability of causing an error when random vectors are applied This delay is allocated to gates according to the delay distribution algorithm The results are shown for different clock periods When the amount of delay added to the rare path is increased, and the probability of error grows above 2−26 , the error probability can feasibly be estimated with random simulation In this regime, we can evaluate the tradeoff of delay and trigger probability For example, when the chosen path is given a total delay of 3150 ps allocated using genetic algorithm for delay distribution, and the circuit is operated at a clock period of 2800 ps (as might be reasonable for a nominal critical path of 2520 ps) an erroneous output occurs with probability of roughly 2−24 (once every 16 million multiplications) when random inputs are applied The overall tradeoff is shown in Fig for different clock periods One can exploit this tradeoff to create a desired error probability by increasing or decreasing the total amount of delay added to the chosen path Bug Attack on ECDH with a Trojan Multiplier The main motivation of choosing a multiplier as our case study is the bug attack paper by Biham et al [5,6] They showed how several public key implementations can be attacked if the used multiplier computes a faulty response for some rare inputs The real-world implications of bug attacks were first demonstrated by Brumley et al in 2012 when they showed how a software bug in A Design Methodology for Stealthy Parametric Trojans 639 an implementation of the reduction step of an elliptic curve group operation in OpenSSL could be exploited to recover private ECDH-TLS server keys [7] Note that while they exploited a software bug as opposed to a hardware bug and a modular reduction as opposed to a multiplication, the attack idea itself is the same as in the original bug attack paper [5] 6.1 Fault Model of the Trojan Multiplier The Trojan Multiplier introduced in the precious Section has a different fault model than the one assumed in [5] In particular, the output of the Trojan Multiplier does not only depend on the current input but also on the previous inputs, i.e., it has a state We define the multiplication of two 32-bit numbers a1 , b1 with our Trojan Multiplier as y˜ = M U La0 ,b0 (a1 , b1 ) where a0 , b0 is the previous input pair to the multiplier The list F of quadruples (a0 , b0 , a1 , b1 ) are all input sequences for which the Trojan Multiplier computes a faulty response: For all (a0 , b0 , a1 , b1 ) ∈ F : y˜ = M U La0 ,b0 (a1 , b1 ) = y = a1 · b1 For all (a0 , b0 , a1 , b1 ) ∈ / F : y˜ = M U La0 ,b0 (a1 , b1 ) = y = a1 · b1 (3) Outputs computed with the Trojan Multiplier are always represented with a tilde An ECC scalar multiplication of point Q ∈ E with an integer k is denoted as R = k · Q An elliptic curve scalar multiplication using the Trojan Multiplier ˜ = k Q In the following we assume that an is denoted with an , i.e., R attacker has knowledge of the Trojan Multiplier or access to a chip with the ˜ = R Trojan Multiplier such that the attacker knows for which inputs R The attack complexity strongly depends on the probability that a multiplication results in a faulty response In order to be able to compute this probability we make following definitions: PM (a1 ,b1 ) : Probability that for two random 32-bit integers a1 , b1 there exits at least one pair of 32-bit integers a0 , b0 such that y˜ = M U La0 ,b0 (a1 , b1 ) computes a faulty response PM (a1 ) : Probability that for a random 32-bit integers a1 there exits at least one triplet of 32-bit integers a0 , b0 , b1 such that y˜ = M U La0 ,b0 (a1 , b1 ) computes a faulty response Probability PM (b1 ) is defined in the same fashion PM (a0 ,b0 |a1 ,b1 ) : Probability that for two random 32-bit integers a0 , b0 and two given integers a1 , b1 the multiplication y˜ = M U La0 ,b0 (a1 , b1 ) computes a faulty response if there exists at least one other input pair a0 , b0 for which y˜ = M U La0 ,b0 (a1 , b1 ) computes a faulty response PM (a0 |a1 ,b1 =b0 ) : Probability that for a random 32-bit integers a0 , and two given integers a1 , b1 the multiplication y˜ = M U La0 ,b0 (a1 , b1 ) with b0 = b1 computes a faulty response if there exists at least one other input pair a0 , b0 for which y˜ = M U La0 ,b0 (a1 , b1 ) computes a faulty response Furthermore, we make following assumptions regarding these probabilities for the Trojan Multiplier : 640 S Ghandali et al PM (a1 ) ≈ PM (b1 ) and PM (a1 ,b1 ) = PM (a1 ) · PM (b1 ) PM (a0 ,b0 |a1 ,b1 ) ≈ 0.09 PM (a0 |a1 ,b1 =b0 ) ≈ 0.18 Assumption (1) follows from the fact that both inputs have the same impact on the propagation path of the signal Hence it is reasonable that both values are equally important to determine if a multiplication fails Assumption (2) is based on experimental results in which 892 out of 10,000 multiplication failed when a0 and b0 are changed randomly while keeping a1 , b1 constant Assumption (3) is based on a similar experiment in which 1813 out of 10,000 multiplication failed when a0 was changed randomly and b0 was fixed to b0 = b1 and a1 was kept constant as well 6.2 Case Study: An ECDH Implementation with Montgomery Ladder For our case study we assume a 255-bit ECDH key agreement with a static public key Furthermore, we assume the implementation uses the Montgomery Ladder scalar multiplication The ECDH key agreement works as follows: Given are a standardized public curve E (e.g Curve25519) and the point G ∈ E The private key of the server is a 255 bit integer ks and the corresponding public key is Qs = ks · G The key agreement is started by the client by choosing a random 255-bit integer kc and computing Qc = kc · G The client sends Qc to the server and computes the shared key R = ks · Qs The server computes the shared secret key R using Qc and his secret key ks by computing R = kS · Qc Usually, the key agreement is followed by a handshake to ensure that both the client and the server are now in possession of the same shared session key R The general idea of the bug attack is that the attacker makes a key guess of the first l bits of the secret key Ks Then the attacker searches for a point ˜ = ks Q results in a failure Q = m · G such that the scalar multiplication R if, and only if, the most significant bits of ks are indeed the l bits the attacker guessed The attacker then sends Q to the server and completes the ECDH key exchange protocol by making a handshake with the shared key R = m·Qs If this handshake fails, the expected multiplication error in the Trojan Multiplier has occurred and hence, the attacker knows that his key guess is correct This way more and more bits of the key are recovered consecutively In the Montgomery Ladder scalar multiplication only one bit of the key is processed in each ladder step and the attack works as follows: Input: Elliptic curve E with point G ∈ E and public server key Qs ∈ E Initialization: Set k = 1(2) Repeat for key bit to 255: (a) Define k0 = k||0(2) [Append a zero to the key k] (b) Define k1 = k||1(2) [Append a one to the key k] (c) Repeatedly choose a value m and compute Q = m · G until: (P˜i = ki Q) = (Pi = ki · Q) for i ∈ {0, 1} (P˜j = kj Q) = (Pj = kj · Q) for j = i, j ∈ {0, 1} A Design Methodology for Stealthy Parametric Trojans 641 (d) Send Q to the server and complete handshake with R = m · Qs (e) If handshake failed, set k = ki , else set k = kj The attack described above is a straight forward adaption of the bug attack from [7] However, in the Trojan multiplier scenario the attack can be improved significantly by adding a precomputation step The main idea is to not use randomly generated points Q in step 3.c) but to use points Q in which the x-coordinate Qx contains a b1 for which the Trojan Multiplier y˜ = M U La0 ,b0 (a1 , b1 ) has a high chance to return a faulty response That is, b1 is one of the inputs for which the Trojan Multiplier fails In each step of the Montgomery Ladder algorithm the projective coordinate Z2 is computed with Z2 ← Z2 · Qx Hence, Qx , and therefore also b1 , is used in every ladder step Furthermore, the value Z2 is different depending on the currently processed key bit Our improved attack targets this 255-bit integer multiplication Z2 · Qx to find a Q such that (P˜i = Pi ) while (P˜j = Pj ) as needed in step 3.c) of the attack algorithm Unfortunately, the attacker cannot freely choose Q since the attacker needs to know m such that Q = m · G to finish the handshake Instead of computing suitable points for each attack, we propose to search for t suitable points Q during a precomputation step as described below: Input: Elliptic curve E with point G ∈ E Initialization: m = 1, Q = G Repeat t times: (a) m = m + 1, Q = Q + G (b) If Qx contains b1 , store m and Q in list L To compute the probability that the 255-bit integer multiplication Z2 · Qx fails the used multiplication algorithm is important We assume that the schoolbook multiplication is used One 255-bit schoolbook multiplication consists of 64 multiplications of which have b1 as an operand Since one of these multiplication is a 31-bit multiplication and we assume that only 32-bit multiplications can trigger the Trojan, 32-bit multiplications with b1 that can trigger the Trojan are performed in each ladder step Furthermore, due to the F OR loops in the schoolbook multiplication, in of these multiplications b0 = b1 , i.e., the second operand in the multiplication remains unchanged Note that PM (a0 |a1 ,b1 =b0 ) ≈ 0.18 and hence this is actually not a problem but rather helpful The average number AQ of points Q that need to be tested until a failure occurs for key bit or is therefore: AQ = 1 · PM (a1 ) · PM (a0 |a1 ,b1 =b0 ) · + PM (a1 ) · PM (a0 ,b0 |a1 ,b1 ) · Let us assume that the attacker tries to find a point Q for key bit i Since the attacker searches for a fault in the last Montgomery Ladder step, for every point Q the attacker needs to compute i − Montgomery Ladder steps (for the first See Appendix B of the IACR ePrint version for the Montgomery Ladder algorithm 642 S Ghandali et al Table Attack complexity of the proposed improved bug attack using the Trojan multiplier assuming a 256 bit curve PM (a1 ,b1 ) 2−64 2−48 2−32 Precomputation complexity (point additions) 266.8 250.8 234.8 Storage requirement 14 PB 55 TB 215 GB Attack complexity (scalar multiplications) 230.8 222.8 214.8 Attack complexity (montgomery ladder steps) 246.8 238.8 230.8 key bit no step is needed) and then two Montgomery Ladder steps for key bit and respectively to check if the multiplication fails Hence, in total the attacker needs an average of AM Montgomery Ladder steps to recover a 255 bit key: 255 (i · AQ ) = AM = i=2 2552 + 255 · AQ ≈ 216 · AQ To compute t points Q during the precomputation such that b1 is in Qx the attacker needs in average AP = t · PM (b1 ) point additions We chose t = 16 · AQ which results in a failure probability of ca 3.3·10−8 which should be small enough for all reasonable attack scenarios Table summarizes the attack complexity for our improved bug attack with precomputation for different parameters for the Trojan Multiplier To put these numbers into perspective, the hardware implementation of curve25519 presented in [22] can compute roughly 239.3 Montgomery Ladder steps per second on a Xilinx Zynq 7020 FPGA Hence, especially for a failure probability of PM (a1 ,b1 ) = 2−48 the attack complexity of 239 Montgomery ladder steps (and 250 point additions that only need to be done once) is quite practical in a real-world scenario On the other hand, the probability that the Trojan is triggered unintentionally during normal operation is about 2−37 which is low enough to not cause problems (see Appendix B for details) Conclusion This paper introduced a new type of parametric hardware Trojans based on rarely-sensitized path delay faults While hardware Trojans using parametric changes (i.e that only modify the performance/parameters of gates) have been proposed before, the previously proposed parametric hardware Trojans cannot be triggered deterministically They are instead either triggered after time by aging [23], triggered randomly under reduced voltage [17] or are always on and can leak keys using a power side-channel [4] In contrast, the proposed parametric hardware Trojan in this paper can be triggered by applying specific input A Design Methodology for Stealthy Parametric Trojans 643 sequences to the circuit Hence, this paper introduces the first trigger-based hardware Trojan that is realized solely by small and stealthy parametric changes To achieve this, a SAT-based algorithm is presented which efficiently searches a combinational circuit for paths that are extremely rarely sensitized A genetic algorithm is then used to distribute delays over all the gates on the path so that a path delay fault occurs when trigger inputs are applied, while for other inputs the timing criteria are met In this way, a faulty response is computed only for a very small subset of input combinations To demonstrate the usefulness of the proposed technique, a 32-bit multiplier is modified so that, for some multiplications, faulty responses are computed These faults can be so rare that they not interfere with normal operations but can still be used by the Trojan designer for a bug attack against public key algorithms As a motivating example, we showed how this can be achieved for ECDH implementations Please note that while we used a multiplier as our case study, the general idea of path delay Trojans and the tool-flow and algorithms presented in this paper are not restricted to multipliers Hence, this work shows that by only making extremely stealthy parametric changes to a design, a malicious factory could insert backdoors to leak out secret keys A Difficulty of Justification and Propagation Tables Table Computation of dif f j for different gate types In the case of 2-input gates, we assume without loss of generality that input A is the on-path input and B is the offpath input The first two columns show the output transition, and the input transition that we are trying to justify for this output transition Columns 3–6 show the values that the on-path input (A) and off-path input (B) must take in the first and second cycles to justify the desired transition The final column shows the formula to compute dif f j in terms of the controllability of the inputs Output trans Input trans A Dif f j B v(1) v(2) v(1) v(2) X = AND(A,B) X ↓ A↓ 1 C1 (A) ∗ C0 (A) ∗ C12 (B) X ↑ A↑ - C0 (A) ∗ C1 (A) ∗ C1 (B) X ↓ A↓ - C1 (A) ∗ C0 (A) ∗ C0 (B) X ↑ A↑ 0 C0 (A) ∗ C1 (A) ∗ C02 (B) X ↓ A↓ 0 X ↓ A↑ 1 X ↑ A↑ 0 X ↑ A↓ 1 X ↓ A↓ - - X ↑ A↑ - - X = OR(A,B) X = XOR(A,B) X = BUFF(A) X = INV(A) C1 (A) ∗ C0 (A) ∗ C02 (B) C0 (A) ∗ C1 (A) ∗ C12 (B) C0 (A) ∗ C1 (A) ∗ C02 (B) C1 (A) ∗ C0 (A) ∗ C12 (B) X ↓ A↑ - - X ↑ A↓ - - 644 S Ghandali et al Table Computation of dif f p for different gate types In the case of 2-input gates, we assume without loss of generality that input A is the on-path input and B is the offpath input The first two columns show the output transition, and the input transition that we are trying to propagate for this on-path input transition Columns 3–6 show the values that the output (X) and off-path input (B) must take in the first and second cycles to propagate the desired transition The final column shows the formula to compute dif f p in terms of the controllability of the off-path input and observability of output Output trans X = AND(A,B) X B Dif f p v(1) v(2) v(1) v(2) OB1 (X) ∗ OB0 (X) ∗ C12 (B) X ↓ A↓ 1 X ↑ A↑ - OB0 (X) ∗ OB1 (X) ∗ C1 (B) X = OR(A,B) X ↓ A↓ - OB1 (X) ∗ OB0 (X) ∗ C0 (B) X ↑ A↑ 0 X = XOR(A,B) X ↓ A↓ 0 X ↓ A↑ 1 X ↑ A↑ 0 X ↑ A↓ 1 OB0 (X) ∗ OB1 (X) ∗ C12 (B) X ↓ A↓ - - OB1 (X) ∗ OB0 (X) X ↑ A↑ - - OB0 (X) ∗ OB1 (X) X ↓ A↑ - - OB1 (X) ∗ OB0 (X) X ↑ A↓ - - OB0 (X) ∗ OB1 (X) X = BUFF(A) X = INV(A) B Input trans OB0 (X) ∗ OB1 (X) ∗ C02 (B) OB1 (X) ∗ OB0 (X) ∗ C02 (B) OB1 (X) ∗ OB0 (X) ∗ C12 (B) OB0 (X) ∗ OB1 (X) ∗ C02 (B) Montgomery Ladder To be able to compute the exact attack complexity the details of the Montgomery Ladder are important to determine how many manipulations are performed in each step Algorithms and describe the details of the assumed Montgomery Ladder implementation Computing the Failure Probability of a Scalar Multiplication In this subsection we describe how the failure probability of a Montgomery Ladder Algorithm Montgomery Ladder Input: A 255-bit scalar s and the x-coordinate Qx of Q ∈ E Output: c-coordinate Px of point P ∈ E with P = s · Q X1 ← 1; Z1 ← 0; X3 ← Qx ; Z2 ← for i ← 254 downto b ← bit i of s c ← bit i − of s for i < 254 else c ← if b ⊕ c = then Swap(X1 , X2 ) Swap(Z1 , Z2 ) (X1 , Z1 , X2 , Z2 ) ← LADDERST EP (Qx , X1 , Z1 , X2 , Z2 ) 10 Px ← X1 /Z1 return Px A Design Methodology for Stealthy Parametric Trojans 645 Algorithm LADDERSTEP of the Montgomery Ladder (for curve 25519) 10 Input: Qx , X1 , Z1 , X2 , Z2 Output: X1 , Z1 , X2 , Z2 T1 ← X2 + Z2 X1 ← X2 − Z Z ← X1 + Z X1 ← X1 − Z T1 ← T1 · Z2 X2 ← X2 · Z Z2 ← Z2 · Z2 X1 ← X1 · X1 T2 ← Z2 − X1 Z1 ← T2 · a24 11 12 13 14 15 16 17 18 19 Z ← Z + X1 Z1 ← T2 · Z1 X1 ← Z · X1 Z2 ← T1 − X2 Z2 ← Z2 · Z2 Z ← Z · Qx X2 ← T1 + X2 X2 ← X2 · X2 return X1 , Z1 , X2 , Z2 scalar multiplication with schoolbook multiplication on the Trojan Multiplier can be compute To compute the probability that the computation fails we fist compute the probability that a computation does not fail As noted previously, in a 255-bit schoolbook integer multiplications with 32-bit word size, 64 multiplications are performed From this 64 multiplications, 49 multiplications are the multiplications of two 32-bit numbers, while are 32-bit times 31-bit multiplications and one 31-bit times 31-bit multiplications We again assume that only 32-bit multiplications can result in a faulty response In 42 multiplications the second operand is the same as in the previous multiplications and hence the probability that such a multiplication fails is: PM (a1 ,ab ) · PM (a0 |a1 ,b1 =b0 ) For multiplications the failure probability is: PM (a1 ,ab ) · PM (a0 ,b1 |a1 ,b1 ) The probability that no failure occurs during one Montgomery Ladder step is therefore: (1 − PM (a1 ,ab ) )42 · (1 − PM (a0 ,b1 |a1 ,b1 ) )7 A 255-bit scalar multiplication requires 254 Montgomery Ladder steps Hence the probability that a failure occurs is given by: − ((1 − PM (a1 ,ab ) )42 · (1 − PM (a0 ,b1 |a1 ,b1 ) )7 )254 646 S Ghandali et al References Genetic Algorithm http://www.mathworks.com/discovery/genetic-algorithm html Accessed 01 Feb 2016 Agrawal, D., Baktir, S., Karakoyunlu, D., Rohatgi, P., Sunar, B.: Trojan detection using IC fingerprinting In: IEEE Symposium on Security and Privacy (SP 2007), pp 296–310 (2007) Bao, C., Forte, D., Srivastava, A.: On reverse engineering-based hardware Trojan detection IEEE Trans Comput.-Aided Des Integr Circ Syst 35(1), 49–57 (2016) Becker, G.T., Regazzoni, F., Paar, C., Burleson, W.P.: Stealthy dopant-level hardware Trojans In: Bertoni, G., Coron, J.-S (eds.) CHES 2013 LNCS, vol 8086, pp 197–214 Springer, Heidelberg (2013) Biham, E., Carmeli, Y., Shamir, A.: Bug attacks In: Wagner, D (ed.) CRYPTO 2008 LNCS, vol 5157, pp 221–240 Springer, Heidelberg (2008) Biham, E., Carmeli, Y., Shamir, A.: Bug attacks J Cryptology 1–31 (2015) http://dx.doi.org/10.1007/s00145-015-9209-1 Brumley, B.B., Barbosa, M., Page, D., Vercauteren, F.: Practical realisation and elimination of an ECC-related software bug attack In: Dunkelman, O (ed.) CTRSA 2012 LNCS, vol 7178, pp 171–186 Springer, Heidelberg (2012) Chakraborty, R.S., Wolff, F., Paul, S., Papachristou, C., Bhunia, S.: MERO: a statistical approach for hardware Trojan detection In: Clavier, C., Gaj, K (eds.) CHES 2009 LNCS, vol 5747, pp 396–410 Springer, Heidelberg (2009) Eggersgl, S., Wille, R., Drechsler, R.: Improved SAT-based ATPG: more constraints, better compaction In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp 85–90 (2013) 10 Ghandali, S., Alizadeh, B., Navabi, Z.: Low power scheduling in high-level synthesis using dual-Vth library In: 16th International Symposium on Quality Electronic Design (ISQED), pp 507–511 (2015) 11 Gupta, P., Kahng, A.B., Sharma, P., Sylvester, D.: Gate-length biasing for runtimeleakage control IEEE Trans Comput.-Aided Des Integr Circ Syst 25(8), 1475–1485 (2006) 12 Heragu, K., Agrawal, V., Bushnell, M.: FACTS: fault coverage estimation by test vector sampling In: Proceedings of IEEE VLSI Test Symposium, pp 266–271 (1994) 13 Hicks, M., Finnicum, M., King, S.T., Martin, M.M., Smith, J.M.: Overcoming an untrusted computing base: detecting and removing malicious hardware automatically In: IEEE Symposium on Security and Privacy (SP 2010), pp 159–172 (2010) 14 Karri, R., Rajendran, J., Rosenfeld, K., Tehranipoor, M.: Trustworthy hardware: identifying and classifying hardware Trojans Computer 10, 39–46 (2010) 15 King, S.T., Tucek, J., Cozzie, A., Grier, C., Jiang, W., Zhou, Y.: Designing and implementing malicious hardware In: Proceedings of the 1st USENIX Workshop on Large-scale Exploits and Emergent Threats (LEET 08), pp 1–8 (2008) 16 Kulkarni, S.H., Sylvester, D.M., Blaauw, D.T.: Design-time optimization of postsilicon tuned circuits using adaptive body bias IEEE Trans Comput Aided Des Integr Circ Syst 27(3), 481–494 (2008) 17 Kumar, R., Jovanovic, P., Burleson, W., Polian, I.: Parametric Trojans for faultinjection attacks on cryptographic hardware In: 2014 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), pp 18–28 IEEE (2014) A Design Methodology for Stealthy Parametric Trojans 647 18 Lin, L., Kasper, M., Gă uneysu, T., Paar, C., Burleson, W.: Trojan side-channels: lightweight hardware Trojans through side-channel engineering In: Clavier, C., Gaj, K (eds.) CHES 2009 LNCS, vol 5747, pp 382–395 Springer, Heidelberg (2009) 19 Rajendran, J., Jyothi, V., Karri, R.: Blue team red team approach to hardware trust assessment In: IEEE 29th International Conference on Computer Design (ICCD 2011), pp 285–288, October 2011 20 Rajendran, J., Jyothi, V., Sinanoglu, O., Karri, R.: Design and analysis of ring oscillator based design-for-trust technique In: 29th IEEE VLSI Test Symposium (VTS 2011), pp 105–110 (2011) 21 Saha, S., Chakraborty, R.S., Nuthakki, S.S., Mukhopadhyay, D.: Improved test pattern generation for hardware Trojan detection using genetic algorithm and Boolean satisfiability In: Gă uneysu, T., Handschuh, H (eds.) CHES 2015 LNCS, vol 9293, pp 577596 Springer, Heidelberg (2015) 22 Sasdrich, P., Gă uneysu, T.: Implementing Curve25519 for side-channel-protected elliptic curve cryptography ACM Trans Reconfigurable Technol Syst (TRETS) 9(1), (2015) 23 Shiyanovskii, Y., Wolff, F., Rajendran, A., Papachristou, C., Weyer, D., Clay, W.: Process reliability based Trojans through NBTI and HCI effects In: NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2010), pp 215–222 (2010) 24 Sugawara, T., Suzuki, D., Fujii, R., Tawa, S., Hori, R., Shiozaki, M., Fujino, T.: Reversing stealthy dopant-level circuits In: Batina, L., Robshaw, M (eds.) CHES 2014 LNCS, vol 8731, pp 112–126 Springer, Heidelberg (2014) 25 Tang, X., Zhou, H., Banerjee, P.: Leakage power optimization with dual-Vth library in high-level synthesis In: 42nd Annual Design Automation Conference (DAC 2005), pp 202–207 (2005) 26 Waksman, A., Sethumadhavan, S.: Silencing hardware backdoors In: IEEE Symposium on Security and Privacy (SP 2011), pp 49–63 (2011) Author Index Anagnostopoulos, Nikolaos A 432 Aoki, Takafumi 538 Azarderakhsh, Reza 517 Batina, Lejla 301 Battistello, Alberto 23 Becker, Georg T 625 Bhattacharya, Sarani 602 Bilgin, Begül 194 Boit, Christian 147 Bos, Joppe W 215 Boss, Erik 171 Bruinderink, Leon Groot 323 Burian, Daniel 559 Chou, Tung 280 Chowdhury, Dipanwita Roy 581 Coron, Jean-Sébastien 23, 498 Danger, Jean-Luc De Cnudde, Thomas 194 Del Pozo, Santos Merino 40 Delvaux, Jeroen 412 Dugardin, Margaux Durvaux, Franỗois 40 Eisenbarth, Thomas Fọòler, Fabian 368 391 Gabmeyer, Sebastian 432 Ganji, Fatemeh 391 Genkin, Daniel 346 Ghandali, Samaneh 625 Goudarzi, Dahmun 457 Greuet, Aurélien 498 Grosso, Vincent 61, 171 Gu, Dawu 412 Guajardo, Jorge 85 Guilley, Sylvain Gulmezoglu, Berk 368 Güneysu, Tim 171 Heninger, Nadia 346 Hiller, Matthias 412 Holcomb, Daniel 625 Homma, Naofumi 538 Hubain, Charles 215 Hülsing, Andreas 323 İnci, Mehmet Sinan 368 Irazoqui, Gorka 368 Jain, Shalabh 85 Järvinen, Kimmo 517 Kammerstetter, Markus 559 Kastner, Wolfgang 559 Katzenbeisser, Stefan 432 Kudera, Christian 559 Lange, Tanja 323 Leander, Gregor 171 Lohrke, Heiko 147 Longa, Patrick 517 López, Julio 259 Michiels, Wil 215 Miele, Andrea 517 Moradi, Amir 171 Morioka, Sumio 538 Muellner, Markus 559 Mukhopadhyay, Debdeep 602 Najm, Zakaria Nikov, Ventzislav 194 Nikova, Svetla 194 Nürnberger, Stefan 106 Oliveira, Thomaz 259 Paar, Christof 625 Poussier, Romain 61 Prouff, Emmanuel 23, 498 Pulkus, Jürgen 479 650 Author Index Renes, Joost 301 Reparaz, Oscar 194 Rijmen, Vincent 194 Rioul, Olivier Rivain, Matthieu 457 Rodríguez-Henríquez, Francisco Rossow, Christian 106 Tajik, Shahin 147, 391 Teuwen, Philippe 215 Ueno, Rei 538 259 Saha, Dhiman 581 Saleem, Muhammad Umair 432 Schaller, André 432 Schneider, Tobias 171 Schwabe, Peter 301 Seifert, Jean-Pierre 147, 391 Smith, Benjamin 301 Srivastava, Ankur 127 Standaert, Franỗois-Xavier 40, 61 Sunar, Berk 368 Szefer, Jakub 432 Verbauwhede, Ingrid 412 Vivek, Srinivas 479 Xie, Yang 127 Xiong, Wenjie 432 Yarom, Yuval 323, 346 Yener, Bülent 237 Yu, Meng-Day (Mandel) 412 Zeitoun, Rina 23, 498 Zonenberg, Andrew 237 ... 030 2-9 743 ISSN 161 1-3 349 (electronic) Lecture Notes in Computer Science ISBN 97 8-3 -6 6 2-5 313 9-6 ISBN 97 8-3 -6 6 2-5 314 0-2 (eBook) DOI 10.1007/97 8-3 -6 6 2-5 314 0-2 Library of Congress Control Number: 20169 46628... Gierlichs Axel Y Poschmann (Eds.) • Cryptographic Hardware and Embedded Systems – CHES 2016 18th International Conference Santa Barbara, CA, USA, August 1 7–1 9, 2016 Proceedings 123 Editors Benedikt... June 2016 Benedikt Gierlichs Axel Y Poschmann CHES 2016 18th Conference on Cryptographic Hardware and Embedded Systems Santa Barbara, California, USA August 1 7–1 9, 2016 Sponsored by the International

Ngày đăng: 14/05/2018, 10:56

Từ khóa liên quan

Mục lục

  • Preface

  • CHES 2016

  • Contents

  • Side Channel Analysis

  • Correlated Extra-Reductions Defeat Blinded Regular Exponentiation

    • 1 Introduction

    • 2 State of the Art of Extra-Reductions Probabilities

      • 2.1 Montgomery Modular Multiplication: Definitions and Notations

      • 2.2 A Bias to Differentiate a Multiply from a Square

      • 3 A Bias to Test the Dependency of Operations

        • 3.1 Principle of Correlated Extra-Reductions

        • 3.2 Methodology to Analyze the Bias

        • 3.3 Mathematical Derivations

        • 4 Exploiting the Bias Using Our Attack

        • 5 Experimental Results

          • 5.1 Simulations

          • 5.2 Experimental Detection of Extra-Reductions

          • 5.3 Conclusions on Experiments

          • 6 Conclusion

          • A Analysis of Extra-Reduction in OpenSSL and MbedTLS Source Codes

          • References

          • Horizontal Side-Channel Attacks and Countermeasures on the ISW Masking Scheme

            • 1 Introduction

            • 2 Preliminaries

            • 3 Secure Multiplication Schemes

Tài liệu cùng người dùng

  • Đang cập nhật ...

Tài liệu liên quan