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4 Memory system-Multilevel Memories, Cache (Memory), Virtual Memory ??? [2] • • • Memory The storage area in which programs are kept when they are running and that contains the data needed by the running programs dynamic random access memory (DRAM) Memory built as an integrated circuit; it provides random access to any location dual inline memory module (DIMM) A small board that contains DRAM chips on both sides (SIMMs have DRAMs on only one side.) [2] ??? [2] • • • cache memory A small, fast memory that acts as a buffer for a slower, larger memory static random access memory (SRAM) Also memory built as an integrated circuit, but faster and less dense than DRAM SRAM is faster but less dense, and hence more expensive, than DRAM volatile memory Storage, such as DRAM, that Retains data only if it is receiving power ??? [2] • • nonvolatile memory A form of memory that retains data even in the absence of a power source and that is used to store programs between runs Magnetic disk is nonvolatile main memory Also called primary memory Memory used to hold programs while they are running; typically consists of DRAM in today’s computers ??? [2] • • • secondary memory Nonvolatile memory used to store programs and data between runs; typically consists of magnetic disks in today’s computers magnetic disk Also called hard disk A form of nonvolatile secondary memory composed of rotating platters coated with a magnetic recording material flash memory A nonvolatile semiconductor memory It is cheaper and slower than DRAM but more expensive and faster than magnetic disks ???[3] • Method of accessing units of data [page 113] – Sequential access – Direct access – Random access – Associative • Performance parameters of memory – Access time (latency) – Memory cycle time – Transfer rate Memory • • • • a cost per bit b capacity c access time d frequency of access of the memory by the processor [3.8th] Early Read-Only Memory Technologies Punched cards, From early 1700s through Jaquard Loom, Babbage, and then IBM Punched paper tape, instruction stream in Harvard Mk Diode Matrix, EDSAC-2 µcode store IBM Balanced Capacitor ROS IBM Card Capacitor ROS Early Read/Write Main Memory Technologies Babbage, 1800s: Digits stored on mechanical wheels Williams Tube, Manchester Mark 1, 1947 Mercury Delay Line, Univac 1, 1951 Also, regenerative capacitor memory on Atanasof-Berry computer, and rotating magnetic drum memory on IBM 650 MIT Whirlwind Core Memory DRAM Packaging (Laptops/Desktops/Servers) ~7 Clock and control signals Address lines DRAM multiplexed chip row/column address ~12 Data bus (4b,8b,16b,32b) ▪ DIMM (Dual Inline Memory Module) contains multiple chips with clock/control/address signals connected in parallel (sometimes need bufers to drive signals to all chips) ▪ Data pins work together to return wide word (e.g., 64-bit data bus using 16x4-bit parts) 9/15/2016 CS152, Fall 2016 16 DRAM Operation ▪ ▪ ▪ ▪ ▪ ▪ Three steps in read/write access to a given bank Row access (RAS) – – – – decode row address, enable addressed row (often multiple Kb in row) bitlines share charge with storage cell small change in voltage detected by sense amplifiers which latch whole row of bits sense amplifiers drive bitlines full rail to recharge storage cells Column access (CAS) – – – – decode column address to select small number of sense amplifier latches (4, 8, 16, or 32 bits depending on DRAM package) on read, send latched bits out to chip pins on write, change sense amplifier latches which then charge storage cells to required value can perform multiple column accesses on same row without another row access (burst mode) Precharge – charges bit lines to known value, required before next row access Each step has a latency of around 15-20ns in modern DRAMs Various DRAM standards (DDR, RDRAM) have diferent ways of encoding the signals for transmission to the DRAM, but all share same core architecture 9/15/2016 CS152, Fall 2016 17 200MHz Double-Data Rate (DDR2) DRAM ▪ [ Micron, 256Mb DDR2 SDRAM datasheet ] Clock Row Column Precharge Row’ Data 400Mb/s Data Rate 9/15/2016 CS152, Fall 2016 18 CPU-Memory Botleneck CPU Memory Performance of high-speed computers is usually limited by memory bandwidth & latency ▪ Latency (time for a single access) – Memory access time >> Processor cycle time ▪ Bandwidth (number of accesses per unit time) if fraction m of instructions access memory · · 9/15/2016 1+m memory references / instruction CPI = requires 1+m memory refs / cycle (assuming RISC-V ISA) CS152, Fall 2016 19 Processor-DRAM Gap (latency) µProc 60%/year 1000 CPU Processor-Memory Performance 100 Performance Gap: (growing 50%/yr) DRAM 10 7%/year DRAM 2000 1999 1998 1997 1996 1995 1994 1993 1992 1991 1990 1989 1988 1987 1986 1985 1984 1983 1982 1981 1980 Time Four-issue 3GHz superscalar accessing 100ns DRAM could execute 1,200 instructions during time for one memory access! 9/15/2016 CS152, Fall 2016 20 Physical Size Afects Latency CPU CPU Small Memory 9/15/2016 Big Memory ▪ Signals have further to travel ▪ Fan out to more locations CS152, Fall 2016 21 Exercise [2] CACHE MEMORY PRINCIPLES [3] • Cache memory is intended to give memory speed approaching that of the fastest memories available, and at the same time provide a large memory size at the price of less expensive types of semiconductor memories • [3] part 4.5 th CACHE MEMORY PRINCIPLES Example • Example 4.1 page 116 th Cache Read Operation [3 ] th ELEMENTS OF CACHE DESIGN [3 ] Cache Sizes of Some Processors INTERNAL MEMORY [3 th chapter 5] • 5.1 Semiconductor Main Memory • 5.3 Advanced DRAM Organization – Organization – DRAM and SRAM – Types of ROM – Chip Logic – Chip Packaging – Module Organization – Interleaved Memory – Synchronous DRAM – Rambus DRAM – DDR SDRAM – Cache DRAM Semiconductor Memory Types • • 1/ List all types of rom 2/ Depict the key characteristics of each types of RAMs th Table 5.1 Semiconductor Memory Types [3 ] ... regenerative capacitor memory on Atanasof-Berry computer, and rotating magnetic drum memory on IBM 650 MIT Whirlwind Core Memory Core Memory ▪ Core memory was first large scale reliable main memory – invented... nonvolatile main memory Also called primary memory Memory used to hold programs while they are running; typically consists of DRAM in today’s computers ??? [2] • • • secondary memory Nonvolatile memory. .. (number of accesses per unit time) if fraction m of instructions access memory · · 9/15/2016 1+m memory references / instruction CPI = requires 1+m memory refs / cycle (assuming RISC-V ISA) CS152,