;******************************************************************************* ; MSP430F20x2 Demo - ADC10, DTC Sample A1 32x, 1.5V, Repeat Single, DCO ; ; Description: Use DTC to sample A1 32 times with reference to internal 1.5v ; Vref Software writes to ADC10SC to trigger sample burst In Mainloop MSP430 ; waits in LPM0 to save power until ADC10 conversion complete, ADC10_ISR(DTC) ; will force exit from any LPMx in Mainloop on reti ADC10 internal ; oscillator times sample period (16x) and conversion (13x) DTC transfers ; conversion code to RAM 200h - 240h P1.0 set at start of conversion burst, ; reset on completion ; ; MSP430F20x2 ; ; /|\| XIN|; | | | ; |RST XOUT|; | | ; > -|P1.1/A1 P1.0| >LED ; ; L Westlund ; Texas Instruments Inc ; May 2006 ; Built with IAR Embedded Workbench Version: 3.41A ;******************************************************************************* #include "msp430x20x2.h" ; RSEG CSTACK ; Define stack segment ; RSEG CODE ; Assemble to Flash memory ; RESET mov.w #SFE(CSTACK),SP ; Initialize stackpointer StopWDT mov.w #WDTPW+WDTHOLD,&WDTCTL ; Stop WDT SetupADC10 mov.w #CONSEQ_2+INCH_1,&ADC10CTL1 ; Repeat single channel mov.w #SREF_1+ADC10SHT_2+MSC+REFON+ADC10ON+ADC10IE,&ADC10CTL0; mov.w #30,&TACCR0 ; Delay to allow Ref to settle bis.w #CCIE,&TACCTL0 ; Compare-mode interrupt mov.w #TACLR+MC_1+TASSEL_2,&TACTL; up mode, SMCLK bis.w #LPM0+GIE,SR ; Enter LPM0, enable interrupts bic.w #CCIE,&TACCTL0 ; Disable timer interrupt dint ; Disable Interrupts mov.b #020h,&ADC10DTC1 ; 32 conversions bis.b #02h,&ADC10AE0 ; P1.1 ADC option select SetupP1 bis.b #001h,&P1DIR ; P1.0 output ; Mainloop bic.w #ENC,&ADC10CTL0 ; busy_test bit #BUSY,&ADC10CTL1 ; ADC10 core inactive? jnz busy_test ; mov.w #0200h,&ADC10SA ; Data buffer start bis.b #001h,&P1OUT ; P1.0 = bis.w #ENC+ADC10SC,&ADC10CTL0 ; Start sampling bis.w #CPUOFF+GIE,SR ; LPM0, ADC10_ISR will force exit bic.b #001h,&P1OUT ; P1.0 = jmp Mainloop ; Again ; ; TA0_ISR; ISR for TACCR0 ; clr.w &TACTL ; Clear Timer_A control registers bic.w #LPM0,0(SP) ; Exit LPM0 on reti reti ; ; ADC10_ISR; Exit LPM0 on reti ; bic.w #CPUOFF,0(SP) ; Exit LPM0 on reti reti ; ; ; COMMON INTVEC ; Interrupt Vectors ; ORG ADC10_VECTOR ; ADC10 Vector DW ADC10_ISR ORG TIMERA0_VECTOR ; Timer_A0 Vector DW TA0_ISR ORG RESET_VECTOR ; POR, ext Reset DW RESET END