DSpace at VNU: Sub-100nm Ferroelectric-Gate Thin-Film Transistor with Low-Temperature PZT Fabricated on SiO2 Si Substrate

DSpace at VNU: Sub-100nm Ferroelectric-Gate Thin-Film Transistor with Low-Temperature PZT Fabricated on SiO2 Si Substrat...

Ferroelectrics Letters Section, 42:65–74, 2015 Copyright © Taylor & Francis Group, LLC ISSN: 0731-5171 print / 1563-5228 online DOI: 10.1080/07315171.2015.1026215 Sub-100 nm Ferroelectric-Gate Thin-Film Transistor with Low-Temperature PZT Fabricated on SiO2 /Si Substrate DO HONG MINH AND BUI NGUYEN QUOC TRINH∗ Faculty of Engineering Physics and Nanotechnology, University of Engineering and Technology, Vietnam National University, Building E4, 144 Xuan Thuy, Cau Giay, Hanoi, Vietnam Communicated by Dr Deborah J Taylor (Received in final form December 9, 2014) Thin film transistor which uses an active oxide-semiconductor channel and a ferroelectric-gate insulator, so-called FGT, has wide attention for the application of a new nonvolatile memory owing to its prominent features such as simple structure, high speed and low power consumption Previously, we have reported on demonstration of the FGTs operation, but the ones developed have channel lengths (LDS ) more than 100 nm, which should be reduced for high-density storage in integration circuits In this work, a new technique has been proposed to fabricate the sub-100 nm FGT using low-temperature PZT thin film, whose source-drain gap would be mainly created from electron beam lithography, dry etching and ashing With the new technique, the memory functionality of the fabricated sub-100 nm FGTs are comparable with that of the sub-µm sized FGT In particular, the ON/OFF current ratio is about 104–105, the memory window is 2.0, 1.8 and 1.7 V, and the field-effect mobility is 0.12, 0.07 and 0.16 cm2V −1s−1 for the LDS of 100, 50, and 30 nm, respectively Keywords Electron beam lithography (EBL); thin film transistor (TFT); ferroelectric; PZT; ITO Introduction Size-downing tendency to electronic devices followed by Moore’s law has been progressively dedicated to manufacture the transistors in the integration circuit, but always brings great challenges to researchers At the present, it is a critical moment to move the plane transistors to less than 32 nm size in a mass-production requirement Recently, Intel Corporation has announced that they have succeeded to reduce transistors size from 32 nm to 22 nm by using a fin structure, but the transistors demonstrated have only 20 to 30 percent gains in efficiency and performance, which would be some difficulties in industrial aspect That is, researching and developing motivations still increase in realization of several nanometer-ordered transistors ∗ Corresponding author; E-mail: trinhbnq@vnu.edu.vn Color versions of one or more of the figures in the article can be found online at www.tandfonline.com/gfel 65 66 D H Minh and B N Q Trinh At laboratory research level, many groups have attempted to reduce the cell size in the thin-film transistor (TFT) typed-devices [1–3] It is interesting that a 3-nm sized organic TFT has been demonstrated as an excellent example [4] Note that the organic TFT is more favorable in the size minimization than the inorganic one, because of processing at the low temperature that might not cause any serious deformation Unfortunately, the performance of nanometer-sized organic TFT is normally poor, and it is sensitive with the fabrication process On the other hand, the inorganic TFT has stability with the fabrication process, and it has a high reproducibility A trade-off consideration would be opened between the organic and inorganic selection, when manufacturing nanometer-sized TFTs at a low-temperature process It is well-known that oxide-semiconductor channel-based TFTs with a channel layer such as (ZnO) [5], indium gallium zinc oxide (IGZO) [6], indium zinc oxide (IZO) [7], or indium tin oxide (ITO) [8], has been successfully demonstrated using solution-processed and low-temperature deposition methods When the gate insulator is paraelectric, TFTs require a high-operation voltage due to a small induced charge density coming from the paraelectric materials Hence, TFTs using ferroelectric layer for the gate insulator are not only able to make the operation voltage become lower by compensating a huge charge from the nature of ferroelectric materials, but also play a role of memory function Hereafter, this kind of memory device is denoted as FGT, which belongs to a group of ferrelectric field-effect transistor memory (FeFET) [9] Hitherto, we found on International Technology Roadmap for Semiconductor that the smallest size of FGT/FeFET developed is about µm [10], but we also found that the sub-1 µm ferroelectric memory has been successfully demonstrated [11], and the 60-nm FGTs with an excellent property has been reported [12] The achievement suggests that the FGT has a high potential to the scaling merit of the low-power consumption devices In this study, a new technique has been implemented to fabricate the sub-100 nm FGTs, whose channel length is defined to be 30, 50 and 100 nm, patterned basing on electron beam (EB) lithography, dry etching and ashing We point out that the new technique is promising to go further in reduction of the FGT cell size, even to several nanometers Experimental Procedures a) Preparing Layers Structure of FGT Figure 1(a) shows a schematic drawing of the layers structure in the sub-100 nm FGT First, a SiO2 /Si substrate was treated in 1% HF acid for min, and then in acetone for to remove inorganic and organic contaminations, respectively On the substrate cleaned, a 10-nm thick Ti film and 100-nm-thick Pt film were in turn deposited by using rf sputtering at a substrate temperature of 100◦ C, in order to produce a highly crystalline quality of the Pt film for the flat-gate electrode layer [13] In this step, the thin Ti film layer plays a role of enhancing adhesion between the Pt film and the SiO2 /Si substrate Second, a ferroelectric-gate PZT film with 160 nm in thickness was formed after sol-gel coating and crystallizing at 500◦ C for 30 in a pure-air atmosphere, which was mixed between oxygen and nitrogen (99.99% purity) under the gas flow ratio of 1:4 Third, the channel layer was created from a 20-nm thick ITO film, which was deposited by a sol-gel coating, and crystallized at 450◦ C for 20 in an air atmosphere These annealing processes were performed in a rapid thermal annealing furnace (RTA, ULVAC-Mila5000) Finally, Sub-100 nm Ferroelectric-Gate Thin-Film Transistor 67 Figure New technique to fabricate the sub-100 nm FGTs: (a) Layers structure of sample, (b) sub-100 nm gap patterned by EB lithography, (c) dry-etching with Ar gas only to remove Pt at the channel gap, (d) the source and drain areas patterned by photo-lithography, (e) dry-etching with Ar gas only to form the channel width, the source and drain contacts, and (f) final structure of sub-100 nm FGTs a 50-nm thick Pt film was deposited by rf sputtering to form the source/drain electrode layer b) Patterning Sub-100 nm FGTs Conventionally, lift-off or wet/dry etching process is applied to create a gap between the source and drain of the transistor structure For the lift-off process, if we use a single-layer electron beam resist, the resist remover is difficult to break the EB resist at the nanometers size after the film deposition to prepare the designed patterns This problem was essentially solved by introducing a double-layer EB resist, whose lower layer receded comparing with the upper layer at the nanometer-ordered patterns area of the electronic devices By this, the lift-off process with double resist layers becomes superior because the resist and the remover are easily contacted from each other However, using the double resist layers, when the pattern size is of several nanometers, it is critical to control exactly the shape, which is comparable with the electron-beam size, leading to the failure of the patterns formation In this study, we have developed a new technique to create a source-drain gap of 30, 50 and 100 nm, essentially basing on EB lithography, dry etching and ashing processes The details were described from Fig 1(b) to Fig 1(f) A sample with layers structure shown in Fig 1(a) was coated by a positive EB resist layer (ZEP520A), and in sequence, exposed by using EB lithography equipment (EBL, JEOL-JBX6300SJ) at Tokyo Institute of Technology, Japan From Fig 1(b), it is obvious that the smallest gap is approaching an equal to the electron-beam size in principle One notes on Figs 1(b) and (c) that the length of gaps designed is about 25 µm, in order to support to an easy alignment from the photo-lithography step of Fig 1(d) Next, inductively coupled plasma (ICP)-typed dry etching with power of 80 W, a bias power of 50 W and an Ar pressure of 1.0 Pa was carried out to remove the Pt film layer as shown in Fig 1(c), i.e to create the channel length of 68 D H Minh and B N Q Trinh Figure Optical microscope image of the sub-100 nm FGT FGT Here, we explain that when the FGT cell size is less than 100 nm, the source and drain electrodes should be thin in height, have a high conductivity, and can be easily etched in the patterning process In our case, the Pt selected has a higher conductivity than the other metals, but it is critically etched due to its chemical stability in the dry treatment It means that some strongly reactive gases such as CF4 , BCl3 or Cl2 must be usually introduced to react with Pt at the etched areas Nevertheless, we found in the new technique that the Pt could be effectively etched by controlling the bias voltage with Ar gas only, and its etching rate reached as high as 60 nm/min, even not using any reactive gases It is believed the etching with the Ar gas only is more suitable in the sub-100 nm FGT fabrication than that with reactive gases, because it does not produce any compound of Pt at the source-drain gap area, which supports to enhance the FGT performance In addition, the etching with Ar only can restrict a side-wall etch, which is favorable for sub-100 nm patterns Figures 1(d) and (e) show a formation of the channel width of the sub-100 nm FGT In this step, a negative photo-resist (OMR-85) with µm in thickness was patterned, using a common photo-lithography technique, to protect the gap, source and drain areas when the dry-etching process mentioned above was done It is noticed that the 50-nm Pt and 20-nm ITO film layers were etched together For both EB and photo resists remained after the dry-etching process, they were removed by an oxygen ashing process at a power of 50 W for As a result, we fabricated the sub-100 nm FGT as shown in Fig (f) Results and Discussion Figure shows a typical optical microscope image of a sub-100 nm FGT fabricated on a SiO2 /Si substrate, where the source, drain and gap areas were patterned and the gate electrode was flat In this figure, the region of PZT, Pt and ITO thin films surface marked is well-formed without any damages It reveals that the new technique produces successfully the desire patterns Additionally, the drain and source areas were well-aligned with the gap, and the channel width (W DS ) was determined to be µm Figure shows SEM images of the source-drain gaps of the sub-100 nm FGTs, after etching the Pt film and ashing the remaining resist For whole cases, we can see a clear Sub-100 nm Ferroelectric-Gate Thin-Film Transistor 69 Figure SEM images of the source-drain gap of the sub-100 nm FGTs: (a) 100 nm, (b) 50 nm and (c) 30 nm separation between the source and the drain areas, in which the black is the gap area and the dark is the source and drain areas We can see that, at the high scale (×100 k), the surface of source, drain and gap is really level even after dry etching and ashing process From the SEM images, the channel length of the FGTs was determined to be 100, 50 and 30 nm, which supports an evidence to fabricate successfully the sub-100 nm FGTs using the new technique as proposed in Fig Figure shows the 3D AFM image of the 100-nm FGT on a SiO2 /Si substrate One confirms again that the source-drain gap of the 100-nm FGT is about 100 nm which is similar to the SEM result observed in Fig 3(a) From Fig 4, we determined the height of the source and drain electrodes is about 50 nm with a smooth surface of Pt Yet the gap separation must be tested from the electrical measurement To verify the ferroelectric property of PZT film and the source-drain isolation after pattering process, we also designed a structure of Pt/PZT/Pt ferroelectric capacitor, which resembles the FGT structure without ITO film layer, as shown in the inset of Fig Polarization-voltage (P-V) characteristic of the PZT thin film was measured between the source/drain and the gate electrodes Figure shows the P-V hysteresis loops of the Pt/PZT/Pt capacitor, which was measured by applying a pulsed voltage between the Figure The 3D AFM image of the 100-nm FGT 70 D H Minh and B N Q Trinh Figure Polarization-applied voltage (P-V) hysteresis loops of the Pt/PZT/Pt capacitor source/drain and the gate electrodes As can be seen that the remnant polarization was 16.1 µC/cm2, and the twice-coercive voltage (2V c ) was about 2.1 V at an applied voltage of V Here, we calculated the capacitance per area unit (Cox ) of the gate insulator Cox = P/V and we derived Cox = 3.2 µCV−1cm−2 at V = V Figure shows current-voltage (I-V) characteristics, which were measured between the source and the drain electrodes to verify the gap formation from a viewpoint of electrical investigation as shown in Fig 6(a), and which were measured between the source/drain and the gate electrodes to evaluate the gate-leakage current of the FGT as shown in Fig 6(b) We can obtain from Fig 6(c) that a leakage current is lower than 10−8 A at an applied voltage of V from the gate to the source/drain electrode Also, we can see that a current flowed from the source to the drain is lower than 10−5 A, which is mostly contributed from PZT surface, but not from a leakage current of the PZT film This is because a PbO thin layer is always existed on the PZT film surface [13], which produces a surface conduction breakdown if the voltage applied between source and drain is too high In addition, some Pt particles diffuse into the PZT film or the implanted Ar ions make the PZT surface charge up during the etching/sputtering process These reasons might contribute to a high current as measured above, but it was still acceptable to the sub-100 nm FGT fabrication, if the voltage is not set much higher than V Further improvement is required by optimizing on the etching process when doing the gap isolation to avoid a high value of OFF current Figure shows the transfer characteristics of the sub-100 nm FGTs, for which the channel lengths were various with respect to 100, 50 and 30 nm while the channel width of µm was unchanged In this measurement, the gate voltage (V G ) was double-scanned from −5 V to V with a step of 0.1 V, and the bias voltage between the drain and source (V DS ) was kept of 1.0 V, in order to maintain the low OFF-state current according to the result of Fig 6(c) From Fig 7, the transfer characteristics exhibited clearly memory functionality with a counterclockwise hysteresis loop, typical n-type transistor, whose the ON/OFF current ratio was approximately in range of 104 to 105, and the memory windows were 2.0, 1.8 Sub-100 nm Ferroelectric-Gate Thin-Film Transistor 71 Figure Current-voltage (I-V) characteristics measured between: (a) the source/drain and the gate electrodes, and (b) the source and the drain electrodes of the Pt/PZT/Pt capacitor Figure Transfer characteristics of the fabricated FGTs whose channel length of 100, 50 and 30 nm, measured with V DS of 1.0 V 72 D H Minh and B N Q Trinh Figure Output characteristics of the fabricated FGTs whose channel length of (a) 100 nm, (b) 50 and (c) 30 nm and 1.7 V for the 100-nm, 50-nm and 30-nm FGTs, respectively These values are quite matching with the 2V c estimated from Fig 5, which means that the memory window can be adjusted by improving the PZT film quality and ITO/PZT interface, if necessary The derivation is worse than the FGT having a long channel length as we reported before [9] The degradation might be originated from the short-channel effect when the LDS approaches to the nanometers order [1] Figure shows output characteristics of the FGTs fabricated with the channel lengths of 100, 50 and 30 nm In this measurement, the V G was swept from to V with a step of V while the V DS scanned from to 1.5 V From Fig 8, we obtain an easy saturation behavior for the LDS = 100 and 50 nm, but a hard saturation for the LDS = 30 nm This tendency is a bit related to a short-channel effect of TFT when the channel length is reduced [1] Also, the saturated ON current is slightly increased with shortening the channel length For instance, at V G = 7V and V DS = 1.5 V, the saturated ON current was 0.19, 0.21 and 0.56 mA for the channel length of 100, 50 and 30 nm, respectively The field-effect mobility (µFE ) was calculated from the saturation region of Fig by using the formula as follows: µFE = ID (WDS /2LDS ) Cox · (VG − VT )2 −1 , where the saturated ON current I D = 0.19, 0.21 and 0.56 mA for the LDS = 100, 50 and 30 nm, respectively The channel width W DS = µm, ferroelectric capacitor Cox = 3.2 µCV−1cm−2, V G = V, V T = 0V for LDS = 100, 50 nm, and V T = V for LDS = 30 nm Using these parameters, we estimated the µFE to be 0.12, 0.07 and 0.16 cm2V−1s−1, in turn, Sub-100 nm Ferroelectric-Gate Thin-Film Transistor 73 for LDS = 100, 50, and 30 nm The µFE is much lower than that of polycrystalline silicon TFT [14], but comparable to that of an amorphous silicon TFT [15] Conclusion In summary, we proposed a new technique to fabricate the sub-100 nm FGT whose sourcedrain gap was essentially patterned by using electron beam lithography followed with a dry etching with Ar gas only and an ashing process From SEM observation, it is convinced that the sub-100 nm FGTs were successfully fabricated with the channel lengths of 30, 50 and 100 nm All fabricated sub-100 nm FGTs exhibited memory functionality with ON/OFF current ratio of about 4-5 orders The memory window and the field-effect mobility were extracted about 2.0, 1.8 and 1.7 V, and 0.12, 0.07, and 0.16 cm2V−1s−1 for the channel lengths of 100, 50, and 30 nm, respectively The achievement brings a sufficient contribution not only to realize oxide-based FGT downing to several nanometers, but also to substitute Si-based TFTs in the future Acknowledgments The authors would gratefully appropriate the measurements from Japan Science and Technology Agency, ERATO, Shimoda Nano-Liquid Process Project, and the EB lithography collaborated with Tokyo Institute of Technology Funding This research is funded by Vietnam National Foundation for Science and Technology Development (NAFOSTED) under grant number 103.02-2012.81, and has been supported by Vietnam National University, Hanoi (VNU), under Project No QG.14.08 References I Shong, S Kim, H Yin, C J Kim, J Park, S Kim, H S Choi, E Lee, and Y Park, Short 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may print, download, or email articles for individual use  ... flat-gate electrode layer [13] In this step, the thin Ti film layer plays a role of enhancing adhesion between the Pt film and the SiO2 /Si substrate Second, a ferroelectric-gate PZT film with. .. demonstrated using solution-processed and low-temperature deposition methods When the gate insulator is paraelectric, TFTs require a high-operation voltage due to a small induced charge density... schematic drawing of the layers structure in the sub-100 nm FGT First, a SiO2 /Si substrate was treated in 1% HF acid for min, and then in acetone for to remove inorganic and organic contaminations,