A 100-μW Wake-up Receiver for UHF Transceiver Phong Nguyen Thanh1, Khanh Nguyen Tuan2, Xuan Mai Dong3 RF Department 1, - Integrated Circuit Design Research and Education Center (ICDREC), Ho Chi Minh City University of Technology (HCMUT), Vietnam National University, Ho Chi Minh-City, Vietnam E-mail: phong.nguyenthanh@icdrec.edu.vn, khanh.nguyentuan@icdrec.edu.vn, maidongxuan89@gmail.com Abstract— A wake-up receiver may be used in UHFTransceiver to control duty cycle However, its power dissipation must be extremely low to minimize the power consumption of the overall chip This paper describes the design of a sub-GHz receiver using the “uncertain-IF” architecture, which combines Passive Mixer and a ring oscillator as the RF LO The wake-up receiver is implemented in 180 nm CMOS technology to achieve a sensitivity of -55 dBm at 50 kbps with 100 μW power consumption from the V supply Keywords—CMOS; Transceiver, low IF Wake-up receiver, RFIC, Tx Mode Rx Mode Wake-up Mode Tx Request to send Data Receiver Data out Tx Node Rx Node Active receiver Tx Monitor Rx Monitor ACK Data Timer Timer (a) UHF Tx Mode Rx Mode I INTRODUCTION UHF-Transceivers are often used to collect data, such as power meter, water meter It requires highly integrated electronics for reducing size and cost, combined with low power consumption for extending battery life In order to reduce power consumption, the transceivers must spend most of the time in a low-power sleep mode In order to communicate, the transmitter must have a method for activating the receiver, introducing a challenge for synchronization There are several ways of solving this problem A synchronous protocol (Figure (a)) can be implemented by maintaining a global clock across all receivers and assigning time-slots to individual receivers The synchronous methods exhibit a clear trade-off between power consumption and latency In order to break this trade-off, a fully asynchronous protocol can be implemented using a dedicated auxiliary receiver called a wake-up receiver The Wake-up receiver (WuRx) continuously monitors the channel for requests and activates the receiver (Figure (b)) Because the WuRx is listening continuously, latency is reduced substantially The WuRx is not duty-cycled, however, so its active power consumption must be very low to avoid dominating the overall average power of the chip In this paper, we present a receiver designed specifically for the wake-up application The organization of this paper is as follows Section II explores Wake-up Receiver topologies And next, this paper presents the proposed circuit (Section III) Section IV presents simulation results Finally, Section V summarizes the work and places it in context with other research on low power wireless receivers Wake-up Mode Data Receiver Data out Active receiver Wake-up Receiver Tx Monitor Tx Request to send Tx Node ACK Rx Node Data Wake-up Main receiver (b) Figure Comparison of (a) protocol-based duty-cycling and (b) wake-up duty-cycling II SYSTEM ARCHITECTURE All off wireless receivers use one of the frequency conversion architecture The selection of frequency conversion architecture type based on careful frequency planning, the bandwidth of the signal at a low frequency and the stability of the frequency of the local oscillator For example, the homodyne architecture utilizes one down-conversion operation The RF signal is converted to the intermediate frequency (IF) with high accuracy LO The IF signal is filtered and amplified with a fixed frequency filter But, the weakness of this architecture is LO leakage, DC offsets and image signal And now, most wireless receivers utilize “low-IF” architecture to reduce the DC offset, meanwhile using Poly-phase filter to reject the image signal [1] (Figure 2) The advantage of frequency conversions is that the gain and selectivity can be effectuated at low frequency, leading to lower power consumption and improve the performance [2] IF A D C PPF M at ch ing Net work ED IF LNA S A W IF A D C VRef Ring oscillator Figure The “uncertain-IF” architecture Figure Low-IF Architecture The power consumption is often limited by RF oscillator The high accuracy and phase noise of frequency require a resonant LC oscillator With an LC oscillator, the limitation of the quality factor passive components leads to the power consumption of a few hundred microwatts [3] In had mentioned only the minimum power consumption to achieve the RF oscillation frequency, without consideration to the accuracy and phase noise Of course, the stability of the oscillator frequency is very important for the frequency conversion architecture [4] And the ring oscillator is known to have lower frequency stability than LC oscillator With designing the low-power Wake-up receiver, the “uncertain-IF” architecture is used to relax the specifications of phase noise and the accuracy of frequency, suitable for using a free-running ring oscillator for LO generation The “uncertainIF” architecture is presented in Figure The wake-up Receiver is using in UHF Transceiver System, so it can use the SAW filter of the UHF system The desired signal is first filtered at the front-end by SAW filter to remove the image signal It is mixed with a low accuracy LO In fact, the LO needs to ensure that the IF signal in a predetermined frequency band The signal is then amplified at this IF frequency After that, envelope detector converts the IF signal to DC Finally, the DC signal is compared with a reference voltage to convert to Digital Signal Note that the use of envelope detector will limit the receiver to detect the amplitude-modulated signal, most commonly on-off keying (OOK) The sensitivity of this wake-up receiver can be calculated by the simple equation for path loss Ls: ߣ ͳ ݏܮൌ ሺ ሻଶ ሺ ሻ Ͷߨ ݀ where ߣ: the wavelength of the carrier frequency, d: the link distance, and n is the empirical path loss exponent We will have the sensitivity of -55 dBm if the transmitter output power was 10dBm, ߣ ൌ ͵Ǥͷܿ݉, n=3 and the distance requirement at least 20 meters [5] III CIRCUITS DESIGN A block diagram of the complete Wake-up receiver is shown in Fig The OOK input signal is first filtered by the SAW filter After a matching network for maximum power transfer, the signal will downconvert to IF signal by the mixer and LO signal from Ring – Oscillator The resulting IF signal is amplified with a gain block covering the entire IF range and finally converted to Digital Signal by Envelope Detector and Comparator In each receiver block, the main goal of reducing the power consumption to promote the simplicity of circuit design To reduce power, all block is optimized to operate from a single 1V supply A Mixer The signal input of this Wake-up receiver is 408 MHz, so the amplifier at this frequency will make a lot of power consumption So the mixer was the first block on this system to convert the signal from RF to IF This mixer was designed using the single balanced active mixer architecture as Figure The transistor M1 was the RF input and the LO signal was supplied by the M2 transistor R1 C1 Out LO M2 In M1 Figure Single balance active mixer was designed in this paper B Ring Oscillator The ring oscillator which was designed at 398 MHz as Figure The stages of the inverter and capacitor of load were the main blocks in this schematic The LO signal at the output will be supplied to the LO port of Mixer for the down-conversion signal of IF signal To solve the problem of suffers from the temperature and process variation, this ring oscillator used bits [0:2] for calibration the value of the capacitor With the variation of 1V supply voltage, the LDO was designed to make the voltage stable Out bit0 bit1 M2 M1 bit2 In+ In- Figure The design of ring oscilator at 398 MHz of this paper C IF-Amplifier As described in the architecture design, the IF-Amplifier must provide gain across 40MHz bandwidth With bandwidth requirement, the IF-amplifier should use a wideband differential pair with resistive loads For operating with the low supply voltage, a multi-stage architecture is chosen Differential pair gain stages optimized for the maximum gain-bandwidth product, each stage provides a gain of about 10dB The input signal from the mixer is single-ended as shown in Figure 6, the differential pair devices are sized (3.4/0.5) μm/μm The bias current of all stage is controlled via a single voltage, which is shared among all stages to reduce power consumption Out Vbias Cx Figure The Schematic of Envelope Detector E Comparator In the Envelop Detector, the output signal is attenuated For reconstructing signal, the comparator is used to compare the signal with a reference voltage The comparator uses a preamplifier with 84dB gain as figure below Vref Out- In+ vbias Out+ Cx vbias In- Out- Out+ In+ In- Vbias Vin Vbias Pre Vin Buffer Out Vbias Vref Out vbias Pre-Amplifier Figure Schematic of IF-Amplifier In the first, third and fifth stages, the current source is slip into two halves by a capacitor Cx of 8pF The simulated frequency response of the complete IF amplifier is shown in Figure 10 D Envelope Detector The envelope detector circuit is designed with a differential pair biased in weak inversion with 1.3μA of current per side for maximum nonlinearity The simplified schematic of the Envelope Detector is shown in When a differential IF signal drives the gates of M1 and M2, the nonlinear bias point shift appears at the drain of the current source, converting the IF signal to DC signal A 4.8 pF capacitor at the output filters any feedthrough from the IF signal with a baseband bandwidth of about 700 kHz Buffer Figure Schematic of Comparator IV SIMULATION RESULTS In “uncertain-IF” architecture, the LO frequency from free running Ring Oscillator is very important Figure shows the simulation results of the frequency of the LO signal with temperatures ranging from 0oC to 85oC and the process By changing 3-bits calibration, the variation of ring oscillator can be controlled from 355MHz to 400MHz At room temperature (27oC), the frequency of LO signal is 381.4MHz With the frequency of the RF signal is 408MHz, the frequency of the IF signal will be in the range [8MHz – 53MHz] As mentioned above, the IF signal will be amplified by IFamplifier The frequency response of IF-Amplifier is shown in Figure 10 The maximum gain of IF-Amplifier is 56.5dB and the gain of the IF signal is in the range [47dB – 54.6dB] The gain at LO frequency is approximately 0dB After that, the signal will be envelope detector and compare with a reference voltage to reconstruct the signal The results of transient simulation from RF signal to Output signal are shown in Figure 11 And the important parameters to assess the ability of the Wake-up circuit is the power consumption The circuit consumes only 95μA with a 1V supply consumes more the power but using 1V supply In the future, this receiver needs a Frequency calibration to reduce the frequency deviation of the Ring-Oscillator TABLE I UNCERTAIN-IF RECEIVER PERFORMANCE SUMMARY Power supply Carrier frequency/Modulation Power consumption Mixer IF-Amplifiers LO Envelope detector Comparator Total Data rate (kbps) Power sensitivity Figure The frequency of ring oscillator with process and temperature variation Comparator 20.5% Envelope Detector 2.7% 1V 408MHz/OOK 25μA 29.7 μA 19.5 μA 2.6 μA 19.8 μA 96.6 μA 50-200 -55dBm Mixer 25.9% LO 20.2% IFAmplifier 30.7% Figure 12 Uncertain-IF receiver power consumption (%) Figure 10 The frequency response of IF-Amplifier ACKNOWLEDGMENT The author wishes to thank Director Ngo Duc Hoang and Prof Dang Luong Mo for their advice Thanks to Ministry of Science and Technology, Viet Nam and VNU HCM for the grant in the form of a state-level research project with code number: DAKHCN.2014/DT-03 REFERENCES Figure 11 The transient simulation results of Wake-up Receiver V CONCLUSION This paper used an uncertain IF-architecture to design the low power wake-up application The power consumption of all block is shown in Table Compare to [3], this receiver [1] [2] [3] [4] [5] B Razavi, RF Transmitter Architectures and Circuits, IEEE, 1999 B Razavi, RF Microelectronics, 2nd edition, Prentice Hall, 2011 N M Pletcher, "A 52 uW Wake-up Receiver with -72dBm Sensitivity using an Uncertain-IF Architecture," IEEE JSSC, 2009 A Hajimiri, S Limotyrakis, and T Lee, "Jitter and phase noise in ring oscillators," IEEE J Solid-State Circuits, vol 34, p 790–804, Jun 1999 Nathan Pletcher, Jan M Rabaey, "Ultra Low Power Receivers for Wireless Sensor Networks," the University of California at Berkeley, May 2008 ... operating with the low supply voltage, a multi-stage architecture is chosen Differential pair gain stages optimized for the maximum gain-bandwidth product, each stage provides a gain of about... low-power Wake- up receiver, the “uncertain-IF” architecture is used to relax the specifications of phase noise and the accuracy of frequency, suitable for using a free-running ring oscillator for LO... shift appears at the drain of the current source, converting the IF signal to DC signal A 4.8 pF capacitor at the output filters any feedthrough from the IF signal with a baseband bandwidth of about