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Allegro® User Guide: Getting Started with Physical Design Product Version 16.6 October 2012 Managing the Database This chapter provides information about database compatibility and analysis, script and SkIll compatibility, and the package integrity tool, including Database Compatibility Across Platforms Database Compatibility with Previous Software Releases Database UPREV (DBDoctor) Saving - Partial Versus Full Database Consistency Checks Script Compatibility SKILL Compatibility APD and SiP: Using the Package Design Integrity Tool Database Compatibility Across Platforms Databases are compatible across all configurations on all platforms uses the same database format for all versions of on all platforms, so no conversion is necessary to move between them Database Compatibility with Previous Software Releases Allegro databases are backward-compatible with their major version number (the number to the left of the dot) This means that databases created in or upreved to any revision within a major version (for example, to 14.1) can migrate between revisions of that version You cannot save any major version to an earlier one, such as 15.x to 14.x, 14.x to 13.x, and so on Database UPREV (DBDoctor) Databases are automatically upreved from earlier software versions The Windows version of the layout editor cannot uprev designs created prior to Release 10.0 Databases from earlier versions must be upreved on UNIX (to at least version 10.0) before they can be used on Windows In Release 14.2, databases more than one release removed can be upreved to the current release by running DBDoctor You can run DBDoctor by typing: dbdoctor at the command prompt dbdoctor at your operating system prompt uprev_overwrite at your operating system prompt DBDoctor can also: Analyze and fix database problems Eliminate duplicate vias Perform batch design rule checking (DRC) Saving - Partial Versus Full Database Consistency Checks When you save a design, the layout editor executes a partial database consistency check by default, in essence, a quick check The dbsave_full_check environment variable indicates to the database save utility when to a full check rather than a quick check A number of 1, or specifies that each time a design is saved, execute a full check If you set the variable to 100, then every 100 checks, a full check occurs For example, to set the dbsave_full_check environment variable to a full check every five saves, at the console window prompt, type: set dbsave_full_check = If the layout editor detects errors, it saves the file as .SAV Note: A full database check may considerably lengthen the time required to save large databases Script Compatibility Cadence does not guarantee that scripts are 100% upwardly compatible from release to release SKILL Compatibility SKILL programs are fully compatible with the layout environment and should run without modification APD and SiP: Using the Package Design Integrity Tool The Cadence IC Packaging tools are complex, flexible tools that provide many ways to create a package substrate layout Although the tools have a built-in check for the integrity of the database, the database doctor only validates that the database is architecturally correct, not that it is structured properly for the many commands that may access it As a result, you might have run a particular feature at a time when the database was not configured to handle the request For example, if you used the IC Packaging software to interface with the signal integrity field solver, the solver may have returned incorrect results if some information in the database is missing or incorrectly configured properly The solver would run for hours, even days, before returning bad results With the new Package Design Integrity tool, you can: Save time by running integrity checks to ensure that the database is configured correctly Diagnose your design problems before calling Cadence Technical Support Customize the tool to look for problems or deviations from your company requirements that the standard tool may not consider errors See Adding Checks Using SKILL Functions See the package procedures integrity command for additional information on field descriptions and Package Design Integrity Checks The following table describes the checks that are currently included in the standard tool Any rule that the tool can automatically fix has an F suffix and, when selected, displays the rule name followed by Fixable in the right panel Rules, that the tool cannot automatically fix, display instructions on fixing the problem and reasons why the resulting database structure is an improvement General This category includes checks that may impact a wider range of commands within your package substrate layout editor, and therefore not lend themselves to inclusion in one of the more specific categories Correcting issues reported in this category may improve results obtained with multiple commands in the system If you are running checks from one or more categories, it is recommended that you also consider running these supplementary scans Defaulted Component Class (F) This class plays an important role in the component treatment within the Cadence IC Package design tools A die component, for example, may be either flip-chip or wire bond Only a wire bond die may be connected to the substrate with bond wires The following describes the usage of the component classes: IC: Die Components, flip-chip or wire bond IO: BGA components DISCRETE: Discrete components such as capacitors and resistors PLATING_BAR: Reserved for the plating bar in the design MECHANICAL: Parts with no logic, such as via structures If you assign the wrong component class to a component instance or device, it may not behave in the expected manner You cannot copy a discrete component with class IC, as the tool views it as a die A wire bonded die with class IO is drawn with balls on the pads in the Cadence 3D Design Viewer because the tool views it as a BGA component In many cases, the tool may mistakenly set the component class IC for discrete components, as any component without a class specified in the front-end tools defaults to IC class when added to the physical layout Most of the time, this tool can correct the issue by changing the class If the tool cannot deduce the proper class, it flags the component with a DRC so that you may fix it yourself using the Logic - Edit Parts command To prevent future occurrences, be sure to assign a component class when defining components in the front-end tool Die Group Membership (F) Die components in IC package designs carry additional information beyond that required for discrete, IO, or plating bar components Such information includes, but is not limited to, source IC design information and chip attachment type (wire bond versus flip-chip) When a component is changed from IC to another class, this information must be removed When a component is changed to class IC, default values need to be established If this information is missing, a die component may not be treated correctly by some parts of the tool For example, it may not show up in any die stack, or it may be viewed as a die instead of a BGA and not be properly selectable for logic assignment operations This check looks for incorrect or missing die groups If desired, it can fix the situation by adding or removing the bad information Die Symbol Orientation The orientation of a placed die symbol must be correct iso that many of the commands in the IC Packaging tools operate on it correctly If the die is oriented the wrong way, the wire bond pads will be on the wrong side of the substrate (or bumps for a flip-chip die), which can cause extraction and 3D viewing errors It can also lead to improper relationships with other elements that are part of the same die-stack The most common orientations for dies are: Wire bond: Chip up (not mirrored) on the top of the substrate Flip-chip: Chip down (mirror geometry) on the top of the substrate If the component is placed on the bottom (underneath) of the substrate, the orientation and mirror settings are reversed normally These are not the only possible orientations, however so this rule does not actually change the database The easiest way to correct these errors is to export a die text file Check the mirror pin coordinates in the y axis option on the second page of the wizard Then read the text file in again to replace the die Select the same target pad layer but pick the correct chip orientation This updates the die and reconnects any bond wires back to the pins Missing Dielectrics A dielectric layer is necessary between each pair of adjacent conductor layers These layers ensure there is no short between overlapping conductive objects on those layers When dielectric layers are absent from a design, many commands will not be able to provide accurate feedback This includes any signal integrity or power integrity extraction, most notably, but does not extend to other areas of the tool (including such simple things as calculating a via's true vertical height) You may notice that certain commands take much longer to run, as they are unable to properly resolve electrical characteristics of and between layers These layers cannot be created for you automatically by this tool They should be added through the Setup - Cross Section commmand They are not added automatically because they must be defined with the correct thickness, material, and other properties in order to ensure the accuracy of signal integrity extraction, 3D display and so on Missing Substrate Outline (F) A package design requires a substrate geometry outline shape, which defines the overall boundary of the physical design space In most cases, this is the same size as the main BGA component in the database For example, this package outline shape would not normally include the plating bar region as this is not part of the final physical package The substrate outline is used in a number of commands within the system, from routing to analysis As a result, it is important to have this boundary in your design as early as possible in the flow The BGA generator and the BGA textin wizards automatically define a substrate outline rectangle the same size as the component If this size is incorrect or you are reading the BGA from another source, it may be necessary to manually add the outline This tool can correct this issue by creating an outline which is the same size as the largest of the BGA (IO class) components in the design However, it is not able to create the rectangle if no BGA exists In this situation, a DRC is added to the design To prevent future occurrences of this error, add the substrate geometry outline to your design manually as soon as you know the design's size or use one of the BGA wizard commands to ensure its automatic creation as part of the BGA component Unidentified Valtage Nets(F) Any power and ground nets in a design should be identified as such with the appropriate properties It is not sufficient just for the pins on that net to have a use of POWER or GROUND Each net should have the VOLTAGE property (0.0v for ground, positive voltage for power) and in most cases, the RATSNEST_SCHEDULE property should be set to POWER_AND_GROUND When these properties are missing, it can cause portions of the tool to perform slowly or inaccurately, such as signal integrity extraction and electrical constraint calculations In other cases, the design ratsnests lines may appear confusing and messy because the voltage nets are being drawn with the default signal net scheduling algorithm This tool can fix these errors It will add a VOLTAGE property, with a value of 0.0v for nets having names containing the strings GND, GROUND, or VSS It will use a value of 1.5v for other nets that meet the pin number requirements It will also add a missing RATSNEST_SCHEDULE property with the POWER_AND_GROUND value The packinteg_voltage_nets_min_pins environment variable can be set in the IC_Packaging/Package_Integrity folder of the User Preferences to control the minimum number of pins before a net is considered as being power or ground Manufacturing This category includes checks for issues most likely to cause problems when you generate manufacturing output from the tools, such as generating DXF, stream, or artwork data Correcting issues reported in this category helps minimize cycles with your package foundry You can correct minor inconsistencies in the database prior to the creation of final mask data Extra Cline Segments (F) During the course designing a package substrate, most routing clines will be pushed, shoved, smoothed, or otherwise adjusted This can lead to situations where a seemingly single routing segment is actually multiple segments This can sometimes cause problems when adding fillets or generating manufacturing data You can correct this situation by running the smooth and glossing commands However, these commands can cause additional changes that you may not want in the fully-routed design Running this check scans only for consecutive segments that can be merged No other changes are performed Redundant Clines (F) During the course of designing a substrate, it is possible to create clines which are completely underneath a shape on the same layer and same net These clines are unnecessary and can confuse signal integrity calculations, etch length calculations, and more This can also be add geometries in the manufacturing data whihc are redundant and increase file size needlessly Extra clines can be safely removed by this tool without changes to the logical connectivity or the integrity of the overall database Redundant Padstacks (F) During the course of designing a substrate, it is possible to create multiple identical vias in the same location These extra vias can introduce errors in calculations involving delay and conductor length for a net, while also adding unnecessary geometries to manufacturing output formats This tool can safely remove extra instances without changing the logical connectivity or the integrity of the database To minimize the chance of this scenario occurring in future databases, ensure that the appropriate layers are visible when performing interactive etch editing operations or when placing via structures Via-Pin alignment (F) When a component is moved or replaced (ECO process, etc.) during the course of designing a substrate, vias connected to the pins of the component may no longer connect at the exact X,Y location of the pin While the two items are still connected, they are not considered aligned This may be undesirable for manufacturing and analysis reasons This check will scan for these vias Where direct connections to pins occur and the location of the via and pin are not same, a DRC error will be created at the via's X,Y location If fixing errors, the via will be moved to the pin's location and any connected clines will be stretched to the new locationto maintain connectivity Note that if multiple vias (for instance a via array) connect to the pin, none of these vias will be aligned Only pins with single via connections will be processed Signal Integrity This category includes checks for items that are most likely to cause problems when performing 10 signal integrity analysis using either a 2D or 3D field solver Correcting issues reported in this category helps minimize problems running the solvers, while also ensuring that the tools give the most accurate results possible Bad Fillet Properties (F) Routing clines, that have the FILLET property attached but are not real fillets, can cause the system to generate inaccurate results for signal integrity, routing length, and other calculations Fillets are ignored in many calculations as they not impact the electrical path, but rather are present to improve the substrate manufacturability Therefore clines, which have this property but may cause inaccurate calculation results This situation can occur when you edit routing after adding fillets to the design Adjacent cline objects on the same net may merge into a single cline object If one of the original clines has the FILLET property, this may be mistakenly inherited through this process Similar problems can occur when pasting from a subdrawing You can prevent this problem by adding fillets to your design only at the end of the design flow If you need to edit routing after you add fillets, first remove any fillets from the clines or nets in question, perform your edits, and then re-run the filleting procedures Wire Bonding 11 This category includes checks for issues related to adding and manipulating the wire bonds in your design Correcting issues reported in this category helps to ensure that you not encounter unforeseen problems when trying to adjust your wire bonds later in your design flow In many cases, these checks may also help if you are experiencing problems with the display of bond wires in the Cadence 3D Design Viewer or extracting them for the 3D field solver Dangling Bond Wires (F) Bond wires are dangling when they are not connected to valid objects, such as pins, bond fingers, and rings, on both ends Dangling bond wires not know the height of the object to which they should connect at the dangling end, which is a requirement to draw the wire accurately in the Cadence 3D Design Viewer As a result, a wire that is dangling has that end drawn to an undetermined z-axis elevation in the Cadence 3D Design Viewer This can cause further issues with any 3D-based DRC checks that you want to perform In most cases, dangling wire bond problems occur if tools other than the wirebond commands are used to modify the wire bonds in the design Using the edit vertex, move, or connect commands to modify bond wires is a primary source of this problem To minimize the odds of reoccurrence in the future, modify the wire bonds only with the commands in the Route - Wire Bond menu of the layout editor Duplicate Wire Bond Guide Paths (F) On path and orthogonal style bond finger placement requires a guide path object that the finger follows as it moves It is possible for multiple guide paths to be defined in the database which are either very close together or completely identical 12 When this situation occurs, the tool cannot tell, for a specific finger, which of the two paths should be used As a result, if some fingers associate with one overlapping guide path and some with another, the results of some push and shove operations may be undesirable, particularly when in the "shove all" placement style One manifestation of this problem is that fingers will, apparently at random, stop pushing adjacent bond fingers This situation can be easily remedied by removing the duplicate guide paths However, in a complex design, the precise guide path(s) which have more than one instance may be difficult to find This check will identify the presence of duplicate guide paths If enabled, it will remove one of the duplicate entries This rule will only delete exact duplicate paths If two paths are very close together, it will warn you of this situation, but will not remove either path, to avoid a potential incorrect change to your design that may not be noticed until late in the design flow Power/Ground Ring Configuration For a shape to be allowable as a power or ground ring during wire bond operations, the shape must be on the nearest exposed package substrate layer, and must be assigned to a power or ground net (net with VOLTAGE property) If either of these conditions is not met, then the shape will not be considered as a ring, and will subsequently be ignored during bonding operations In most cases, this situation occurs if power and ground nets are not properly identified when they are created This can be remedied by adding the voltage property (with the correct value) using the Edit ->Properties ("property edit) command or the Logic - Identify DC Nets ("identify nets") command If the ring is not on the correct layer in the substrate, this can be 13 fixed using the Edit - Z-Copy ("zcopy shape") tool Because the tool cannot automatically determine the correct net, layer, or voltage assignment, this error cannot be fixed automatically Adding Checks Using SKILL Functions You can add new categories and rules to this tool and have them operate as if they were part of the standard tool The four SKILL functions are described below Note: You need a SKILL development license if you plan to use the SKILL functions for debugging purposes packageDesignCheckAddCategory NAME packageDesignCheckAddCategory SYNOPSIS packageDesignCheckAddCategory(t_name t_bitmap t_description) ==> defstruct defining category FUNCTION This function will register a new category inside the IC Packaging tools' "package integrity" command check tree You must define a category before adding checks to it So, this function should always be called prior to packageDesignCheckAddCheck A newly added category will be inserted into the tree in alphabetically sorted order Therefore, you not need to manage the order categories are added by yourself NOTE: If the category name already exists, it will not be redefined NEEDS t_name - Name of the category of rules as it should appear in the user interface This name should be used when calling packageDesignCheckAddCheck to add specific rules t_bitmap - Name of the bitmap file which should be shown when this rule category is active in the user interface This 14 should be a full path to the bitmap or else the bitmap must be resolvable through BMPPATH t_description - The description to be displayed in the GUI when this category is highlighted RETURNS Skill defstruct defining the category SEE ALSO packageDesignCheckAddCheck packageDesignCheckAddCheck NAME packageDesignCheckAddCheck SYNOPSIS packageDesignCheckAddCheck( t_category t_name t_bitmap t_description s_runCommand g_fixable ) ==> defstruct defining check FUNCTION This function will register a new check in the specified category of the IC Packaging tools' "package integrity" command check tree You must define a category before adding checks to it So, this function should always be called after packageDesignCheckAddCategory A newly added check will be inserted into the tree in alphabetically sorted order Therefore, you not need to manage the order checks are added by yourself s_runCommand is the skill function which should be called if this rule is selected to run This function MUST adhere to the following guidelines: #1: It must take exactly one argument, which is whether to fix errors it encounters or not #2: It must return an integer value of the number of errors that were found in the database 15 #3: It must call the following functions: packageDesignCheckLogError() and packageDesignCheckDrcError() to report any errors it finds These restrictions are imposed to ensure that output is consistent across all checks run by this command interface NEEDS t_category - Name of the category this check should be placed under in the user interface tree This should be the same name as sent to packageDesignCheckAddCategory t_name - Name of the check as it should appear in the user interface This will be the name given to the rule in the resulting log file, and will be the description for any external DRCs created t_bitmap - Name of the bitmap file which should be shown when this rule check is active in the user interface This should be a full path to the bitmap or else the bitmap must be resolvable through BMPPATH t_description - The description to be displayed in the GUI when this check is highlighted This description will also be printed to the log file ahead of any violations found for this check As a result, the description should be as descriptive as possible in order to maximize its usefulness s_runCommand - A symbol representing the function to be called to check this rule See FUNCTION description for details about the required format and return value of this function g_fixable - Boolean flag to tell the user on the interface whether problems found by this check can be automatically fixed or not RETURNS Skill defstruct defining the check SEE ALSO 16 packageDesignCheckAddCategory packageDesignCheckLogError NAME packageDesignCheckLogError SYNOPSIS packageDesignCheckLogError(t_errorString g_fixed g_location) ==> nil FUNCTION This function will log an error found by this function to the log file if the log file is enabled By using this interface, you are ensuring that the API will format your message consistently NEEDS t_errorString - String to be printed to the log file This should have all variable substitutions already done and be a simple string This function will take care of any formatting necessary g_fixed - Boolean indicating whether the error was fixed by the tool g_location - Location where the error occurred, if applicable This is appended to the log entry for you and is used to let the user zoom to the error location in the design If the location is unknown or not applicable, pass nil for the location RETURNS nil SEE ALSO packageDesignCheckAddCheck packageDesignCheckDrcError packageDesignCheckDrcError NAME packageDesignCheckDrcError 17 SYNOPSIS packageDesignCheckDrcError(l_location g_dbids) ==> nil FUNCTION This function will create an external DRC marker for an error found by the currently running package integrity check The tool itself will track the rule being run so that it knows the name to use for the rule violation NEEDS l_location - Location at which to place the DRC marker g_dbids - Optional list of database object ids which are associated with this error Usually 0-2 objects are affected RETURNS nil SEE ALSO packageDesignCheckAddCheck packageDesignCheckLogError Return to top of page For support, see Cadence Online Support service Copyright © 2012, Cadence Design Systems, Inc All rights reserved 18 ... change the database The easiest way to correct these errors is to export a die text file Check the mirror pin coordinates in the y axis option on the second page of the wizard Then read the text... Although the tools have a built-in check for the integrity of the database, the database doctor only validates that the database is architecturally correct, not that it is structured properly for the. .. geometry) on the top of the substrate If the component is placed on the bottom (underneath) of the substrate, the orientation and mirror settings are reversed normally These are not the only possible