THIẾT KẾ VI MẠCH TƯƠNG TỰ

THIẾT KẾ VI MẠCH TƯƠNG TỰCHƯƠNG 2: CMOS Technology Hoàng Trang-bộ môn Kỹ Thuật Điện Tử TP.Hồ Chí Minh 12/2011 Hoàng Trang bộ môn Kỹ Thuật Điện Tử hoangtrang@hcmut.edu.vn 1... FABRICATION

Trang 1

THIẾT KẾ VI MẠCH TƯƠNG TỰ

CHƯƠNG 2: CMOS Technology

Hoàng Trang-bộ môn Kỹ Thuật Điện Tử

TP.Hồ Chí Minh 12/2011

Hoàng Trang bộ môn Kỹ Thuật Điện Tử

hoangtrang@hcmut.edu.vn

1

Trang 3

Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 3

Trang 4

Trang 5

Trang 6

Trang 7

Trang 8

CMOS Components – Transistors

Trang 10

Trang 11

Trang 12

Trang 13

Trang 14

Trang 15

Trang 16

Trang 17

Trang 18

Illustration of Photolithography ‐ Exposure

Trang 19

Positive Photoresist

Trang 20

4.) Thin oxide and gate polysilicon

5.) Lightly doped drains and sources

6.) Sidewall spacer) p

7.) Heavily doped drains and sources

8.) Siliciding (Salicide and Polycide)

9 ) Bottom metal tungsten plugs and oxide

10.) Higher level metals, tungsten plugs/vias, and oxide

11.) Top level metal, vias and protective oxide

Trang 21

FABRICATION PROCESSStep 1 – Starting Material

The substrate should be highly doped to act like a good conductor

Trang 22

FABRICATION PROCESS

Step 2 - n and p wells

These are the areas where the transistors will be fabricated

-NMOS in the p well and PMOS in the n well

NMOS in the p-well and PMOS in the n-well.

Done by implantation followed by a deep diffusion

Trang 23

FABRICATION PROCESSStep 3 – Shallow Trench Isolation

The shallow trench isolation (STI) electrically isolates one

region/transistor from another

Trang 24

FABRICATION PROCESSStep 4 – Threshold Shift and Anti-Punch Through Implants

- The natural thresholds of the NMOS is about 0V and of the PMOS is about –

1.2V An p-implant is used to make the NMOS harder to invert and the PMOS p p

easier resulting in threshold voltages balanced around zero volts.

- Also an implant can be applied to create a higher-doped region beneath the channels to prevent punch-through from the drain depletion region extending to source depletion region.

Trang 25

FABRICATION PROCESSStep 5 – Thin Oxide and Polysilicon Gates

A thin oxide is deposited followed by polysilicon These layers are removed where they are not wanted

removed where they are not wanted

Trang 26

FABRICATION PROCESSStep 6 – Lightly Doped Drains and Sources

A lightly-doped implant is used to create a lightly-doped source and drain next to the channel of the MOSFETs

and drain next to the channel of the MOSFETs

Trang 27

FABRICATION PROCESSStep 7 – Sidewall Spacers

A layer of dielectric is deposited on the surface and removed in

such a way as to leave “sidewall spacers” next to the thin oxide

such a way as to leave sidewall spacers next to the polysilicon-polycide sandwich These sidewall spacers will prevent the part of the source and drain next to the channel from

thin-oxide-becoming heavily doped

Trang 28

FABRICATION PROCESSStep 8–Implantation of the Heavily Doped Sources and Drains

Note that not only does this step provide the completed sources and drains but allows for ohmic contact into the wells and

and drains but allows for ohmic contact into the wells and

substrate

Trang 29

FABRICATION PROCESSStep 9 – Siliciding

Siliciding and polyciding is used to reduce interconnect resistivity

by placing a lowresistance silicide such as TiSi2 WSi2 TaSi2 etc

by placing a lowresistance silicide such as TiSi2, WSi2, TaSi2, etc

on top of the diffusions

Trang 30

FABRICATION PROCESSStep 10 – Intermediate Oxide Layer

An oxide layer is used to cover the transistors and to planarize (or polish >CMP) the surface

polish->CMP) the surface

Trang 31

FABRICATION PROCESSStep 11- First-Level Metal

Tungsten plugs are built through the lower intermediate oxide

layer to provide contact between the devices wells and substrate

layer to provide contact between the devices, wells and substrate

to the first-level metal

Trang 32

FABRICATION PROCESSStep 12 – Second-Level Metal

The previous step is repeated to from the second-level metal

Trang 33

FABRICATION PROCESSCompleted Fabrication

After multiple levels of metal are applied, the fabrication is completed with a thicker level metal and a protective layer to hermetically seal the circuit from the environment Note that metal is used for the upper level metal vias The chip is electrically connected by removing the protective layer over large bonding pads

top-Hoàng Trang-bộ môn Kỹ Thuật Điện Tử, 12/2011 33

Trang 34

FABRICATION PROCESSScanning Electron Microscope (SEM) of a MOSFET

cross-section

Trang 35

FABRICATION PROCESSSEM: Showing Metal Levels and Interconnect

Trang 36

FABRICATION PROCESSDSM CMOS Technology Summary

Trang 37

What is UDSM CMOS Technology?

Vindication of Moore’s Law

“The minimum feature size decreases by approximately 0.7 every two years.” y pp y y y

Minimum feature size ~25 nanometers (2012)

2006 state of the art:

- 65 nm drawn length - 35 nm transistor gate length

- 1.2 nm transistor gate oxide - 8 layers of copper interconnect

Trang 38

Example: about 65 Nanometer CMOS Technology

Trang 39

UDSM Metal and Interconnects

Trang 40

Advantages of UDSM CMOS Technology:

Trang 41

Disadvantages of UDSM CMOS Technology (for Analog)?

• Reduction in power supply resulting in reduced headroom

• Gate leakage currents

R d d ll i l i t i i i

• Reduced small-signal intrinsic gains

• Increased nonlinearity (IIP3)

• Noise and matching?

Intrinsic gain and IP3 as a function of the gate overdrive for decreasing VDS:

Anne-Johan Annema, et Al., “Analog Circuits in Ultra-Deep-Submicron CMOS,” IEEE J of Solid-State

Circuits, 2005

Trang 42

the Gate Leakage Problem?

Trang 43

Gate Leakage and fgate

Trang 44

UDSM CMOS Technology Summary

• Increased transconductance and frequency capability

Trang 45

How are PN Junctions used in CMOS?

• PN junctions are used to electrically isolate one semiconductor region from another

• PN diodes

• Creation of the thermal voltage for bandgap purposes

• Depletion capacitors – voltage variable capacitors (varactors)

Components of a PN junction:

1.) p-doped semiconductor – a semiconductor having atoms containing a lack

of electrons (acceptors) The concentration of acceptors is NA in atoms per cubic centimeter.

2.) n-doped semiconductor – a semiconductor having atoms containing an

excess of electrons (donors) The concentration of these atoms is ND in atoms

excess of electrons (donors) The concentration of these atoms is ND in atoms per cubic centimeter.

Trang 46

PHYSICAL ASPECTS OF MOS TRANSISTORS

Physical Structure of MOS Transistors in an n-well Technology

Width (W) of the MOSFET = Width of the source/drain diffusion

Length (L) of the MOSFET = Width of the polysilicon gate between the S/D diffusions

Note: the MOSFET is isolated from the well/substrate by reverse biasing the resulting

PN junction

Trang 48

Depletion Mode MOSFET

The channel is diffused into the substrate so that a channel exists between the source and drain with no external gate potential.

The threshold voltage for a depletion mode NMOS transistor will be negative (a

negative gate potential is necessary to attract enough holes underneath the gate to

negative gate potential is necessary to attract enough holes underneath the gate to cause this region to invert to p-type material).

Trang 49

Weak Inversion Operation

Trang 50

the current flow under the gate.

• Minimize the area of the source and drain to reduce bulk-source/drain capacitance.

Trang 51

LAYOUT OF MOS TRANSISTORS

Geometric Effects

Orientation:

Devices oriented in the same direction match more precisely than those

oriented in other directions

Trang 52

Diffusion and Etch Effects

• Poly etch rate variation – use dummy elements to prevent etch rate differences.

• Do not put contacts on top of the gate for matched transistors.

• Be careful of diffusion interactions for diffusions near the channel of the

MOSFET

Trang 53

Thermal and Stress Effects

• Oxide gradients – use common centroid geometry layout

• Stress gradients – use proper location and common centroid geometry layout

• Thermal gradients – keep transistors well away from power devices and use common centroid geometry layout with interdigitated transistors

Examples of Common Centroid Interdigitated transistor layout:

Trang 54

MOS Transistor Layout

Photolithographic invariance (PLI) are transistors that exhibit

identical orientation PLI comes from optical interactions between pthe UV light and the masks

Examples of the layout of matched MOS transistors:

1 E l f i t d h t lith hi i i

1 Examples of mirror symmetry and photolithographic invariance

Trang 55

Examples of the layout of matched MOS transistors (cont)

2 Two transistors sharing a common source and laid out to

hi b th h t lith hi i i d t idachieve both photolithographic invariance and common centroid

Trang 56

Examples of the layout of matched MOS transistors (cont)

3 Compact layout of the previous example

Trang 57

Types of Capacitors for CMOS Technology

Trang 58

Characterization of Capacitors

Trang 59

PN JUNCTION CAPACITORS

PN Junction Capacitors in a Well

Trang 60

PN JUNCTION CAPACITORS

PN Junction Capacitors in a Well

Trang 61

MOSFET GATE CAPACITORS

MOSFET Gate Capacitor Structure

The MOSFET gate capacitors have the gate as one terminal of

the capacitor and some combination of the source, drain, and bulk

as the other terminal

In the model of the MOSFET gate capacitor shown below, the

gate capacitance is really two capacitors in series depending on

gate capacitance is really two capacitors in series depending on the condition of the channel

Trang 62