For interrupt response time information, refer to the hardware description chapter. Note: 1. Operations on SFR byte address 208 or bit addresses 209-215 (that is, the PSW or bits in the PSW) also affect flag settings. Instructions that Affect
2-71Microcontroller Instruction SetFor interrupt response time information, refer to the hardware description chapter.Note: 1. Operations on SFR byte address 208 or bit addresses 209-215 (that is, the PSW or bits in the PSW) also affect flag settings.Instructions that Affect Flag Settings(1)Instruction Flag Instruction FlagCOVAC COVACADD X X X CLR C OADDC X X X CPL C XSUBB X X X ANL C,bit XMUL O X ANL C,/bit XDIV O X ORL C,bit XDA X ORL C,/bit XRRC X MOV C,bit XRLC X CJNE XSETB C 1The Instruction Set and Addressing ModesRnRegister R7-R0 of the currently selected Register Bank.direct8-bit internal data location’s address. This could be an Internal Data RAM location (0-127) or a SFR [i.e., I/O port, control register, status register, etc. (128-255)].@Ri8-bit internal data RAM location (0-255) addressed indirectly through register R1or R0.#data8-bit constant included in instruction.#data 1616-bit constant included in instruction.addr 1616-bit destination address. Used by LCALL and LJMP. A branch can be anywhere within the 64K byte Program Memory address space.addr 1111-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2K byte page of program memory as the first byte of the following instruction.relSigned (two’s complement) 8-bit offset byte. Used by SJMP and all conditional jumps. Range is -128 to +127 bytes relative to first byte of the following instruction.bitDirect Addressed bit in Internal Data RAM or Special Function Register.0509B-B–12/97Instruction Set Instruction Set2-72Instruction Set SummaryNote: Key: [2B] = 2 Byte, [3B] = 3 Byte, [2C] = 2 Cycle, [4C] = 4 Cycle, Blank = 1 byte/1 cycle012345670 NOP JBCbit,rel[3B, 2C]JBbit, rel[3B, 2C]JNBbit, rel[3B, 2C]JCrel[2B, 2C]JNCrel[2B, 2C]JZrel[2B, 2C]JNZrel[2B, 2C]1 AJMP(P0)[2B, 2C]ACALL(P0)[2B, 2C]AJMP(P1)[2B, 2C]ACALL(P1)[2B, 2C]AJMP(P2)[2B, 2C]ACALL(P2)[2B, 2C]AJMP(P3)[2B, 2C]ACALL(P3)[2B, 2C]2 LJMPaddr16[3B, 2C]LCALLaddr16[3B, 2C]RET[2C]RETI[2C]ORLdir, A[2B]ANLdir, A[2B]XRLdir, a[2B]ORLC, bit[2B, 2C]3RRARRCARLARLCAORLdir, #data[3B, 2C]ANLdir, #data[3B, 2C]XRLdir, #data[3B, 2C]JMP@A + DPTR[2C]4INCADECAADDA, #data[2B]ADDCA, #data[2B]ORLA, #data[2B]ANLA, #data[2B]XRLA, #data[2B]MOVA, #data[2B]5INCdir[2B]DECdir[2B]ADDA, dir[2B]ADDCA, dir[2B]ORLA, dir[2B]ANLA, dir[2B]XRLA, dir[2B]MOVdir, #data[3B, 2C]6INC@R0DEC@R0ADDA, @R0ADDCA, @R0ORLA, @R0ANLA, @R0XRLA, @R0MOV@R0, @data[2B]7INC@R1DEC@R1ADDA, @R1ADDCA, @R1ORLA, @R1ANLA, @R1XRLA, @R1MOV@R1, #data[2B]8INCR0DECR0ADDA, R0ADDCA, R0ORLA, R0ANLA, R0XRLA, R0MOVR0, #data[2B]9INCR1DECR1ADDA, R1ADDCA, R1ORLA, R1ANLA, R1XRLA, R1MOVR1, #data[2B]AINCR2DECR2ADDA, R2ADDCA, R2ORLA, R2ANLA, R2XRLA, R2MOVR2, #data[2B]BINCR3DECR3ADDA, R3ADDCA, R3ORLA, R3ANLA, R3XRLA, R3MOVR3, #data[2B]CINCR4DECR4ADDA, R4ADDCA, R4ORLA, R4ANLA, R4XRLA, R4MOVR4, #data[2B]DINCR5DECR5ADDA, R5ADDCA, R5ORLA, R5ANLA, R5XRLA, R5MOVR5, #data[2B]EINCR6DECR6ADDA, R6ADDCA, R6ORLA, R6ANLA, R6XRLA, R6MOVR6, #data[2B]FINCR7DECR7ADDA, R7ADDCA, R7ORLA, R7ANLA, R7XRLA, R7MOVR7, #data[2B] Instruction Set2-73Instruction Set Summary (Continued)Note: Key: [2B] = 2 Byte, [3B] = 3 Byte, [2C] = 2 Cycle, [4C] = 4 Cycle, Blank = 1 byte/1 cycle89A B CDEF0 SJMPREL[2B, 2C]MOVDPTR,#data 16[3B, 2C]ORLC, /bit[2B, 2C]ANLC, /bit[2B, 2C]PUSHdir[2B, 2C]POPdir[2B, 2C]MOVX A,@DPTR[2C]MOVX@DPTR, A[2C]1 AJMP(P4)[2B, 2C]ACALL(P4)[2B, 2C]AJMP(P5)[2B, 2C]ACALL(P5)[2B, 2C]AJMP(P6)[2B, 2C]ACALL(P6)[2B, 2C]AJMP(P7)[2B, 2C]ACALL(P7)[2B, 2C]2ANLC, bit[2B, 2C]MOVbit, C[2B, 2C]MOVC, bit[2B]CPLbit[2B]CLRbit[2B]SETBbit[2B]MOVXA, @R0[2C]MOVXwR0, A[2C]3MOVC A,@A + PC[2C]MOVC A,@A + DPTR[2C]INCDPTR[2C]CPLCCLRCSETBCMOVXA, @RI[2C]MOVX@RI, A[2C]4DIVAB[2B, 4C]SUBBA, #data[2B]MULAB[4C]CJNE A,#data, rel[3B, 2C]SWAPADAACLRACPLA5MOVdir, dir[3B, 2C]SUBBA, dir[2B]CJNEA, dir, rel[3B, 2C]XCHA, dir[2B]DJNZdir, rel[3B, 2C]MOVA, dir[2B]MOVdir, A[2B]6MOVdir, @R0[2B, 2C]SUBBA, @R0MOV@R0, dir[2B, 2C]CJNE@R0, #data, rel[3B, 2C]XCHA, @R0XCHDA, @R0MOVA, @R0MOV@R0, A7MOVdir, @R1[2B, 2C]SUBBA, @R1MOV@R1, dir[2B, 2C]CJNE@R1, #data, rel[3B, 2C]XCHA, @R1XCHDA, @R1MOVA, @R1MOV@R1, A8MOVdir, R0[2B, 2C]SUBBA, R0MOVR0, dir[2B, 2C]CJNER0, #data, rel[3B, 2C]XCHA, R0DJNZR0, rel[2B, 2C]MOVA, R0MOVR0, A9MOVdir, R1[2B, 2C]SUBBA, R1MOVR1, dir[2B, 2C]CJNER1, #data, rel[3B, 2C]XCHA, R1DJNZR1, rel[2B, 2C]MOVA, R1MOVR1, AAMOVdir, R2[2B, 2C]SUBBA, R2MOVR2, dir[2B, 2C]CJNER2, #data, rel[3B, 2C]XCHA, R2DJNZR2, rel[2B, 2C]MOVA, R2MOVR2, ABMOVdir, R3[2B, 2C]SUBBA, R3MOVR3, dir[2B, 2C]CJNER3, #data, rel[3B, 2C]XCHA, R3DJNZR3, rel[2B, 2C]MOVA, R3MOVR3, ACMOVdir, R4[2B, 2C]SUBBA, R4MOVR4, dir[2B, 2C]CJNER4, #data, rel[3B, 2C]XCHA, R4DJNZR4, rel[2B, 2C]MOVA, R4MOVR4, ADMOVdir, R5[2B, 2C]SUBBA, R5MOVR5, dir[2B, 2C]CJNER5, #data, rel[3B, 2C]XCHA, R5DJNZR5, rel[2B, 2C]MOVA, R5MOVR5, AEMOVdir, R6[2B, 2C]SUBBA, R6MOVR6, dir[2B, 2C]CJNER6, #data, rel[3B, 2C]XCHA, R6DJNZR6, rel[2B, 2C]MOVA, R6MOVR6. AFMOVdir, R7[2B, 2C]SUBBA, R7MOVR7, dir[2B, 2C]CJNER7, #data, rel[3B, 2C]XCHA, R7DJNZR7, rel[2B, 2C]MOVA, R7MOVR7, A Instruction Set2-74Table 1. AT89 Instruction Set Summary(1)Note: 1. All mnemonics copyrighted © Intel Corp., 1980.Mnemonic Description Byte Oscillator PeriodARITHMETIC OPERATIONSADD A,RnAdd register to Accumulator112ADD A,direct Add direct byte to Accumulator212ADD A,@RiAdd indirect RAM to Accumulator112ADD A,#data Add immediate data to Accumulator212ADDC A,RnAdd register to Accumulator with Carry112ADDC A,direct Add direct byte to Accumulator with Carry212ADDC A,@RiAdd indirect RAM to Accumulator with Carry112ADDC A,#data Add immediate data to Acc with Carry212SUBB A,RnSubtract Register from Acc with borrow112SUBB A,direct Subtract direct byte from Acc with borrow212SUBB A,@RiSubtract indirect RAM from ACC with borrow112SUBB A,#data Subtract immediate data from Acc with borrow212INC A Increment Accumulator 1 12INC RnIncrement register 1 12INC direct Increment direct byte 2 12INC @RiIncrement direct RAM 1 12DEC A Decrement Accumulator 1 12DEC RnDecrement Register 1 12DEC direct Decrement direct byte 2 12DEC @RiDecrement indirect RAM 1 12INC DPTR Increment Data Pointer 1 24MUL AB Multiply A & B 1 48DIV AB Divide A by B 1 48DA A Decimal Adjust Accumulator112Mnemonic Description Byte Oscillator PeriodLOGICAL OPERATIONSANL A,RnAND Register to Accumulator112ANL A,direct AND direct byte to Accumulator212ANL A,@RiAND indirect RAM to Accumulator112ANL A,#data AND immediate data to Accumulator212ANL direct,A AND Accumulator to direct byte212ANL direct,#data AND immediate data to direct byte 324ORL A,RnOR register to Accumulator112ORL A,direct OR direct byte to Accumulator212ORL A,@RiOR indirect RAM to Accumulator 112ORL A,#data OR immediate data to Accumulator212ORL direct,A OR Accumulator to direct byte212ORL direct,#data OR immediate data to direct byte324XRL A,RnExclusive-OR register to Accumulator112XRL A,direct Exclusive-OR direct byte to Accumulator212XRL A,@RiExclusive-OR indirect RAM to Accumulator112XRL A,#data Exclusive-OR immediate data to Accumulator212XRL direct,A Exclusive-OR Accumulator to direct byte212XRL direct,#data Exclusive-OR immediate data to direct byte324CLR A Clear Accumulator 1 12CPL A Complement Accumulator112RL A Rotate Accumulator Left 1 12RLC A Rotate Accumulator Left through the Carry112LOGICAL OPERATIONS (continued) Instruction Set2-75RR A Rotate Accumulator Right112RRC A Rotate Accumulator Right through the Carry112SWAP A Swap nibbles within the Accumulator112DATA TRANSFERMOV A,RnMove register to Accumulator112MOV A,direct Move direct byte to Accumulator212MOV A,@RiMove indirect RAM to Accumulator112MOV A,#data Move immediate data to Accumulator212MOV Rn,A Move Accumulator to register112MOV Rn,direct Move direct byte to register224MOV Rn,#data Move immediate data to register212MOV direct,A Move Accumulator to direct byte212MOV direct,RnMove register to direct byte224MOV direct,direct Move direct byte to direct 3 24MOV direct,@RiMove indirect RAM to direct byte224MOV direct,#data Move immediate data to direct byte324MOV @Ri,A Move Accumulator to indirect RAM112MOV @Ri,direct Move direct byte to indirect RAM224MOV @Ri,#data Move immediate data to indirect RAM212MOV DPTR,#data16 Load Data Pointer with a 16-bit constant324MOVC A,@A+DPTR Move Code byte relative to DPTR to Acc124MOVC A,@A+PC Move Code byte relative to PC to Acc124MOVX A,@RiMove External RAM (8-bit addr) to Acc124DATA TRANSFER (continued)Mnemonic Description Byte Oscillator PeriodMOVX A,@DPTR Move Exernal RAM (16-bit addr) to Acc124MOVX @Ri,A Move Acc to External RAM (8-bit addr) 124MOVX @DPTR,A Move Acc to External RAM (16-bit addr)124PUSH direct Push direct byte onto stack224POP direct Pop direct byte from stack224XCH A,RnExchange register with Accumulator112XCH A,direct Exchange direct byte with Accumulator212XCH A,@RiExchange indirect RAM with Accumulator112XCHD A,@RiExchange low-order Digit indirect RAM with Acc112BOOLEAN VARIABLE MANIPULATIONCLR C Clear Carry 1 12CLR bit Clear direct bit 2 12SETB C Set Carry 1 12SETB bit Set direct bit 2 12CPL C Complement Carry 1 12CPL bit Complement direct bit 2 12ANL C,bit AND direct bit to CARRY 2 24ANL C,/bit AND complement of direct bit to Carry224ORL C,bit OR direct bit to Carry 2 24ORL C,/bit OR complement of direct bit to Carry224MOV C,bit Move direct bit to Carry 2 12MOV bit,C Move Carry to direct bit 2 24JC rel Jump if Carry is set 2 24JNC rel Jump if Carry not set 2 24JB bit,rel Jump if direct Bit is set 3 24JNB bit,rel Jump if direct Bit is Not set324JBC bit,rel Jump if direct Bit is set & clear bit324PROGRAM BRANCHINGMnemonic Description Byte Oscillator Period Instruction Set2-76ACALL addr11 Absolute Subroutine Call 2 24LCALL addr16 Long Subroutine Call 3 24RET Return from Subroutine 1 24RETI Return from interrupt124AJMP addr11 Absolute Jump 2 24LJMP addr16 Long Jump 3 24SJMP rel Short Jump (relative addr)224JMP @A+DPTR Jump indirect relative to the DPTR124JZ rel Jump if Accumulator is Zero224JNZ rel Jump if Accumulator is Not Zero224CJNE A,direct,rel Compare direct byte to Acc and Jump if Not Equal324CJNE A,#data,rel Compare immediate to Acc and Jump if Not Equal324CJNE Rn,#data,rel Compare immediate to register and Jump if Not Equal324CJNE @Ri,#data,rel Compare immediate to indirect and Jump if Not Equal324DJNZ Rn,rel Decrement register and Jump if Not Zero224DJNZ direct,rel Decrement direct byte and Jump if Not Zero324NOP No Operation 1 12Mnemonic Description Byte Oscillator Period Instruction Set2-77Table 2. Instruction Opcodes in Hexadecimal OrderHex CodeNumber of BytesMnemonic Operands00 1 NOP01 2 AJMP code addr02 3 LJMP code addr03 1 RR A04 1 INC A05 2 INC data addr06 1 INC @R007 1 INC @R108 1 INC R009 1 INC R10A 1 INC R20B 1 INC R30C 1 INC R40D 1 INC R50E 1 INC R60F 1 INC R710 3 JBC bit addr,code addr11 2 ACALL code addr12 3 LCALL code addr13 1 RRC A14 1 DEC A15 2 DEC data addr16 1 DEC @R017 1 DEC @R118 1 DEC R019 1 DEC R11A 1 DEC R21B 1 DEC R31C 1 DEC R41D 1 DEC R51E 1 DEC R61F 1 DEC R720 3 JB bit addr,code addr21 2 AJMP code addr22 1 RET23 1 RL A24 2 ADD A,#data25 2 ADD A,data addrHex CodeNumber of BytesMnemonic Operands26 1 ADD A,@R027 1 ADD A,@R128 1 ADD A,R029 1 ADD A,R12A 1 ADD A,R22B 1 ADD A,R32C 1 ADD A,R42D 1 ADD A,R52E 1 ADD A,R62F 1 ADD A,R730 3 JNB bit addr,code addr31 2 ACALL code addr32 1 RETI33 1 RLC A34 2 ADDC A,#data35 2 ADDC A,data addr36 1 ADDC A,@R037 1 ADDC A,@R138 1 ADDC A,R039 1 ADDC A,R13A 1 ADDC A,R23B 1 ADDC A,R33C 1 ADDC A,R43D 1 ADDC A,R53E 1 ADDC A,R63F 1 ADDC A,R740 2 JC code addr41 2 AJMP code addr42 2 ORL data addr,A43 3 ORL data addr,#data44 2 ORL A,#data45 2 ORL A,data addr46 1 ORL A,@R047 1 ORL A,@R148 1 ORL A,R049 1 ORL A,R14A 1 ORL A,R2 Instruction Set2-784B 1 ORL A,R34C 1 ORL A,R44D 1 ORL A,R54E 1 ORL A,R64F 1 ORL A,R750 2 JNC code addr51 2 ACALL code addr52 2 ANL data addr,A53 3 ANL data addr,#data54 2 ANL A,#data55 2 ANL A,data addr56 1 ANL A,@R057 1 ANL A,@R158 1 ANL A,R059 1 ANL A,R15A 1 ANL A,R25B 1 ANL A,R35C 1 ANL A,R45D 1 ANL A,R55E 1 ANL A,R65F 1 ANL A,R760 2 JZ code addr61 2 AJMP code addr62 2 XRL data addr,A63 3 XRL data addr,#data64 2 XRL A,#data65 2 XRL A,data addr66 1 XRL A,@R067 1 XRL A,@R168 1 XRL A,R069 1 XRL A,R16A 1 XRL A,R26B 1 XRL A,R36C 1 XRL A,R46D 1 XRL A,R56E 1 XRL A,R66F 1 XRL A,R770 2 JNZ code addrHex CodeNumber of BytesMnemonic Operands71 2 ACALL code addr72 2 ORL C,bit addr73 1 JMP @A+DPTR74 2 MOV A,#data75 3 MOV data addr,#data76 2 MOV @R0,#data77 2 MOV @R1,#data78 2 MOV R0,#data79 2 MOV R1,#data7A 2 MOV R2,#data7B 2 MOV R3,#data7C 2 MOV R4,#data7D 2 MOV R5,#data7E 2 MOV R6,#data7F 2 MOV R7,#data80 2 SJMP code addr81 2 AJMP code addr82 2 ANL C,bit addr83 1 MOVC A,@A+PC84 1 DIV AB85 3 MOV data addr,data addr86 2 MOV data addr,@R087 2 MOV data addr,@R188 2 MOV data addr,R089 2 MOV data addr,R18A 2 MOV data addr,R28B 2 MOV data addr,R38C 2 MOV data addr,R48D 2 MOV data addr,R58E 2 MOV data addr,R68F 2 MOV data addr,R790 3 MOV DPTR,#data91 2 ACALL code addr92 2 MOV bit addr,C93 1 MOVC A,@A+DPTR94 2 SUBB A,#data95 2 SUBB A,data addr96 1 SUBB A,@R0Hex CodeNumber of BytesMnemonic Operands Instruction Set2-7997 1 SUBB A,@R198 1 SUBB A,R099 1 SUBB A,R19A 1 SUBB A,R29B 1 SUBB A,R39C 1 SUBB A,R49D 1 SUBB A,R59E 1 SUBB A,R69F 1 SUBB A,R7A0 2 ORL C,/bit addrA1 2 AJMP code addrA2 2 MOV C,bit addrA3 1 INC DPTRA4 1 MUL ABA5 reservedA6 2 MOV @R0,data addrA7 2 MOV @R1,data addrA8 2 MOV R0,data addrA9 2 MOV R1,data addrAA 2 MOV R2,data addrAB 2 MOV R3,data addrAC 2 MOV R4,data addrAD 2 MOV R5,data addrAE 2 MOV R6,data addrAF 2 MOV R7,data addrB0 2 ANL C,/bit addrB1 2 ACALL code addrB2 2 CPL bit addrB3 1 CPL CB4 3 CJNE A,#data,code addrB5 3 CJNE A,data addr,code addrB6 3 CJNE @R0,#data,code addrB7 3 CJNE @R1,#data,code addrB8 3 CJNE R0,#data,code addrB9 3 CJNE R1,#data,code addrBA 3 CJNE R2,#data,code addrBB 3 CJNE R3,#data,code addrBC 3 CJNE R4,#data,code addrHex CodeNumber of BytesMnemonic OperandsBD 3 CJNE R5,#data,code addrBE 3 CJNE R6,#data,code addrBF 3 CJNE R7,#data,code addrC0 2 PUSH data addrC1 2 AJMP code addrC2 2 CLR bit addrC3 1 CLR CC4 1 SWAP AC5 2 XCH A,data addrC6 1 XCH A,@R0C7 1 XCH A,@R1C8 1 XCH A,R0C9 1 XCH A,R1CA 1 XCH A,R2CB 1 XCH A,R3CC 1 XCH A,R4CD 1 XCH A,R5CE 1 XCH A,R6CF 1 XCH A,R7D0 2 POP data addrD1 2 ACALL code addrD2 2 SETB bit addrD3 1 SETB CD4 1 DA AD5 3 DJNZ data addr,code addrD6 1 XCHD A,@R0D7 1 XCHD A,@R1D8 2 DJNZ R0,code addrD9 2 DJNZ R1,code addrDA 2 DJNZ R2,code addrDB 2 DJNZ R3,code addrDC 2 DJNZ R4,code addrDD 2 DJNZ R5,code addrDE 2 DJNZ R6,code addrDF 2 DJNZ R7,code addrE0 1 MOVX A,@DPTRE1 2 AJMP code addrE2 1 MOVX A,@R0Hex CodeNumber of BytesMnemonic Operands Instruction Set2-80E3 1 MOVX A,@R1E4 1 CLR AE5 2 MOV A,data addrE6 1 MOV A,@R0E7 1 MOV A,@R1E8 1 MOV A,R0E9 1 MOV A,R1EA 1 MOV A,R2EB 1 MOV A,R3EC 1 MOV A,R4ED 1 MOV A,R5EE 1 MOV A,R6EF 1 MOV A,R7F0 1 MOVX @DPTR,AF1 2 ACALL code addrF2 1 MOVX @R0,AF3 1 MOVX @R1,AF4 1 CPL AF5 2 MOV data addr,AF6 1 MOV @R0,AF7 1 MOV @R1,AF8 1 MOV R0,AF9 1 MOV R1,AFA 1 MOV R2,AFB 1 MOV R3,AFC 1 MOV R4,AFD 1 MOV R5,AFE 1 MOV R6,AFF 1 MOV R7,AHex CodeNumber of BytesMnemonic Operands [...]... DIV (A) 15-8 ← (A)/(B) (B) 7-0 Instruction Set 2-115 SETB <bit> SJMP rel Function: Set Bit Description: SETB sets the indicated bit to one. SETB can operate on the carry flag or any directly addressable bit. No other flags are affected. Example: The carry flag is cleared. Output Port 1 has been written with the value 34H (00110100B). The following instructions, SETB C SETB P1.0 sets the carry flag to... preceding this instruction 127 bytes following it. Example: The label RELADR is assigned to an instruction at program memory location 0123H. The following instruction, SJMP RELADR assembles into location 0100H. After the instruction is executed, the PC contains the value 0123H. Note: Under the above conditions the instruction following SJMP is at 102H. Therefore, the displacement byte of the instruction. .. #data [2B] FINC R7 DEC R7 ADD A, R7 ADDC A, R7 ORL A, R7 ANL A, R7 XRL A, R7 MOV R7, #data [2B] Instruction Set 2-81 Instruction Definitions ACALL addr11 Function: Absolute Call Description: ACALL unconditionally calls a subroutine located at the indicated address. The instruction increments the PC twice to obtain the address of the following instruction, then pushes the 16-bit result onto the stack (low-order byte first)... on Port 1 to 35H (00110101B). SETB C Bytes: 1 Cycles: 1 Encoding: 11010011 Operation: SETB (C) ← 1 SETB bit Bytes: 2 Cycles: 1 Encoding: 11010010 bit address Operation: SETB (bit) ← 1 Function: Short Jump Description: Program control branches unconditionally to the address indicated. The branch destination is computed by adding the signed displacement in the second instruction byte to the PC, after... SUBB sets the carry (borrow) flag if a borrow is needed for bit 7 and clears C otherwise. (If C was set before executing a SUBB instruction, this indicates that a borrow was needed for the previous step in a multiple-precision subtraction, so the carry is subtracted from the Accumulator along with the source operand.) AC is set if a borrow is needed for bit 3 and cleared otherwise. OV is set if... The first instruction in the sequence, CJNE R7, # 60H, NOT_EQ ; . . . . . . . . ;R7 = 60H. NOT_EQ: JC REQ_LOW ;IF R7 < 60H. ; . . . . . . . . ;R7 > 60H. sets the carry flag and branches to the instruction at label NOT_EQ. By testing the carry flag, this instruction determines whether R7 is greater or less than 60H. If the data being presented to Port 1 is also 34H, then the following instruction, WAIT:... Pointer was decremented to 2FH before being loaded with the value popped (20H). Bytes: 2 Cycles: 2 Encoding: 11010000 direct address Operation: POP (direct) ← ((SP)) (SP) ← (SP) - 1 Instruction Set 2-72 Instruction Set Summary Note: Key: [2B] = 2 Byte, [3B] = 3 Byte, [2C] = 2 Cycle, [4C] = 4 Cycle, Blank = 1 byte/1 cycle 01234567 0 NOP JBC bit,rel [3B, 2C] JB bit, rel [3B, 2C] JNB bit, rel [3B, 2C] JC rel [2B,... (11001001B), register 2 holds 54H (01010100B), and the carry flag is set. The instruction, SUBB A,R2 will leave the value 74H (01110100B) in the accumulator, with the carry flag and AC cleared but OV set. Notice that 0C9H minus 54H is 75H. The difference between this and the above result is due to the carry (borrow) flag being set before the operation. If the state of the carry is not known before... is then determined by a mask byte, either a constant contained in the instruction or a variable computed in the Accumulator at run-time. The following instruction, XRL P1,#00110001B complements bits 5, 4, and 0 of output Port 1. XRL A,R n Bytes: 1 Cycles: 1 Encoding: 01101r r r Operation: XRL (A) ← (A) V (R n ) Instruction Set 2-76 ACALL addr11 Absolute Subroutine Call 2 24 LCALL addr16 Long Subroutine... addr D2 2 SETB bit addr D3 1 SETB C D4 1 DA A D5 3 DJNZ data addr,code addr D6 1 XCHD A,@R0 D7 1 XCHD A,@R1 D8 2 DJNZ R0,code addr D9 2 DJNZ R1,code addr DA 2 DJNZ R2,code addr DB 2 DJNZ R3,code addr DC 2 DJNZ R4,code addr DD 2 DJNZ R5,code addr DE 2 DJNZ R6,code addr DF 2 DJNZ R7,code addr E0 1 MOVX A,@DPTR E1 2 AJMP code addr E2 1 MOVX A,@R0 Hex Code Number of Bytes Mnemonic Operands Instruction Set 2-95 INC . following instruction. bitDirect Addressed bit in Internal Data RAM or Special Function Register.0509B-B–12/9 7Instruction Set Instruction Set2 -7 2Instruction Set. the PSW or bits in the PSW) also affect flag settings.Instructions that Affect Flag Settings(1 )Instruction Flag Instruction FlagCOVAC COVACADD X X X CLR C