tệp lênh z80

Table – BIT LOAD GROUP Mnemonic LD LD LD LD d) r, r’ r, n r, (HL) r, (IX + Explanation r ← r’ r ←n Instruction code D7 D6 D5 D4 D3 D2 D1 D0 ← r → ← r’ → 0 n7 n6 r ← (HL) r ← (IX + d) 1 d7 d6 ← r → n5 n4 n3 ← r → 1 ← r → d5 d4 d3 1 n2 n1 Hexa decimal No of T Cycle Comments r, r’ Reg n0 000 B 001 C 1 010 D 1 1 d2 d1 d0 DD 19 011 E 100 H 101 r ← (IY + d) LD d) r, (IY + LD LD r (HL), r (IX + d), (HL) ← r (IX + d) ← r LD r (IY + d), (IY + d) ← r (HL), n (HL) ← n (IX + d), (IX + d) ← n LD LD n L d7 d7 d7 n7 d7 n7 1 d6 1 d6 1 d6 n6 d6 n6 ← d5 1 d5 1 d5 n5 d5 n5 r d4 1 d4 1 d4 n4 1 d4 n4 → d3 d3 d3 n3 d3 n3 1 d2 ← ← d2 ← d2 n2 1 d2 n2 d1 r r d1 r d1 n1 d1 n1 d0 → → d0 → d0 n0 1 d0 n0 FD 19 111 A DD 19 FD 19 36 DD 36 19 Z80 INTRUCTION SET Page LD n (IY + d), Mnemonic (IY + d) ← n 1 0 d7 d6 n7 n6 Explanation LD LD LD A, (BC) A, (DE) A, (nn) A ← (BC) A ← (DE) A ← (nn) LD LD LD (BC), A (DE), A (nn), A (BC) ← A (DE) ← A (nn) ← A LD A, I A ←I LD A, R A ←R LD I, A I ←A LD R, A I ←A D7 0 n7 n15 0 n7 n15 1 1 D6 0 n6 n14 0 n6 n14 1 1 1 1 1 1 d5 d4 d3 n5 n4 n3 1 1 d2 d1 d0 n2 n1 n0 Instruction code D5 D4 D3 D2 0 0 1 1 n5 n4 n3 n2 n13 n12 n11 n10 0 0 0 1 0 n5 n4 n3 n2 n13 n12 n11 n10 1 1 1 1 1 1 1 0 1 1 0 1 D1 1 n1 n9 1 n1 n9 1 1 D0 0 n0 n8 0 n0 n8 1 1 1 1 FD 36 19 Hexa decimal 0A 1A 3A No of T Cycle 7 13 02 12 32 7 13 ED 57 ED 5F ED 47 ED 4F Comments 9 Z80 INTRUCTION SET Page Table – 16 BIT LOAD GROUP Mnemonic LD dd, nn Explanation dd ← nn Instruction code D7 D6 D5 D4 D3 D2 D1 D0 0 d d 0 n7 n6 n5 n4 n3 n2 n1 n0 n15 n14 n13 n12 n11 n10 n9 n8 Hexa decimal No of T Cycle 10 Comments dd Pair 00 BC 01 LD IX, nn IX ← nn LD IY, nn IY ← nn LD HL, (nn) L ← (nn) H ← (nn+1) LD dd, (nn) ddL ← (nn) ddH ← (nn+1) LD IX, (nn) IXL ← (nn) IXH ← (nn+1) LD IY, (nn) IYL ← (nn) IYH ← (nn+1) DE n7 n15 n7 n15 n7 n15 n7 n15 n7 n15 n7 n15 n6 n14 n6 n14 n6 n14 1 n6 n14 n6 n14 n6 n14 n5 n13 1 n5 n13 n5 n13 d n5 n13 n5 n13 1 n5 n13 n4 n12 n4 n12 n4 n12 d n4 n12 n4 n12 n4 n12 n3 n11 n3 n11 n3 n11 1 n3 n11 1 n3 n11 1 n3 n11 n2 n10 n2 n10 n2 n10 n2 n10 n2 n10 n2 n10 0 n1 n9 0 n1 n9 n1 n9 n1 n9 n1 n9 n1 n9 1 n0 n8 1 n0 n8 n0 n8 1 n0 n8 n0 n8 n0 n8 DD 21 14 10 HL 11 SP FD 21 14 2A 16 ED 20 DD 2A 20 FD 2A 20 Z80 INTRUCTION SET Page Mnemonic Explanation (nn) ← L (nn+1) ← H LD (nn), HL LD (nn), dd LD (nn), IX (nn) ← IXL (nn+1) ← IXH LD (nn), IY (nn) ← IYL (nn+1) ← IYH LD LD SP, HL SP, IX SP ← HL SP ← IX LD SP, IY SP ← IY Mnemonic (nn) ← ddL (nn+1) ← ddH Explanatio n D7 n7 n15 n7 n15 n7 n15 n7 n15 1 1 D6 n6 n14 n6 n14 n6 n14 n6 n14 1 1 Instruction code D5 D4 D3 D2 0 n5 n4 n3 n2 n13 n12 n11 n10 1 d d 0 n5 n4 n3 n2 n13 n12 n11 n10 1 1 0 n5 n4 n3 n2 n13 n12 n11 n10 1 1 1 n5 n4 n3 n2 n13 n12 n11 n10 1 0 1 1 1 1 1 1 Instruction code D1 n1 n9 n1 n9 n1 n9 n1 n9 0 0 D0 n0 n8 1 n0 n8 n0 n8 n0 n8 1 1 Hexa decimal 22 No of T Cycle 16 ED 20 DD 22 20 FD 22 20 F9 DD F9 FD F9 10 Hexa - Comments 10 No of Comments Z80 INTRUCTION SET Page PUSH qq SP ← SP-1 (SP) ← qqH SP ← SP-1 (SP) ← qqL D7 D6 1 D5 D4 D3 q q D2 D1 D0 1 decimal 22 T Cycle 15 qq Pair 00 BC 01 DE 10 PUSH PUSH IX IY POP qq POP IX POP IY SP ← SP-1 (SP) ← IXH SP ← SP-1 (SP) ← IXL SP ← SP-1 (SP) ← IYH SP ← SP-1 (SP) ← IYL qqL ← (SP) SP ← SP+1 qqH ← (SP) SP ← SP+1 IXL ← (SP) SP ← SP+1 IXH ← (SP) SP ← SP+1 IYL ← (SP) SP ← SP+1 IYH ← (SP) SP ← SP+1 HL 1 1 1 1 0 1 DD E5 15 1 1 1 1 1 0 1 FD E5 15 1 q q 0 1 1 1 1 0 1 DD E1 14 1 1 1 1 0 1 FD E1 14 11 AF 10 Z80 INTRUCTION SET Page Table – EXCHANGE, BLOCK TRANSFER, SEARCH GROUP Mnemonic EX DE, HL EX AF, AF’ EXX EX (SP), HL EX (SP), IX EX (SP), IY LDI LDIR LDD Explanation DE ↔ HL AF ↔ AF’ BC ↔ BC’ DE ↔ DE’ HL ↔ HL’ (SP+1) ↔ H (SP) ↔ L (SP+1) ↔ IXH (SP) ↔ IXL (SP+1) ↔ IYH (SP) ↔ IYL (DE) ← (HL) DE ← DE + HL ← HL + BC ← BC - (DE) ← (HL) DE ← DE + HL ← HL + BC ← BC – Repeat until BC =0 (DE) ← (HL) DE ← DE - HL ← HL - BC ← BC - D7 D6 1 0 1 Instruction code D5 D4 D3 D2 D1 D0 1 1 0 0 0 1 0 Hexa decimal EB 08 D9 No of T Cycle 4 1 0 1 E3 19 1 1 1 1 1 0 1 1 1 0 1 1 1 0 1 0 1 1 DD E3 FD E3 ED A0 23 1 1 1 1 0 ED B0 21 (BC ≠ 0) 16 (BC = 0) 1 1 0 1 0 ED A8 16 Comments 23 16 Flag: H= 0, N = If (BC-1=0): P/V =0 Else: P/V =1 Flag: H= 0, N = P/V = Flag: H= 0, N = If (BC-1=0): P/V =0 Else: P/V Z80 INTRUCTION SET Page Mnemonic LDDR CPI Explanation (DE) ← (HL) DE ← DE - HL ← HL - BC ← BC - Repeat until BC =0 A - (HL) HL ← HL + BC ← BC - D7 D6 1 Instruction code D5 D4 D3 D2 D1 D0 1 1 1 0 Hexa decimal ED B8 No of T Cycle 21 (BC ≠ 0) 16 (BC = 0) =1 Comments Flag: H= 0, N = P/V = 1 1 0 1 0 1 ED A1 16 Flag: N = 1, S, Z, H, C If (BC-1=0): P/V =0 Else: P/V =1 CPIR A - (HL) HL ← HL + BC ← BC - Repeat until A = (HL) or BC =0 1 1 1 1 0 1 ED B1 21 (BC≠ or A≠ (HL)) 16 (BC= or A=(HL)) Flag: N = 1, S, Z, H, C If (BC-1=0): P/V =0 Else: P/V =1 CPD A - (HL) HL ← HL - BC ← BC - 1 1 1 0 1 0 1 ED A9 16 Flag: N = 1, S, Z, H, C If (BC-1=0): P/V =0 Else: P/V =1 CPDR A - (HL) HL ← HL - 1 1 1 1 1 0 1 ED B9 21 (BC≠ or A≠ Flag: N = 1, S, Z, H, Z80 INTRUCTION SET Page BC ← BC – Repeat until A = (HL) or BC =0 (HL)) 16 (BC= or A=(HL)) C If (BC-1=0): P/V =0 Else: P/V =1 Table – BIT ARITHMETIC AND LOGICAL GROUP Mnemonic ADD ADD A, r A, n Explanation A ← A+r A ← A+n ADD ADD + d) A, (HL) A, (IX A ← A + (HL) A ← A + (IX + d) ADD d) A, (IY + A ← A + (IY + d) D7 1 n7 1 d7 1 d7 D6 n6 d6 d6 Instruction code D5 D4 D3 D2 0 ← 0 n5 n4 n3 n2 0 1 1 0 d5 d4 d3 d2 1 1 0 d5 d4 d3 d2 0 1 0 1 ADC A, s SUB s SBC A, s A ← A + s + CY A ← A-s A ← A - s - CY AND A ← A AND s 0 A ← A OR s 1 A ← A XOR s A - s 1 1 OR s s XOR s CP s D1 r n1 1 d1 d1 D0 → n0 d0 d0 Hexa decimal C6 No of T Cycle 86 DD 86 19 FD 86 19 Comments Flag: N = S, Z, H, C V (P/V) Flag: N = S, Z, H, C, V H=1 N = 0, C =0 H=0 P (P/V) H=0 S, Z N = 1, S, Z, H, C, Z80 INTRUCTION SET Page r ← r+1 (HL) ← (HL) + INC (IX + d) (IX + d) ← (IX + d) + INC (IY + d) (IY + d) ← (IY + d) + DEC m m ← m-1 s: r, n, (HL), (IX + d), (IY + d) INC INC r (HL) 0 0 1 0 d7 d6 1 0 d7 d6 ← r → 1 0 0 1 1 d5 d4 d3 1 1 d5 d4 d3 1 0 d2 d1 d0 1 0 d2 d1 d0 1 m: r, (HL), (IX + d), (IY + d) 34 V N = 0, S, Z, H, V 11 DD 34 23 FD 34 23 N = 1, S, Z, H, V Table – 16 ARITHMETIC GROUP Mnemonic Explanation D7 D6 Instruction code D5 D4 D3 D2 D1 D0 Hexa decimal No of T Cycle 11 ADD HL, ss HL ← HL + ss 0 s s 0 ADC HL, ss HL ← HL + ss 1 1 s s 1 0 1 ED 15 SBC HL, ss HL ← HL - ss CY 1 1 s s 1 0 1 ED 15 ADD IX, pp IX ← IX + pp IY ← IY + rr p r s 1 1 1 0 0 0 1 1 1 15 IY, rr p r s DD ADD 1 0 FD 15 1 1 DD INC ss ss ← ss + 1 0 INC IX IX ← IX + 1 Comments Flag: N = 0, H, C Flag: N = 0, H, C V, S, Z Flag: N = 1, H, C V, S, Z Flag: N = 0, H, C 10 Z80 INTRUCTION SET Page INC IY ← IY + IY DEC ss ss ← ss - DEC IX IX ← IX - DEC IY IY ← IY - ss 00 01 10 11 Pair BC DE HL SP 0 0 1 s s 1 0 1 1 1 23 FD 23 1 1 Pair BC DE IX SP 1 1 1 1 1 rr 1 1 1 Pair DD 2B FD 2B pp 00 01 10 11 00 01 10 11 10 10 10 BC DE IY SP Table – ROTATE AND SHIFT GROUP Mnemonic Explanation 0 0 1 Hexa decim al 07 0 1 1 17 0 0 1 1 0F 0 1 1 1F 1 0 0 0 1 ← r → CB 1 0 0 0 CB 06 15 D7 D6 RLCA CY RLA CY RRCA RRA RLC r RLC (HL) A7 A6 A5 A4 A3 A2 A1 A0 A7 A6 A5 A4 A3 A2 A1 A0 A7 A6 A5 A4 A3 A2 A1 A0 CY A7 A6 A5 A4 A3 A2 A1 A0 CY r CY b7 b6 b5 b4 b3 b2 b1 b0 CY b7 b6 b5 b4 b3 b2 b1 b0 (HL) Instruction code D5 D4 D3 D2 D1 D0 1 No of T Cycle Comments Flag: N = 0, H = Flag: N = 0, H = S, Z, P (P/V) Z80 INTRUCTION SET 10 Page RLC (IX + d) CY 1 d7 1 d7 b7 b6 b5 b4 b3 b2 b1 b0 (IX + d) RLC (IY + d) CY b7 b6 b5 b4 b3 b2 b1 b0 (IY + d) RL RRC RR m m CY m b7 b6 b5 b4 b3 b2 b1 b0 m b7 b6 b5 b4 b3 b2 b1 b0 m m SRA m SRL m RLD CY Explanation b7 b6 b5 b4 b3 b2 b1 b0 m b7 b6 b5 b4 b3 b2 b1 b0 CY m b7 b6 b5 b4 b3 b2 b1 b0 0 d5 d5 1 d4 d3 0 1 d4 d3 0 0 1 1 1 d2 d1 d0 1 1 1 d2 d1 d0 1 Instruction code D7 D6 D5 D4 D3 D2 D1 D0 m CY CY 0 1 1 DD CB 23 FD CB 23 Hexa decim al No of T Cycle b7 b3 b4 b0 1 1 0 1 1 1 ED 6F 18 b7 b3 b4 b0 b7 b3 b0 b4 1 1 0 1 1 1 ED 67 18 A (HL ) (HL ) Comments Flag: N = 0, H= S, Z, P (P/V) b7 b3 b4 b0 A RRD CY m b7 b6 b5 b4 b3 b2 b1 b0 Mnemonic SLA 1 d6 1 d6 Flag: N = 0, H= S, Z, P (P/V) Z80 INTRUCTION SET 11 Page Table – GENERAL PURPOSE ARITHMEIC AND CPU CONTROL GROUP Mnemonic Explanation 0 0 1 27 No of T Cycle 0 1 1 2F 0 1 0 1 0 1 1 1 1 0 1 1 ED 44 3F 37 0 1 1 1 0 0 0 1 0 00 76 F3 4 1 1 1 FB D7 D6 DDA Decimal Adjust ACC A ←A CPL NEG A ←0 - A CCF SCF CY ← CY CY ← NOP HALT DI No operations CPU halted Disable Interrupt Enable Interrupt EI Instruction code D5 D4 D3 D2 D1 D0 Hexa decimal 4 Comments Flag: S, Z, H, C, P Flag: N = 1, H=1 Flag: C = 1, S, Z, H, V Flag: N = 0, H Flag: N = 0, H =0 Table – BIT MANIPULATION GROUP Mnemonic Explanation BIT b, r Z ← rb BIT b, (HL) Z ← (HL)b BIT d) b, (IX + Z ← (IX + d)b D7 D6 1 1 1 1 1 d7 d6 Instruction code D5 D4 D3 D2 D1 D0 0 1 ← b → ← r → 0 ← b → 1 0 d5 d4 d3 ← b → 1 1 0 d2 d1 1 1 d0 Hexa decimal CB No of T Cycle CB 12 Comments Flag: N = 0, H = S, P/V b DD CB 20 Bit 000 001 010 011 Z80 INTRUCTION SET 12 Page BIT d) b, (IY + Z ← (IY + d)b rb ← SET b, r SET b, (HL) (HL)b ← SET d) b, (IX + (IX + d)b ← SET d) b, (IY + (IY + d)b ← RES b, m mb ← 1 1 d7 d6 1 1 1 1 1 1 d7 d6 1 1 1 d7 d6 1 1 1 0 d5 d4 d3 ← b → 0 ← b → 0 ← b → 1 0 d5 d4 d3 ← b → 1 0 d5 d4 d3 ← b → 0 d2 d1 1 ← r 1 1 0 d2 d1 1 0 d2 d1 1 1 d0 → 1 d0 1 d0 FD CB 20 CB CB 15 DD CB 23 FD CB 23 100 101 110 111 m: r, (HL), (IX + d), (IY + d) Table – INPUT AND OUTPUT GROUP Mnemonic Explanation IN A, (n) A ← (n) IN r, (C) r ← (C) D7 D6 1 n7 n6 1 Instruction code D5 D4 D3 D2 D1 D0 1 1 n5 n4 n3 n2 n1 n0 1 1 ← r → 0 Hexa decimal DB No of T Cycle 11 ED 12 Comments Flag: H= 0, N = S, Z, P Flag: N = Z (HL) ← (C) 1 1 1 ED 16 1 0 A2 HL ← HL + B ← B-1 INIR (HL) ← (C) 1 1 1 ED 21 (B ≠ Flag: Z = 1, N = Z80 INTRUCTION SET 13 Page INI HL ← HL + B ← B–1 Repeat until B =0 (HL) ← (C) HL ← HL - B ← B-1 (HL) ← (C) HL ← HL - B ← B–1 Repeat until B =0 IND INDR Mnemonic (n), A (n) ← A OUT (C), r (C) ← r OTIR OUTD 1 0 0 B0 0) 16 (B = 0) 1 1 0 1 0 1 ED AA 16 1 1 1 1 0 1 ED BA 21 (B ≠ 0) 16 (B = 0) Flag: Z = 1, N = Hexa decimal D3 No of T Cycle 11 Comments ED 12 ED A3 16 Explanation OUT OUTI (C) ← (HL) HL ← HL + B ← B-1 (C) ← (HL) HL ← HL + B ← B–1 Repeat until B =0 (C) ← (HL) D7 D6 1 n7 n6 1 1 1 Instruction code D5 D4 D3 D2 D1 D0 0 1 n5 n4 n3 n2 n1 n0 1 1 ← r → 0 1 1 1 0 1 1 1 1 1 0 1 ED B3 21 (B ≠ 0) 16 (B = 0) 1 1 1 ED 16 Flag: N = Z Flag: N = Z Flag: Z = 1, N = Flag: N = Z80 INTRUCTION SET 14 Page OTDR HL ← HL - B ← B-1 (C) ← (HL) HL ← HL - B ← B–1 Repeat until B =0 1 1 AB 1 1 1 1 0 1 ED BA Z 21 (B ≠ 0) 16 (B = 0) Flag: Z = 1, N = Table 10 – JUMP GROUP Mnemonic JP JP nn cc, nn Explanation PC ← nn If cc is TRUE: PC ← nn D7 n7 n15 D6 n6 n14 1 n7 n6 n15 n14 Instruction code D5 D4 D3 D2 D1 D0 0 0 1 n5 n4 n3 n2 n1 n0 n13 n12 n11 n10 n9 n8 ← cc → n5 n4 n3 n13 n12 n11 Hexa decimal C3 No of T Cycle 10 Comments cc Condition 000 NZ 001 n2 n1 n0 n10 n9 n8 10 NC 011 Z 010 C 100 PE Z80 INTRUCTION SET 15 Page JR JR e ss, e PC ← PC + e If ss is TRUE : PC ← PC +e 0 1 0 18 12 e ← ss → e 0 12 (ss TRUE) (ss FALSE) JP HL PC ← HL 1 1 0 E9 JP IX PC ← IX 1 1 1 1 0 1 DD E9 JP IY PC ← IY 1 1 1 1 1 0 1 FD E9 0 0 0 10 (B = 0) 13 (B ≠ 0) DJNZ e B ←B - If B ≠ 0: PC ← PC + e 101 PO 110 e P 111 M ss Condition 111 C 110 NC 101 Z 100 NZ Table 11 – CALL AND RETURN GROUP Mnemonic Explanation D7 n7 n15 D6 n6 n14 Instruction code D5 D4 D3 D2 D1 D0 0 1 n5 n4 n3 n2 n1 n0 n13 n12 n11 n10 n9 n8 Hexa decimal CD No of T Cycle 17 Comments SP ← SP-1 (SP) ← PCH SP ← SP-1 (SP) ← PCL Z80 INTRUCTION SET 16 Page CALL nn CALL RET RET cc cc, nn PC ← nn If cc is TRUE: SP ← SP-1 (SP) ← PCH SP ← SP-1 (SP) ← PCL PC ← nn 1 n7 n6 n15 n14 ← cc → n5 n4 n3 n13 n12 n11 0 n2 n1 n0 n10 n9 n8 10 (cc FALSE) 17 (cc TRUE) cc Condition 000 NZ 001 NC 011 Z 010 C 100 PE PCL ← (SP) SP ← SP+1 PCH ← (SP) SP ← SP+1 If cc is TRUE: PCL ← (SP) SP ← SP+1 PCH ← (SP) SP ← SP+1 1 0 0 C9 10 101 PO 110 ← cc → P 111 M 0 (cc FALSE) 11 (cc TRUE) Z80 INTRUCTION SET 17 Page ... 36 19 Hexa decimal 0A 1A 3A No of T Cycle 7 13 02 12 32 7 13 ED 57 ED 5F ED 47 ED 4F Comments 9 Z80 INTRUCTION SET Page Table – 16 BIT LOAD GROUP... n8 1 n0 n8 n0 n8 1 n0 n8 n0 n8 n0 n8 DD 21 14 10 HL 11 SP FD 21 14 2A 16 ED 20 DD 2A 20 FD 2A 20 Z80 INTRUCTION SET Page Mnemonic Explanation (nn)... 22 No of T Cycle 16 ED 20 DD 22 20 FD 22 20 F9 DD F9 FD F9 10 Hexa - Comments 10 No of Comments Z80 INTRUCTION SET Page PUSH qq SP ← SP-1 (SP) ←