Ebook Visualization analysis and design Part 2

(BQ) Part 1 book Visualization analysis and design has contents: Arrange spatial data, arrange networks and trees, map color and other channels, manipulate view, facet into multiple views, reduce items and attributes, analysis case studies,...and other contents.

CMOS VLSI Design A Circuits and Systems Perspective Fourth Edition This page intentionally left blank CMOS VLSI Design A Circuits and Systems Perspective Fourth Edition Neil H E Weste Macquarie University and The University of Adelaide David Money Harris Harvey Mudd College Addison-Wesley Boston Columbus Indianapolis New York San Francisco Upper Saddle River Amsterdam Cape Town Dubai London Madrid Milan Munich Paris Montreal Toronto Delhi Mexico City Sao Paulo Sydney Hong Kong Seoul Singapore Taipei Tokyo Editor in Chief: Michael Hirsch Acquisitions Editor: Matt Goldstein Editorial Assistant: Chelsea Bell Managing Editor: Jeffrey Holcomb Senior Production Project Manager: Marilyn Lloyd Media Producer: Katelyn Boller Director of Marketing: Margaret Waples Marketing Coordinator: Kathryn Ferranti Senior Manufacturing Buyer: Carol Melville Senior Media Buyer: Ginny Michaud Text Designer: Susan Raymond Art Director, Cover: Linda Knowles Cover Designer: Joyce Cosentino Wells/J Wells Design Cover Image: Cover photograph courtesy of Nick Knupffer—Intel Corporation Copyright © 2009 Intel Corporation All rights reserved Full Service Vendor: Gillian Hall/The Aardvark Group Publishing Service Copyeditor: Kathleen Cantwell, C4 Technologies Proofreader: Holly McLean-Aldis Indexer: Jack Lewis Printer/Binder: Edwards Brothers Cover Printer: Lehigh-Phoenix Color/Hagerstown Credits and acknowledgments borrowed from other sources and reproduced with permission in this textbook appear on appropriate page within text or on page 838 The interior of this book was set in Adobe Caslon and Trade Gothic Copyright © 2011, 2005, 1993, 1985 Pearson Education, Inc., publishing as Addison-Wesley All rights reserved Manufactured in the United States of America This publication is protected by Copyright, and permission should be obtained from the publisher prior to any prohibited reproduction, storage in a retrieval system, or transmission in any form or by any means, electronic, mechanical, photocopying, recording, or likewise To obtain permission(s) to use material from this work, please submit a written request to Pearson Education, Inc., Permissions Department, 501 Boylston Street, Suite 900, Boston, Massachusetts 02116 Many of the designations by manufacturers and sellers to distinguish their products are claimed as trademarks Where those designations appear in this book, and the publisher was aware of a trademark claim, the designations have been printed in initial caps or all caps Cataloging-in-Publication Data is on file with the Library of Congress Addison-Wesley is an imprint of 10 1—EB—14 13 12 11 10 ISBN 10: 0-321-54774-8 ISBN 13: 978-0-321-54774-3 To Avril, Melissa, Tamara, Nicky, Jocelyn, Makayla, Emily, Danika, Dan and Simon N W To Jennifer, Samuel, and Abraham D M H This page intentionally left blank Contents Preface xxv Chapter Introduction 1.1 A Brief History 1.2 Preview 1.3 MOS Transistors 1.4 CMOS Logic The Inverter 1.4.1 The NAND Gate 1.4.2 CMOS Logic Gates 1.4.3 The NOR Gate 11 1.4.4 Compound Gates 11 1.4.5 Pass Transistors and Transmission Gates 12 1.4.6 Tristates 14 1.4.7 Multiplexers 15 1.4.8 Sequential Circuits 16 1.4.9 1.5 CMOS Fabrication and Layout 19 Inverter Cross-Section 19 1.5.1 Fabrication Process 20 1.5.2 Layout Design Rules 24 1.5.3 Gate Layouts 27 1.5.4 Stick Diagrams 28 1.5.5 1.6 Design Partitioning 29 Design Abstractions 30 1.6.1 Structured Design 31 1.6.2 Behavioral, Structural, and Physical Domains 31 1.6.3 1.7 Example: A Simple MIPS Microprocessor 33 MIPS Architecture 33 1.7.1 Multicycle MIPS Microarchitecture 34 1.7.2 1.8 Logic Design 38 Top-Level Interfaces 38 1.8.1 Block Diagrams 38 1.8.2 Hierarchy 40 1.8.3 Hardware Description Languages 40 1.8.4 1.9 Circuit Design 42 vii viii Contents 1.10 Physical Design 45 1.10.1 Floorplanning 45 1.10.2 Standard Cells 48 1.10.3 Pitch Matching 50 1.10.4 Slice Plans 50 1.10.5 Arrays 51 1.10.6 Area Estimation 51 1.11 Design Verification 53 1.12 Fabrication, Packaging, and Testing 54 Summary and a Look Ahead Exercises 55 57 Chapter MOS Transistor Theory 2.1 Introduction 61 2.2 Long-Channel I-V Characteristics 64 2.3 C-V Characteristics 68 2.3.1 Simple MOS Capacitance Models 68 2.3.2 Detailed MOS Gate Capacitance Model 70 2.3.3 Detailed MOS Diffusion Capacitance Model 72 2.4 Nonideal I-V Effects 74 2.4.1 Mobility Degradation and Velocity Saturation 75 2.4.2 Channel Length Modulation 78 2.4.3 Threshold Voltage Effects 79 2.4.4 Leakage 80 2.4.5 Temperature Dependence 85 2.4.6 Geometry Dependence 86 2.4.7 Summary 86 2.5 DC Transfer Characteristics 87 2.5.1 Static CMOS Inverter DC Characteristics 88 2.5.2 Beta Ratio Effects 90 2.5.3 Noise Margin 91 2.5.4 Pass Transistor DC Characteristics 92 2.6 Pitfalls and Fallacies 93 Summary 94 Exercises 95 Chapter CMOS Processing Technology 3.1 Introduction 99 3.2 CMOS Technologies 100 3.2.1 Wafer Formation 100 3.2.2 Photolithography 101 Contents 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 3.2.9 3.2.10 Well and Channel Formation 103 Silicon Dioxide (SiO2) 105 Isolation 106 Gate Oxide 107 Gate and Source/Drain Formations 108 Contacts and Metallization 110 Passivation 112 Metrology 112 3.3 Layout Design Rules 113 3.3.1 Design Rule Background 113 3.3.2 Scribe Line and Other Structures 116 3.3.3 MOSIS Scalable CMOS Design Rules 117 3.3.4 Micron Design Rules 118 3.4 CMOS Process Enhancements 119 3.4.1 Transistors 119 3.4.2 Interconnect 122 3.4.3 Circuit Elements 124 3.4.4 Beyond Conventional CMOS 129 3.5 Technology-Related CAD Issues 130 3.5.1 Design Rule Checking (DRC) 131 3.5.2 Circuit Extraction 132 3.6 Manufacturing Issues 133 3.6.1 Antenna Rules 133 3.6.2 Layer Density Rules 134 3.6.3 Resolution Enhancement Rules 134 3.6.4 Metal Slotting Rules 135 3.6.5 Yield Enhancement Guidelines 135 3.7 Pitfalls and Fallacies 136 3.8 Historical Perspective 137 Summary 139 Exercises 139 Chapter Delay 4.1 Introduction 141 4.1.1 Definitions 141 4.1.2 Timing Optimization 142 4.2 Transient Response 143 4.3 RC Delay Model 146 4.3.1 Effective Resistance 146 4.3.2 Gate and Diffusion Capacitance 147 4.3.3 Equivalent RC Circuits 147 4.3.4 Transient Response 148 4.3.5 Elmore Delay 150 ix 312 Chapter Circuit Simulation TABLE 8.5 Device characteristics for a variety of processes Vendor Orbit Model Feature Size f VDD MOSIS HP AMI AMI MOSIS MOSIS MOSIS TSMC TSMC TSMC IBM IBM IBM MOSIS MOSIS TSMC IBM IBM IBM nm 2000 800 600 600 350 250 180 130 90 65 V 5 3.3 3.3 2.5 1.8 1.2 1.0 1.0 1.90 2.30 1.67 1.04 0.97 0.80 Cg (delay) f F /Rm 1.77 1.67 Gates 1.55 1.48 Cg (power) f F /Rm 2.24 1.70 1.83 1.76 2.20 2.92 2.06 1.34 1.23 1.07 ps 856 297 230 312 210 153 75.6 45.9 37.2 17.2 Cd (isolated) fF/Rm ·1.19 1.11 1.14 nMOS 1.21 1.63 1.88 1.12 0.94 0.89 0.76 Cd (shared) fF/Rm 1.62 1.43 1.41 1.50 2.04 2.60 1.62 1.56 1.60 1.28 FO4 Inv Delay Cd (merged) fF/Rm 1.48 1.36 1.19 1.24 1.60 2.16 1.41 1.40 1.51 1.20 Rn (single) k⍀ · Rm 30.3 10.1 9.19 11.9 5.73 4.02 2.69 2.54 2.35 1.34 Rn (series) k⍀ · Rm 22.1 6.95 6.28 8.59 4.01 3.10 2.00 1.93 1.81 1.13 V 0.65 0.65 0.70 0.70 0.59 0.48 0.41 0.32 0.32 0.31 Vtn (const I) Vtn (linear ext.) V 0.65 0.75 0.76 0.76 0.67 0.57 0.53 0.43 0.43 0.43 Idsat RA/Rm 152 380 387 216 450 551 566 478 497 755 Ioff pA/Rm 2.26 9.36 2.21 1.45 6.57 56.3 93.9 1720 4000 33400 I gate pA/Rm n/a n/a n/a n/a n/a n/a n/a 1.22 3620 8520 Cd (isolated) fF/Rm 1.42 1.17 1.31 pMOS 1.42 1.89 2.07 1.24 0.94 0.74 0.73 Cd (shared) fF/Rm 1.92 1.62 1.73 1.86 2.37 2.89 1.79 1.56 1.25 1.25 Cd (merged) fF/Rm 1.52 1.23 1.35 1.43 1.83 2.40 1.56 1.41 1.16 1.18 Rp (single) k⍀ · Rm 67.1 26.7 19.9 29.6 16.1 8.93 6.51 6.39 5.47 2.87 Rp (series) k⍀ · Rm 53.9 21.4 15.4 23.6 13.3 6.91 5.41 5.48 4.92 2.42 V 0.72 0.91 0.90 0.90 0.83 0.46 0.43 0.33 0.35 0.33 |Vtp| (const I) |Vtp| (linear ext.) V 0.71 0.94 0.93 0.93 0.88 0.52 0.51 0.42 0.43 0.42 Idsat RA/Rm 70.5 154 215.3 99.0 181 245 228 177 187 360 Ioff pA/Rm 2.18 1.57 2.08 1.38 2.06 30.1 25.2 1330 2780 19500 I gate pA/Rm n/a n/a n/a n/a n/a n/a n/a 0.06 1210 2770 The gate capacitance for delay held steady near fF/Rm for many generations, as scaling theory would predict, but abruptly dropped after the 180 nm generation The gate capacitance for power is slightly higher than that for delay as discussed in Section 8.4.3 The FO4 inverter delay has steadily improved with feature size as constant field scaling predicts It fits our rule from Section 4.4.3 of one third to one half of the effective channel length, when delay is measured in picoseconds and length in nanometers Diffusion capacitance of an isolated contacted source or drain has been 1–2 fF/Rm for both nMOS and pMOS transistors over many generations The capacitance of a shared contacted diffusion region is slightly higher because it has more area and includes two gate overlaps The capacitance of the merged diffusion reflects two gate overlaps but a smaller diffusion area Half the capacitance of the shared and merged diffusions is allocated to each of the transistors connected to the diffusion region 8.5 Circuit Characterization The effective resistance of a Rm wide transistor has decreased with process scaling in proportion to the feature size f However, the resistance of a unit (4/2 Q) nMOS transistor, R/2f, has remained roughly constant around k