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Tài liệu hướng dẫn chi tiết về sử dụng Quartus ii. Đây là một tài liệu rất hữu ích, không thể thiếu đối với bất kỳ sinh viên nào muốn học tốt về ngôn ngữ HDL và phần mềm Quartus ii Introduction This tutorial provides an introduction to simulation of logic circuits using the Graphical Waveform Editor in the ModelSim Simulator. It shows how the simulator can be used to perform functional simulation of a circuit specified in Verilog HDL. It is intended for a student in an introductory course on logic circuits, who has just started learning this material and needs to acquire quickly a rudimentary understanding of simulation. Contents: • Design Project • Creating Waveforms for Simulation • Simulation • Making Changes and Resimulating • Concluding Remarks
Using ModelSim to Simulate Logic Circuits for Altera FPGA Devices Introduction This tutorial is a basic introduction to ModelSim, a Mentor Graphics’ simulation tool for logic circuits We show how to perform functional and timing simulations of logic circuits implemented by using Quartus II CAD software The reader is expected to have the basic knowledge of Verilog hardware description language, and the Altera Quartus II CAD software Contents: • Introduction to simulation • What is ModelSim? • Functional simulation using ModelSim • Timing simulation using ModelSim Altera Corporation - University Program September 2010 U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS FOR A LTERA FPGA D EVICES Background Designers of digital systems are inevitably faced with the task of testing their designs Each design can be composed of many modules, each of which has to be tested in isolation and then integrated into a design when it operates correctly To verify that a design operates correctly we use simulation, which is a process of testing the design by applying inputs to a circuit and observing its behavior The output of a simulation is a set of waveforms that show how a circuit behaves based on a given sequence of inputs The general flow of a simulation is shown in Figure Figure The simulation flow There are two main types of simulation: functional and timing simulation The functional simulation tests the logical operation of a circuit without accounting for delays in the circuit Signals are propagated through the circuit using logic and wiring delays of zero This simulation is fast and useful for checking the fundamental correctness of the designed circuit The second step of the simulation process is the timing simulation It is a more complex type of simulation, where logic components and wires take some time to respond to input stimuli In addition to testing the logical operation of the circuit, it shows the timing of signals in the circuit This type of simulation is more realistic than the functional simulation; however, it takes longer to perform Altera Corporation - University Program September 2010 U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS FOR A LTERA FPGA D EVICES In this tutorial, we show how to simulate circuits using ModelSim You need Quartus II CAD software and ModelSim software, or ModelSim-Altera software that comes with Quartus II, to work through the tutorial Example Design Our example design is a serial adder It takes 8-bit inputs A and B and adds them in a serial fashion when the g o input is set to The result of the operation is stored in a 9-bit sum register A block diagram of the circuit is shown in Figure It consists of three shift registers, a full adder, a flip-flop to store carry-out signal from the full adder and a finite state machine (FSM) The shift registers A and B are loaded with the values of A and B After the st ar t signal is set high, these registers are shifted right one bit at a time At the same time the least-significant bits of A and B are added and the result is stored into the shift register sum Once all bits of A and B have been added, the circuit stops and displays the sum until a new addition is requested Figure Block diagram of a serial-adder circuit The Verilog code for the top-level module of this design is shown in Figure It consists of the instances of the shift registers, an adder and a finite state machine (FSM) to control this design Altera Corporation - University Program September 2010 U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS FOR A LTERA FPGA D EVICES 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 module serial(A, B, start, resetn, clock, sum); input [7:0] A, B; input resetn, start, clock; output [8:0] LEDR; // Registers wire [7:0] A_reg,B_reg; wire [8:0] sum; reg cin; // Wires wire reset, enable, load; wire bit_sum, bit_carry; // Confrol FSM FSM my_control(start, clock, resetn, reset, enable, load); // Datapath shift_reg reg_A( clock, 1’b0, A, 1’b0, enable, load, A_reg); shift_reg reg_B( clock, 1’b0, B, 1’b0, enable, load, B_reg); // a full adder assign bit_carry, bit_sum = A_reg[0] + B_reg[0] + cin; always @(posedge clock) begin if (enable) if (reset) cin [...]... will appear to the right of the serial.v file in the Project tab 4.3 Simulation To begin a simulation of the design, the software needs to be put in simulation mode To do this, select Start Simulation from the Simulate menu The window in Figure 11 will appear Figure 11 Start simulation mode in ModelSim The window to start simulation consists of many tabs These include a Design tab that lists designs available... locate the toolbar buttons shown in Figure 18 Figure 18 Simulation control buttons on the toolbar The toolbar buttons shown in Figure 18 are used to step through the simulation The left-most button is the restart button, which causes the simulation window to be cleared and the simulation to be restarted The text field, shown with a 100ps string inside it, defines the amount of time that the simulation. .. CAD software The project for this part of the tutorial has been created for you in the example/timing subdirectory 5.1 Setting up a Quartus II Project for Timing Simulation with ModelSim To perform timing simulation we need to set up Quartus II software to generate the necessary delay information for ModelSim by setting up EDA Tools for simulation in the Quartus II project To set up EDA Tools for simulation, ... go signal and moved to state 01 to begin computing the sum of the two inputs Figure 21 Simulation results after 200ps To complete the operation, the circuit will require 9 clock cycles To fast forward the simulation to see the result, specify 900ps in the text field next to the run button, and press the run button This brings the simulation to time 1100ps, at which point a result of summation is shown... M ODEL S IM TO S IMULATE L OGIC C IRCUITS FOR A LTERA FPGA D EVICES Figure 16 Simulation window with aliased signals Now that we set up a set of signals to observe we can begin simulating the circuit There are two ways to run a simulation in ModelSim: manually or by using scripts A manual simulation allows users to apply inputs and advance the simulation time to see the results of the simulation in... altera /verilog/ cycloneii directory in the ModelSim- Altera software To add this library to your project, include the altera /verilog/ cycloneii directory using the Add button Then, click Altera Corporation - University Program September 2010 23 U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS FOR A LTERA FPGA D EVICES on the Design tab, select your project for simulation, and click OK When the ModelSim software... registers that store A and B at the positive edge of the clock The reg_sum|q signal is a register that stores the resulting sum Begin the simulation by resetting the circuit To do this, set go and resetn signals to 0 Also, set the clock input to have a period of 20ns, whose first edge is a falling edge To run the simulation, set the simulation step to 20ns and press the Run button The simulation result... SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS FOR A LTERA FPGA D EVICES Figure 27 Timing Simulation after 20ns To proceed with the simulation deassert the resetn signal by setting it to 1, and apply data to inputs A and B Set them to 143 and 57, and assign a value of 1 to the go input as described in the Functional Simulation section of the tutorial Then run the simulation for a period of 20ns, by pressing... performs timing analysis Then it stores the compilation result in the Altera Corporation - University Program September 2010 21 U SING M ODEL S IM TO S IMULATE L OGIC C IRCUITS FOR A LTERA FPGA D EVICES Figure 24 Quartus II EDA simulation tool settings simulation directory for ModelSim to use Take a moment to examine the files generated for simulation using a text editor The two main files are serial.vo,... the Run button (to the right of the text field) is pressed The remaining three buttons, Continue, Run -All and Break, can be used to resume, start and interrupt a simulation, respectively We will not need them in this tutorial To run a simulation for 100ps, set the value in the text field to 100ps and press the Run button After the simulation run for 100ps completes, you will see the state of the circuit