ARM v7-M Architecture Application Level Reference Manual Beta Copyright © 2006 ARM Limited All rights reserved ARM DDI 0405A-01 ARM v7-M Architecture Application Level Reference Manual Copyright © 2006 ARM Limited All rights reserved Release Information The following changes have been made to this document Change History Date Issue Change 21-Mar-2006 A first beta release Proprietary Notice ARM, the ARM Powered logo, Thumb, and StrongARM are registered trademarks of ARM Limited The ARM logo, AMBA, Angel, ARMulator, EmbeddedICE, ModelGen, Multi-ICE, PrimeCell, ARM7TDMI, ARM7TDMI-S, ARM9TDMI, ARM9E-S, ETM7, ETM9, TDMI, STRONG, are trademarks of ARM Limited All other products or services mentioned herein may be trademarks of their respective owners The product described in this document is subject to continuous developments and improvements All particulars of the product and its use contained in this document are given by ARM in good faith Subject to the provisions set out below, ARM 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Beta ARM DDI 0405A-01 No licence, express, implied or otherwise, is granted to LICENSEE, under the provisions of Clause 1, to use the ARM tradename, in connection with the use of the ARM Architecture Reference Manual or any products based thereon Nothing in Clause shall be construed as authority for you to make any representations on behalf of ARM in respect of the ARM Architecture Reference Manual or any products based thereon Copyright © 2005, 2006 ARM limited 110 Fulbourn Road Cambridge, England CB1 9NJ Restricted Rights Legend: Use, duplication or disclosure by the United States Government is subject to the restrictions set forth in DFARS 252.227-7013 (c)(1)(ii) and FAR 52.227-19 The right to use and copy this document is subject to the licence set out above ARM DDI 0405A-01 Copyright © 2006 ARM Limited All rights reserved Beta iii iv Copyright © 2006 ARM Limited All rights reserved Beta ARM DDI 0405A-01 Contents ARM v7-M Architecture Application Level Reference Manual Preface About this manual x Unified Assembler Language xi Using this manual xii Conventions xiv Further reading xv Feedback xvi Part A Chapter A1 Application Introduction A1.1 A1.2 Chapter A2 Application Level Programmer’s Model A2.1 A2.2 A2.3 ARM DDI 0405A-01 The ARM Architecture – M profile A1-2 Introduction to Pseudocode A1-3 The register model A2-2 Exceptions, faults and interrupts A2-5 Coprocessor support A2-6 Copyright © 2006 ARM Limited All rights reserved Beta v Contents Chapter A3 ARM Architecture Memory Model A3.1 A3.2 A3.3 A3.4 A3.5 A3.6 A3.7 A3.8 A3.9 Chapter A4 The Thumb Instruction Set A4.1 A4.2 A4.3 A4.4 A4.5 A4.6 A4.7 Chapter A5 Chapter B1 System Level Programmer’s Model The system address map B2-2 Bit Banding B2-5 System Control Space (SCS) B2-7 System timer - SysTick B2-9 Nested Vectored Interrupt Controller (NVIC) B2-10 Protected Memory System Architecture B2-12 ARMv7-M System Instructions B3.1 vi Introduction to the system level B1-2 System programmer’s model B1-3 System Address Map B2.1 B2.2 B2.3 B2.4 B2.5 B2.6 Chapter B3 Format of instruction descriptions A5-2 Immediate constants A5-8 Constant shifts applied to a register A5-10 Memory accesses A5-13 Memory hints A5-14 NOP-compatible hints A5-15 Alphabetical list of Thumb instructions A5-16 System B1.1 B1.2 Chapter B2 Instruction set encoding A4-2 Instruction encoding for 16-bit Thumb instructions A4-3 Instruction encoding for 32-bit Thumb instructions A4-12 Conditional execution A4-33 UNDEFINED and UNPREDICTABLE instruction set space A4-37 Usage of 0b1111 as a register specifier A4-39 Usage of 0b1101 as a register specifier A4-41 Thumb Instructions A5.1 A5.2 A5.3 A5.4 A5.5 A5.6 A5.7 Part B Address space A3-2 Alignment Support A3-3 Endian Support A3-5 Synchronization and semaphores A3-8 Memory types A3-19 Access rights A3-26 Memory access order A3-27 Caches and memory hierarchy A3-32 Bit banding A3-34 Alphabetical list of ARMv7-M system instructions B3-2 Copyright © 2006 ARM Limited All rights reserved Beta ARM DDI 0405A-01 Contents Part C Chapter C1 Debug Debug C1.1 C1.2 C1.3 C1.4 C1.5 C1.6 C1.7 C1.8 C1.9 C1.10 C1.11 Appendix A Pseudo-code definition A.1 A.2 A.3 A.4 A.5 A.6 Appendix B Appendix C Instruction encoding diagrams and pseudo-code AppxA-2 Data Types AppxA-4 Expressions AppxA-8 Operators and built-in functions AppxA-10 Statements and program structure AppxA-18 Helper procedures and functions AppxA-22 Legacy Instruction Mnemonics CPUID C.1 Appendix D Introduction to debug C1-2 The Debug Access Port (DAP) C1-4 Overview of the ARMv7-M debug features C1-7 Debug and reset C1-8 Debug event behavior C1-9 Debug register support in the SCS C1-11 Instrumentation Trace Macrocell (ITM) support C1-12 Data Watchpoint and Trace (DWT) support C1-14 Embedded Trace (ETM) support C1-15 Trace Port Interface Unit (TPIU) C1-16 Flash Patch and Breakpoint (FPB) support C1-17 Core Feature ID Registers AppxC-2 Deprecated Features in ARMv7M Glossary ARM DDI 0405A-01 Copyright © 2006 ARM Limited All rights reserved Beta vii Contents viii Copyright © 2006 ARM Limited All rights reserved Beta ARM DDI 0405A-01 Preface This preface describes the contents of this manual, then lists the conventions and terminology it uses • About this manual on page x • Unified Assembler Language on page xi • Using this manual on page xii • Conventions on page xiv • Further reading on page xv • Feedback on page xvi ARM DDI 0405A-01 Copyright © 2006 ARM Limited All rights reserved Beta ix Preface About this manual This manual documents the Microcontroller profile associated with version of the ARM Architecture (ARMv7-M) For short-form definitions of all the ARMv7 profiles see page A1-1 The manual consists of three parts: Part A The application level programming model and memory model information along with the instruction set as visible to the application programmer This is the information required to program applications or to develop the toolchain components (compiler, linker, assembler and disassembler) excluding the debugger For ARMv7-M, this is almost entirely a subset of material common to the other two profiles Instruction set details which differ between profiles are clearly stated Note All ARMv7 profiles support a common procedure calling standard, the ARM Architecture Procedure Calling Standard (AAPCS) Part B The system level programming model and system level support instructions required for system correctness The system level supports the ARMv7-M exception model It also provides features for configuration and control of processor resources and management of memory access rights This is the information in addition to Part A required for an operating system (OS) and/or system support software It includes details of register banking, the exception model, memory protection (management of access rights) and cache support Part B is profile specific ARMv7-M introduces a new programmer’s model and as such has some fundamental differences at the system level from the other profiles As ARMv7-M is a memory-mapped architecture, the system memory map is documented here Part C The debug features to support the ARMv7-M debug architecture, and the programmer’s interface to the debug environment This is the information required in addition to Parts A and B to write a debugger Part C covers details of the different types of debug: • halting debug and the related debug state • exception-based monitor debug • non-invasive support for event generation and signalling of the events to an external agent This part is profile specific and includes several debug features unique within the ARMv7 architecture to this profile x Copyright © 2006 ARM Limited All rights reserved Beta ARM DDI 0405A-01 Pseudo-code definition AppxA-30 Copyright © 2006 ARM Limited All rights reserved Beta ARM DDI 0405A-01 Appendix B Legacy Instruction Mnemonics The following table shows the pre-UAL assembly syntax used for Thumb instructions before the introduction of Thumb-2 and the equivalent UAL syntax for each instruction It can be used to translate correctly-assembling pre-UAL Thumb assembler code into UAL assembler code This table is not intended to be used for the reverse translation from UAL assembler code to pre-UAL Thumb assembler code In this table, 3-operand forms of the equivalent UAL syntax are used, except in one case where a 2-operand form needs to be used to ensure that the same instruction encoding is selected by a UAL assembler as was selected by a pre-UAL Thumb assembler Table AppxB-1 Pre-UAL assembly syntax Pre-UAL Thumb syntax Equivalent UAL syntax ADC , ADCS , , ADD , , # ADDS , , # ADD , # ADDS , # ADD , , ADDS , , ADD , SP ADD , SP, ARM DDI 0405A-01 Copyright © 2006 ARM Limited All rights reserved Beta Notes AppxB-1 Legacy Instruction Mnemonics Table AppxB-1 Pre-UAL assembly syntax AppxB-2 Pre-UAL Thumb syntax Equivalent UAL syntax Notes ADD , ADD , , If or is a high register and is not SP ADD , PC, # ADR , ADD , PC, # ADR , ADR form preferred where possible ADD , SP, # ADD , SP, # ADD SP, # ADD SP, SP, # AND , ANDS , , ASR , , # ASRS , , # ASR , ASRS , , B B B B BIC , BICS , , BKPT BKPT BL BL BLX BLX can be a high register BX BX can be a high register CMN , CMN , CMP , # CMP , # CMP , CMP , CPS CPS CPY , MOV , EOR , EORS , , LDMIA !, LDMIA , LDMIA !, If listed in Otherwise LDR , [, #] LDR , [, #] can be SP Copyright © 2006 ARM Limited All rights reserved Beta and can be high registers ARM DDI 0405A-01 Legacy Instruction Mnemonics Table AppxB-1 Pre-UAL assembly syntax Pre-UAL Thumb syntax Equivalent UAL syntax LDR , [, ] LDR , [, ] LDR , [PC, #] LDR , LDR , [PC, #] LDR , LDRB , [, #] LDRB , [, #] LDRB , [, ] LDRB , [, ] LDRH , [, #] LDRH , [, #] LDRH , [, ] LDRH , [, ] LDRSB , [, ] LDRSB , [, ] LDRSH , [, ] LDRSH , [, ] LSL , , # LSLS , , # LSL , LSLS , , LSR , , # LSRS , , # LSR , LSRS , , MOV , # MOVS , # MOV , ADDS , , #0MOV , MUL , MULS , , MVN , MVNS , NEG , RSBS , , #0 ORR , ORRS , , POP POP can include PC PUSH PUSH can include LR REV , REV , [...]... follows: ARMv7-A the application profile for systems supporting the ARM and Thumb instruction sets, and requiring virtual address support in the memory management model ARMv7-R the realtime profile for systems supporting the ARM and Thumb instruction sets, and requiring physical address only support in the memory management model ARMv7 -M the microcontroller profile for systems supporting only the Thumb instruction... Introduction ARMv7 overview, the different architecture profiles and the background to the Microcontroller (M) profile Chapter A2 Application Level Programmer’s Model Details on the registers and status bits available at the application level along with a summary of the exception support Chapter A3 ARM Architecture Memory Model Details of the ARM architecture memory attributes and memory order model Chapter... deterministic operation for an implementation are more important than absolute performance While profiles were formally introduced with the ARMv7 development, the A-profile and R-profile have implicitly existed in earlier versions, associated with the Virtual Memory System Architecture (VMSA) and Protected Memory System Architecture (PMSA) respectively Instruction Set Architecture (ISA) ARMv7 -M only... references to the system information part of the architecture specification as appropriate ARM DDI 0405A-01 Copyright © 2006 ARM Limited All rights reserved Beta A2-1 Application Level Programmer’s Model A2.1 The register model The application level programmer’s model provides details of the general-purpose and special-purpose registers visible to the application programmer, the ARM memory model, and the instruction... Virtual memory is not supported in ARMv7 -M A3-2 Copyright © 2006 ARM Limited All rights reserved Beta ARM DDI 0405A-01 ARM Architecture Memory Model A3.2 Alignment Support The system architecture can choose one of two policies for alignment checking in ARMv7 -M: • Support the unaligned access • Generate a fault when an unaligned access occurs The policy varies with the type of access An implementation... the memory has the sharable or non-sharable memory attribute, see Shared Normal memory on page A3-22 Uniprocessor systems are only required to support the non-shared memory model This means they can support synchronization primitives with the minimum amount of hardware overhead Figure A3-2 on page A3-9 shows an example minimal system A3-8 Copyright © 2006 ARM Limited All rights reserved Beta ARM DDI... includes information on data types and the operations (logical and arithmetic) supported by the ARM architecture ARM DDI 0405A-01 Copyright © 2006 ARM Limited All rights reserved Beta A1-3 Introduction A1-4 Copyright © 2006 ARM Limited All rights reserved Beta ARM DDI 0405A-01 Chapter A2 Application Level Programmer’s Model This chapter provides an application level view of the programmer’s model This... additions and improvements are also welcome xvi Copyright © 2006 ARM Limited All rights reserved Beta ARM DDI 0405A-01 Part A Application Chapter A1 Introduction Due to the explosive growth in recent years associated with the ARM architecture into many market areas, along with the need to maintain high levels of architecture consistency, ARMv7 is documented as a set of architecture profiles The ARM architecture. .. information on the ARM family of processors This manual provides architecture imformation It is designed to be read in conjunction with a Technical Reference Manual (TRM) for the implementation of interest The TRM provides details of the IMPLEMENTATION DEFINED architecture features in the ARM compliant core The silicon partner’s device specification should be used for additional system details ARM periodically... its documentation For the latest information and errata, some materials are published at http://www .arm. com Alternatively, contact your distributor or silicon partner who will have access to the latest published ARM information, as well as information specific to the device of interest ARM publications The first ARMv7 -M implementation is described in the Cortex -M3 Technical Reference Manual (ARM DDI ... ModelGen, Multi-ICE, PrimeCell, ARM7 TDMI, ARM7 TDMI-S, ARM9 TDMI, ARM9 E-S, ETM7, ETM9, TDMI, STRONG, are trademarks of ARM Limited All other products or services mentioned herein may be trademarks... ARMv7 -M introduces a new programmer’s model and as such has some fundamental differences at the system level from the other profiles As ARMv7 -M is a memory-mapped architecture, the system memory... Virtual memory is not supported in ARMv7 -M A3-2 Copyright © 2006 ARM Limited All rights reserved Beta ARM DDI 0405A-01 ARM Architecture Memory Model A3.2 Alignment Support The system architecture