Arithmetic builtin self test for embedded systems

This PDF book contains some OCR errors Arithmetic Built-in Self-Test for Embedded Systems Janusz Rajski Mentor Graphics Corporation, Wilsonville, Oregon Jerzy Tyszer Poznan University of Technology, Poland To join a Prentice Hall PTR Internet mailing list, point to: http://www.prenhall.com/mail_lists/ ISBN 0137564384, October 1997 Prentice Hall P T R Upper Saddle River, NJ 07458 Contents Preface vii 1 4 12 14 17 17 17 19 23 24 28 30 30 32 32 33 35 38 38 42 Built-in Self-Test 1.1 Introduction 1.2 Design for Testability 1.2.1 Controllability and Observability 1.2.2 Ad Hoc Techniques 1.2.3 Scan Designs 1.2.4 Boundary-Scan Architecture 1.2.5 Test Point Insertion 1.3 Generation of Test Vectors 1.3.1 Exhaustive Testing 1.3.2 Pseudo-Exhaustive Testing 1.3.3 Pseudo-Random Testing 1.3.4 Weighted Patterns 1.3.5 Reseeding of Linear Feedback Shift Registers 1.3.6 Diffraction 1.3.7 Pattern Mapping 1.3.8 Scan-Encoded Patterns 1.4 Compaction of Test Responses 1.4.1 Objectives and Requirements 1.4.2 Compaction Schemes 1.4.3 Error Models and Aliasing 1.5 BIST Schemes for Random Logic 1.5.1 Design Rules for BIST 1.5.2 Serial BIST Architectures Contents iv 1.6 1.5.3 1.5.4 1.5.5 1.5.6 BIST 1.6.1 1.6.2 1.6.3 Parallel BIST Architectures BIST controllers Modular BIST Automation of BIST for Memory Arrays Schemes Based on Deterministic Tests Pseudo-Random Testing Transparent BIST 44 47 49 52 53 55 57 57 Generation of Test Vectors 61 2.1 Additive Generators of Exhaustive Patterns 61 2.1.1 Basic Notions 62 2.1.2 Optimal Generators for Single Size Subspaces 65 2.1.3 Operand Interleaving 70 2.1.4 The Best Generators for Subspaces Within a Range of Sizes 72 2.2 Other Generation Schemes 76 2.2.1 Emulation of LFSRs and CAs 76 2.2.2 Weighted Patterns 77 2.2.3 Generators for Delay Testing 79 2.3 Two-Dimensional Generators 81 Test-Response Compaction 3.1 Binary Adders 3.2 l's Complement Adders 3.2.1 Steady State Analysis 3.2.2 Transient Behavior 3.2.3 Detection of Internal Faults 3.3 Rotate-Carry Adders 3.3.1 Fault-Free Operation 3.3.2 Test-Response Compaction 3.3.3 The Compaction Quality 3.4 Cascaded Compaction Scheme Fault Diagnosis 4.1 Analytical Model 4.2 Experimental Validation 4.3 The Quality of Diagnostic Resolution 4.4 Fault Diagnosis in Scan-Based Designs 87 88 90 90 93 100 101 102 104 108 112 117 117 121 122 126 Contents v BIST of Data-Path Kernel 5.1 Testing of ALU 5.1.1 Generation of Test Vectors 5.1.2 Test Application Phase 5.1.3 Compaction of Test Responses 5.1.4 Experimental Validation 5.2 Testing of the MAC Unit 5.3 Testing of the Microcontroller 135 135 137 137 139 139 140 141 Fault Grading 6.1 Fault Simulation Framework 6.2 Functional Fault Simulation 6.2.1 Ripple-Carry Adder 6.2.2 Subtracter 6.2.3 Carry-Lookahead Adder 6.2.4 Arithmetic and Logic Unit 6.2.5 Multiplexor 6.2.6 Array Multiplier 6.2.7 Booth Multiplier 6.3 Experimental Results 6.3.1 Performance of Building Block Models 6.3.2 High-Level Synthesis Benchmark Circuits 6.3.3 Comparison with PROOFS 147 148 150 152 153 153 154 154 154 159 163 164 165 166 High-Level Synthesis 7.1 Implementation-Dependent Fault Grading 7.1.1 Ripple-Carry Adder 7.1.2 Carry-Lookahead Adder 7.1.3 Carry-Skip Adder 7.2 Synthesis Steps 7.3 Simulation Results 173 174 174 174 175 176 178 ABIST at Work 8.1 Testing of Random Logic 8.1.1 Pseudo-Random Testing 8.1.2 Deterministic Testing 8.2 Memory Testing 8.2.1 Test program 8.2.2 Memory Array Faults 8.2.3 Read and Write Logic Faults 8.2.4 Address Decoder Faults 8.2.5 Multiple Faults 185 185 185 187 192 192 194 194 195 195 vi Contents 8.3 8.4 Digital Integrators 8.3.1 Testing of the Unmodified Integrator 8.3.2 Modified Integrator 8.3.3 Register File-Based Integrator Leaking Integrators 8.4.1 Unidirectional Faults 8.4.2 Bidirectional Faults 8.4.3 An Improved Compaction Scheme 196 197 199 203 207 209 215 218 Epilog 223 A Tables of Generators 227 B Assembly Language 245 Bibliography 249 Index 265 Preface T he semiconductor industry, driven by ever-increasing demands for higher performance and reliability, as well as greater functionality and speeds, continuously introduces new higher density technologies and new integrated circuits These circuits, like any other complex systems, not only have to meet the performance and functionality requirements, but they also have to be manufacturable In particular, they have to be highly testable in order to meet extremely high and constantly growing quality requirements The quality of testing is often defined as the number of faulty chips that pass the test for one million chips declared as good Many microelectronics companies have already set their testing quality goals to less than 100 dpm (defects per million), and there is intensive ongoing research to lower this number to less than 10 dpm as targeted in the six sigma project pioneered by Motorola Many integrated circuits are produced in large volume and very often operate at high speeds Since their manufacturing yield strongly depends on the silicon area, and their performance is directly related to the delays on critical paths, it is essential that the testing strategy provides a high fault coverage without a significant area overhead and performance degradation in order to build reliable and competitive products It is a well-known fact that the costs associated with detecting faults rise over thousands of times from the time the product is specified to the time the product is released to customers This is why the most effective way to prevent costly prototyping turns is to consider testing issues as early in the design cycle as possible Tremendous practical importance of this problem generated an immense amount of research in an attempt to develop testing schemes of the ultimate quality The increasing complexity of VLSI circuits, in the absence of a corresponding increase in the number of input and output pins, has made structured design for testability (DFT) and built-in self-test (BIST) two of the most important concepts in testing that profoundly Vlll influenced the area in recent years [16] Scan design is a good example of structured DFT where, in the test mode, all memory elements are connected in scan chains, through which the test vectors can be shifted in and out This solution enhances the controllability and observability of the circuit, and, as far as testing of combinational stuck-at faults is concerned, the circuit can be treated as a combinational network In BIST, the original circuit designed to perform the system function is ap­ pended with additional modules for generation of test patterns and compaction of test responses [16] Thus, the BIST approach can be applied at all levels of testing, starting from wafer and device to system and field testing It is widely accepted that appending these modules to the original circuit satisfies the high fault coverage requirement while reducing the dependence on expensive testing equipment However, it is also agreed that this solution compromises a circuit's area and performance as it inevitably introduces either a hardware overhead or additional delays and increased latency These delays may be excessive for high-speed circuits used in several new applications such as broadband packet switching, digital signal processing (DSP) for the asynchronous transfer mode (ATM), new generations of floating point processors, and others Therefore, BIST schemes are evaluated thoroughly on the basis of the fault coverage they provide, area overhead they require, and the performance penalty they intro­ duce A more detailed survey of existing DFT and BIST schemes is provided in Chapter Further information can be found in [2], [6], [7], and [16] With the cost of testing becoming a significant part of the cost of new mi­ croelectronics products, with inevitably upcoming challenges of new deep submicron technologies, with the increasing role of the hardware-software codesign, and last but not least, with ever-changing customer expectations, a demand for new solutions and tools appears to be relentless In particular, an un­ questionable proliferation of high-performance data-path architectures clearly demonstrates how inadequate existing BIST schemes can be if they are to entail non-intrusive and at-speed testing and yet guarantee a portability of test pro­ cedures Paradoxically, although the vastness of data-path architectures consist of powerful building blocks such as adders, multipliers, or arithmetic and logic units (ALUs) offering a very high computational potential, existing data-path BIST schemes are unfortunate examples of having sophisticated modules on the chip but remaining unable to translate this advantage into efficient nonintrusive testing schemes The approach presented in Chapters through is fundamentally different from the solutions introduced so far It uses several generic building blocks, which are already in the data path, as well as its very flexible and powerful con­ trol circuitry to generate patterns and compact test responses This permits de­ sign of complex software-based, and thus very portable, BIST functions These functions produce test vectors in the form of control signals, such as the type Preface IX of ALU operation, the addresses of registers, the input to shifters, etc., rather than data, as it is done in all other systems In such an environment, the need for extra hardware is either entirely eliminated or drastically reduced, test vec­ tors can be easily distributed to different modules of the system, test responses can be collected in parallel, and there is virtually no performance degradation Furthermore, the approach can be used for at-speed testing, thereby provid­ ing a capability to detect failures that may not be detected by conventional low-speed testing These characteristics make this method an exceptionally at­ tractive testing scheme for a wide range of circuits including high performance DSP systems, microprocessors, and microcontrollers In the following chapters we will discuss several new fundamental concepts and practical scenarios concerned with test generation, test application, and test-response compaction performed by means of building blocks of high perfor­ mance data paths We will show that even the simplest modules provide a very high potential for the integration of their features into a new generation of effi­ cient and portable BIST schemes As described techniques rest predominantly on arithmetic operations, these schemes will be jointly referred to as arithmetic built-in self-test (ABIST) methodology We will demonstrate that the ABIST paradigm virtually eliminates a traditional dichotomy between the functional mode and the testing mode, as testing will be based on regular operations and with no interference into the circuit structure It can be expected that it will create a next integration platform where off-line and on-line BIST schemes will be merged together Chapter introduces several test generation schemes that can be easily implemented in data paths based on adders, multipliers, and ALUs These schemes may replace commonly used LFSR-based test-pattern generators, and consequently allow it to mimic several commonly used generation techniques In particular, a new approach to generate pseudo-exhaustive test patterns by means of arithmetic operations is described The resultant test patterns provide a complete state coverage on subspaces of contiguous bits The Accumulator-Based Compaction (ABC) scheme for parallel compaction of test responses is the subject of Chapter We will demonstrate that the ABC scheme offers a quality of compaction similar to that of the best compactors based on multiple input signature registers (MISRs) or cellular automata (CA) of the same size The presented characteristics can be used to estimate the fault coverage drop for a given circuit under test (CUT) characterized by its detection profile The impact of the compactor's internal faults on the compaction quality is also examined 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ITC, pp 368-377, 1994 [189] N Zacharia, J Rajski, and J Tyszer, "Decompression of test data using variable-length seed LFSRs," Proc VLSI Test Symp., pp 426-433, 1995 Bibliography Index accumulator, 61, 62, 78, 82, 87-93, 100-102,104-112,137,138, 140,149,185,192,194,196, 197, 199, 201 adder, 35, 71, 81, 87, 140 l's complement, 90, 93, 121 internal faults, 100 binary, 62, 87, 137 carry-lookahead, 101, 153, 174 carry-skip, 175 ripple-carry, 101, 152, 174 faulty output, 152 rotate-carry, 102, 104, 108,110, 140, 141 address decode faults, 195 address generator, 54 adjacency testing, 79 aliasing probability, 32, 37, 38 iterative calculation, 217 limiting value, 92, 110, 211 maximum value, 96, 99 ALU, 35, 135, 154, 164 area overhead, vii, viii, 10, 58, 61, 173, 206 automated BIST, 47 behavioral synthesis, 173 BEST, 44 bi-directional fault, 215 BILBO, 44, 46 binary heap, 73 BIST controller, 42, 47, 58 bit-slice, 152, 154, 174-176 branch and bound algorithm, 73 bridging faults, 176, 180 built-in self-test, viii, CAD tools, 52 carry, see output carry CEBS, 42 cellular automata, 77, 112 checkerboard pattern, 56 checksum, 35 circular buffer, 188 circular self-test path, 46 clock domain, 40 comb filter, 196 combinational faults, 174 compaction scheme, 32, 165, 178, 185, 187, 193, 199, 208 cascaded, 112, 139, 195 transient behavior, 114 diagnostic resolution, 117 ones-count, 34 transient behavior, 37, 94 comparator, 56, 164 266 compression ratio, 191 concurrent BIST, 47 congruential generation, 82 contiguous subspaces, 63, 72 control path, 173 controllability, 4, 173 counter, 18, 34, 38, 47, 54, 56 coupling faults, 54 datapath, viii, ix, 82, 137, 139, 141, 142,144,173,174,178,180182, 205, 207 data-flow graph, 165, 176 decompressor, 26, 188 cycle, 189 defect level, vii delay faults, 10, 79 Delta-Sigma Modulation, 197 design for testability, vii deterministic patterns, 25 diagnostic program, 128-132 diagnostic resolution, 122 approximation, 125 diagnostic tree, 128 diffraction, 28 digital decimator, 196 easy-to-test faults, 25, 168 edge counting, 34 entropy, 173, 198 error compensation, 112, 195 error models, 36 error pattern, 89, 112, 114 opposite, 98 single, 94 error polynomial, 35 error-free signatures, 127 ex-situ BIST, 40 exhaustive state coverage, 65 exhaustive testing, 17 external faults, 89, 101 injection, 88, 92, 216 Index fault collapsing, 167 fault coverage, 2, 20, 84, 174, 201 fault diagnosis, 117 adaptive approach, 127 fault dictionary, 127 fault dropping, 147, 167 fault list, 121 fault location, 127 fault simulation, 101, 121, 139 concurrent, 169 functional, 148, 150-151 hierarchical, 148, 149 probabilistic, 16 feedback polynomial, 25 finite state machine, 47, 54, 205 full adder, 174, 197 full scan, 84 functional fault model, 148 gain factor, 209 gate level fault simulator, 83 Hamming distance, 28, 79, 80 hard-to-test faults, 25, 168 IEEE 1149.1, 12, 49, 53 in-situ BIST, 40 incrementer, 66, 69, 73 initial value, 66, 73 initialization, input carry, 72, 90, 137, 197 intellectual property, 53 inter-LFSR taps, 188 fc-latency, 63 latency, 64, 73, 178 leaking integrator, 207 LFSR, 19, 33, 54, 75, 76, 78, 79, 112, 121 characteristic polynomial, 19 interconnection network, 188 multiple polynomial, 26 Index 267 type 2, 76 linear dependency, 43, 83 LOCST, 42 LSSD, 10 double-latch design, 11 single-latch design, 11 oscillators, output carry, 66-69, 90, 174 group,175 stored, 104 overflow, 208 oversampling techniques, 196 MAC instruction, 140 MAC module, 135 MAC-based generator, 84, 140, 185 March C test, 55, 192-193 march tests, 54 Markov chain, 37, 57, 89, 91, 210 aperiodicity, 89 double stochastic, 90 irreducibility, 89 microcontroller, 141 microprogram counter, 142 microprogram memory, 5, 142 MISR, 34, 46, 56, 77, 112 mixed congruential generator, 141 mixed-mode generation, 25 Monte Carlo simulations, 82, 199, 201 m-sequence, 19 multiple chip modules, 81 multiple faults, 195 multiplexor, 10, 154, 164 multiplier, 81, 140 array, 141, 154 faulty output, 155 Booth, 141, 159 parity checking, 90 partitioning, pattern mapping, 30 performance degradation, vii-ix, 3, 10, 61, 173, 194, 203, 206 phase shifter, 44 power dissipation, 40 primitive fault, 91 sufficient conditions, 93 primitive polynomial, 19, 38, 83, 188 program memory, 138 PROOFS, 164, 166 propagation profile, 16 pseudo-exhaustive testing, 17 pseudo-random patterns, 19, 84, 121, 185, 191 pseudo-random testing, 19 neighborhood, 77 NPS faults, 54 observability, 5, 173, 180 off-line BIST, 39 on-line BIST, ix, 39 operand interleaving, 71 optimal generators, 65 gradient approach, 75 RAM, 53 random logic, 81, 185 random pattern resistant faults, 23 rank of fault, 89 read/write logic faults, 195 redundancy, redundant faults, Register Transfer Level, 53, 173 reseeding, 25, 76 ROM, 30 RUNBIST, 14, 48 saturation logic, 208 scan cells, 30 scan chains, 8, 81, 185 multiple, 81, 127 scrambling, 55, 199, 201 268 segmentation, 17 self-modifying program, 138 sensitized-path segmentation, 18 sequential depth, 173 serial access design, 55 spherical patterns, 28 SST, 47 state coverage, 62, 178, 198 stuck-at faults, 54, 84, 101,139,152, 154, 176, 180, 181, 191,197, 201, 205 stuck-open faults, 79 STUMPS, 43 subtractor, 153, 164 superposition, 46, 127 syndrome testing, 34 synthesis benchmarks, 163, 178 autoregressive lattice filter, 165 bandpass filter, 165, 181 discrete cosine transform, 165 elliptic wave filter, 165, 178 implementations, 166 terminal faults, 176 test access port, 12 test application time, 10, 17, 81 test confidence, 20 test cube, 25 test data compression, 25, 188-190 test kernel, 135 test length, 20, 21 test points, 6, 15, 173 test-per-clock BIST, 41 test-per-scan BIST, 42 testability, transition counting, 34 transition coverage, 199 transition diagram, 89, 105, 209 transition faults, 54 transition testing, 79 transparent BIST, 57 two-dimensional generator, 43, 81 Index underflow, 208 unidirectional faults, 212 unique signatures, 118 generation, 120 variable-length seeds, 26 verification testing, 18 weighted pseudo-random testing, 23 weighted random patterns, 77 generation, 78 ... Built-in Self- Test tests for redundant faults Moreover, redundant faults may invalidate tests for nonredundant faults Unfortunately, the redundancy is often introduced inadvertently and is therefore... required for the test hardware to perform test- pattern generation and test- response compaction Some performance degradation may be introduced due to the presence of multiplexers needed to apply the test. .. can be tested It reduces the cost of manufacturing testing by shortening the test application / Built-in Self- Test time, minimizing the amount of test data stored, and lowering the cost of test? ?