The quintessential PIC microcontroller

Sid Katzen The Quintessential PIC Microcontroller SPIN Springer’s internal project number, if known Engineering – Monograph (English) November 8, 2000 Springer-Verlag Berlin Heidelberg New York London Paris Tokyo Hong Kong Barcelona Budapest Contents List of Figures VI List of Tables XI List of Programs XIV Part I The Fundamentals Digital Representation Logic Circuitry 17 Stored Program Processing 41 Part II The Software The PIC16F84 Microcontroller 77 The Instruction Set 105 Subroutines and Modules 137 Interrupt Handling 171 Assembly language 197 High-Level Language 231 Part III The Outside World 10 The Real World 253 11 One Byte at a Time 271 VI Contents 12 One Bit at a Time 305 13 Time is of the Essence 361 14 Take the Rough with the Smooth 391 15 To Have and to Hold 431 16 A Case Study 455 Appendices A 14-bit Core Instruction Set 475 B Special Purpose Register Structure for the PIC16C74B 477 C C Instruction Set 479 D Acronyms and Abbreviations 481 Index 485 List of Figures 1.1 1.2 1.3 1.4 1.5 The NOT operation The AND function The inclusive-OR operation The XOR operation Detecting sign overflow 12 13 13 14 15 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 2.18 2.19 2.20 2.21 2.22 2.23 2.24 The 74LS00 quad 2-I/P NAND package Output structures Open-collector buffers driving a party line Sharing a bus The 74LS138 and ’139 MSI natural decoders The 74LS688 octal equality detector Addition Implementing a programmable adder/subtractor The 74LS382 ALU A ROM-implemented 1-bit adder The 2764 Erasable PROM Floating-gate MOSFET link The R S latch Using a R S latch to debounce a switch The D latch and flip flop The 74LS74 dual D flip flop The 74LS377 octal D flip flop array The 74LS373 octal D latch array An 8-bit ALU-accumulator processor The SISO shift register The T flip flop A modulo-16 ripple counter Generating timing waveforms The 6264 8196 × RAM 18 19 20 20 21 23 24 25 25 26 27 27 29 30 31 32 33 34 35 36 36 37 38 39 3.1 3.2 3.3 3.4 An elementary von Neumann computer An elementary Harvard architecture computer Executing the 1st instruction whilst fetching down the 2nd Parallel fetch and execute streams 42 44 45 50 VIII List of Figures 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 Programmer’s model The indirect mechanism Circular shifts The process Visualization of the task process Division by repetitive subtracting Double-precision shifting A 7-bit pseudo-random number generator 54 57 61 65 65 68 70 70 4.1 4.2 4.3 4.4 4.5 4.6 An example of a system based on a microcontroller Architecture of the PIC16F84 microcontroller Showing how all of the PC are altered when writing to PCL Internal clock sequencing waveforms The PIC16F84 Status register Data store memory map 81 85 86 87 89 92 5.1 5.2 5.3 5.4 General 14-bit core Status register The indirect mechanism The ith section of the compare-update sequence Generating a 13-bit Program-store address 109 109 112 114 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 Modular hardware implementing a PC Subroutine calling Using the hardware stack hold return addresses Nested subroutines System view of K × 100 ms delay subroutine The 7-segment display System diagram for the byte multiplication subroutine The stack frame Finding the square root of an integer 138 140 141 142 145 148 150 154 162 7.1 7.2 7.3 7.4 7.5 7.6 Detecting and measuring an external event Responding to an interrupt request The flag:mask pair The PIC 16F84’s interrupt logic Oven safety hardware Echo sounding hardware 172 175 176 178 188 195 8.1 8.2 8.3 8.4 8.5 8.6 8.7 Conversion from assembly-level source to machine code Absolute assembly-level code translation Relocatable assembly-level code translation Linking three source files Code building and testing tools MPLAB window MPLAB screen shot 198 202 211 213 219 221 222 List of Figures IX 9.1 9.2 9.3 9.4 Conversion from high-level source code to machine code Onion skin view of the steps leading to executable code Simulating our example program in MPLAB The active-low die patterns 233 234 242 250 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 Pinout for a variety of PIC family members Typical supply current versus clocking frequency Equivalent output circuit Typical oscillator configurations Configuration word for the PIC16F83/4 Manually resetting the PIC The sequence of events leading to startup on power-up Brown-out reset An alternative brown-out circuit 254 256 257 258 261 263 264 267 269 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12 11.13 11.14 11.15 The mid-range PIC 16CXX series Parallel Ports A and B A simplified typical I/O port line Reading and writing to a port bit set to input or output Sinking and sourcing current Port A I/O pin driver structure Interfacing switches to a port line Port B’s weak pull-up option Interfacing to a keypad The Port B change feature A multi-zone intruder alarm Source current against voltage The stepper motor Using port expansion to drive three 7-segment displays Scanning a 3-digit 7-segment array Low-level output voltage against sink current 272 273 275 276 278 280 280 281 285 287 290 294 298 299 304 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 12.11 12.12 12.13 12.14 The smart card 305 Serial interface to a 3-digit 7-segment display 307 Logic functional diagram of the 74HCT595 octal shift register 309 Serially interfacing to a DAC0800 digital to analog converter 310 Serially interfacing to the multi-zone intruder alarm 311 The MAX549A SPI dual 8-bit DAC 314 SPI waveforms for the MAX549A 316 Multiple MAX549As on the one SPI circuit 316 The basic Serial Synchronous Port 317 The SSP CONtrol and STATus registers 318 SSP SPI-mode master waveforms 321 A multidrop SPI communications network 322 Data transfer on the I2 C bus 325 Sharing the SCL and SDA bus lines 326 X List of Figures 12.15 12.16 12.17 12.18 12.19 12.20 12.21 12.22 12.23 12.24 12.25 A I2 C packet transmission The MAXIM MAX518 I2 C dual digital to analog converter Minimum timing relationships for the Fast I2 C mode Transmitting the string "PIC" in the asynchronous mode The PIC USART configured for asynchronous communication Some signalling configurations Communicating with a PC via an RS-232 link The 24XXX series of I2 C serial EEPROMs EEPROM Read and Write waveforms Interfacing the DS1820 1-Wire digital thermometer A LCD display 327 328 329 336 342 347 349 352 355 356 360 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 13.10 13.11 The integral PIC Watchdog timer The Option register Simplified equivalent circuit for Timer Counting cans of beans on a conveyer belt Functional equivalent circuit for Timer The CCP1 module set to Compare mode Capturing the time of an event A simplified equivalent circuit for Timer Pulse width modulation Timer and the PWM CCP mode An event manifesting itself as a pulse duration 362 363 365 366 372 375 377 379 380 381 387 14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 14.9 14.10 14.11 14.12 14.13 14.14 14.15 14.16 14.17 14.18 Analog world – digital processing The quantizing process The analog–digital process Illustrating aliasing Initializing the 8-4-2-1 capacitor network Simplified view of the A/D converter The successive approximation process The 8-bit 8-channel analog to digital conversion module Configuring the analog inputs for Port A and Port E Interrupt control for the ADC module R-2R digital-to-analog conversion The Maxim MAX506 quad 8-bit D/A converter Generating a continuous sawtooth using a MAX506 DAC Buffered data acquisition A level-shifting resistor network ECG detection strategy A controllable external voltage circuit Pinning for the PIC16C71 391 393 396 397 398 400 402 404 405 408 416 418 419 420 423 426 429 429 15.1 The PIC16F8X Data EEPROM module 433 15.2 The PIC16F8X EECON1 register 434 List of Figures XI 15.3 15.4 15.5 15.6 15.7 15.8 The first 32 bytes of EEPROM The PIC16F87X flash and Data EEPROM storage system The PIC16F87X EEPROM Control register View of the flash Program module Configuration word for the PIC16F87X devices Watchdog timer period versus temperature 438 440 441 445 445 448 16.1 16.2 16.3 16.4 16.5 The annunciator hardware The modular software structure The Main process Programming the PIC from MPLAB The Microchip PICSTART Plus programmer 456 458 468 472 473 List of Tables 1.1 1.2 1.3 7-bit ASCII characters Some common bit groupings Different ways of representing the quantities decimal 0…20 3.1 Our BASIC computer’s instruction set 53 5.1 5.2 5.3 5.4 Move instructions Arithmetic Logic instructions Program Counter instructions 115 117 121 127 6.1 6.2 Subroutine and interrupt handling instructions 139 The 7-segment lookup table showing byte[N] being extracted 149 8.1 8.2 8.3 8.4 8.5 8.6 8.7 The listing file root.lst The absolute 8-bit Intel format object-code file root.hex The error file Part of Microchip’s file p16f84.inc The pic16f84.lkr linker command file The output linker map file rms.asm The resulting absolute object file rms.hex 9.1 Resulting assembly-level CCS compiler output after linking 240 206 206 207 209 212 218 219 10.1 PIC16F83/4 Special-Purpose Register file reset summary 263 10.2 Power-up reset and sleep timeouts 265 10.3 Reset conditions 266 11.1 Summary of mid-range PIC parallel I/O provision 272 11.2 Energization pattern for the eight field directions 294 12.1 The SSP Mode bits 319 14.1 Quantization parameters 394 14.2 ADC clocking frequency versus device crystal frequency 401 14.3 Configuring the ADC port pins in the PIC16C73/74 devices 405 478 The Quintessential PIC Microcontroller File address Name RBPU INTEDG Power-on Reset All other Resets Bank Uses contents of this to address Data memory (not a physical register) 80h INDF 81h 82h OPTION PCL1 83h STATUS1 84h FSR 85h TRISA 86h TRISB Port B Data Direction Register 87h TRISC 88h TRISD 89h TRISE IBF OBF IBOV 8Ah PCLATH — — — 8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF 8Ch PIE1 PSPIE ADIE RCIE TXIE SSPIE CCPIE TMR2IE 8Dh PIE2 — — — — — — — CCP2IE —— ——0 —— ——0 8Eh PCON — — — — — — POR BOR —— ——?? —— ——UU 92h PR2 1111 1111 1111 1111 93h SSPADD 94h SSPSTAT 98h TXSTA 99h SPBRG 9Fh ADCON1 X U ? — Note 1: T0CS T0SE PSA PS2 PS1 PS0 Lower-order bits of the Program Counter IRP RP1 RP0 TO PD Z DC C 000? ?UUU UUUU UUUU —-11 1111 —-11 1111 1111 1111 1111 1111 Port C Data Direction Register 1111 1111 1111 1111 Port D Data Direction Register 1111 1111 1111 1111 Port A Direction Register — PSPM — TRISE2 TRISE1 TRISE0 0000 –111 0000 –111 ——0 0000 ——0 0000 RBIF 0000 000X 0000 000U TMR1IE 0000 0000 0000 0000 Write buffer for top PC bits Timer Period Register — — D/A CSRC TX9 TXEN P S R/W UA BF SYNC — BRGH TRMT TX9D Baud Rate Generator — 0000 0000 XXXX XXXX Synchronous Serial Port (I2 C mode) Address Register — 1111 1111 0001 1XXX Indirect Data memory address pointer — 1111 1111 0000 00000 — Not known Unchanged Value depends on reset condition Unimplemented; read as Next instruction address if PIC in Sleep mode — — PCFG2 PCFG1 PCFG0 0000 0000 0000 0000 —-00 0000 —-00 0000 0000 –010 0000 –010 0000 0000 0000 0000 —— —000 —— —000 Appendix C C Instruction Set Operator Operation Example Top priority Direction (associativity) ⇒ () [] -> Function call Array element Structure element Structure element using a pointer sqr() x[6] PIA1.CRA Unary operators Direction (associativity) ⇐ ! ˜ + ++ -& * (type) sizeof Logical NOT Inversion (1’s complement) Negative Unary plus Increment Decrement Address of Contents of address Cast Size of object in bytes !x ˜x y=-x y=x- +(y+z) x++ or ++x x or x &x *address (long)x sizeof x Arithmetic Direction (associativity) ⇒ * / % Multiplication Division Remainder z=x*y z=x/y z=x%y (Integer types only) + - Addition Subtraction z=x+y z=x-y Shift Integer types only Direction (associativity) ⇒ >> >3 z=xz)?5:10 x=5 if y>z True else x=10 Assignment Direction (associativity) ⇐ = += -= *= /= %= &= ˆ= |= = Simple Compound Compound Compound Compound Compound Compound Compound Compound Compound Compound plus minus multiply divide remainder bit AND bit EX-OR bit OR shift left shift right x=3 x+=3 e.g (x=x+3) x-=3 e.g (x=x-3) x*=3 e.g (x=x*3) x/=3 e.g (x=x/3) x%=3 e.g (x=x%3) x&=3 e.g (x=x&3) xˆ=3 e.g (x=xˆ3) x|=3 e.g (x=x|3) x3) Direction (associativity) ⇒ , Concatenate if(x=0,y=3;x[...]... then: • When B = 0 then f = A; that is the output follows the data input • When B = 1 then f = A; that is the output is the inverse of the data input Thus an XOR gate can be used as a programmable inverter Another useful property considers the XOR function as a logic differentiator The XOR truth table shows that the gate gives a true output if the two inputs differ Alternatively, the ENOR truth table... totalized first, passing a carry if necessary to the next left column The process ends with 6 Sometimes 7 Which called 8-4-2-1 code after the weightings of the first four lowest columns you had to do way back in the mists of time in primary/elementary school! 8 The Quintessential PIC Microcontroller the most significant bit (MSB) column, its carry being the new MSD of the sum For example: 1 0 1 0 0 1 96 + 37... common resource, so only the selected device can be allowed access to the bus at any one time The access has to be withdrawn immediately the data has been read, so that another device 2 Logic Circuitry 21 can use the resource As shown in the diagram, each Thing connected symbol When selected, only to the bus outputs, designated by the the active logic levels will drive the bus lines The 74LS244 octal (×8)... know that the when Minuend is greater than the Subtrahend, the two operands are interchanged and a minus sign is appended to the outcome; that is −(Subtrahend − Minuend) If we do not swap, as in (a) above, then the outcome appears to be incorrect In fact 41 is correct, in that this is the difference between 59 (the correct outcome) and 100 41 is described as the 10’s complement of 59 Furthermore, the fact... 0 1 1 1 1 1 1 1 1 (b) The 74LS138 3- to 8-line decoder Fig 2.5 The 74LS138 and ’139 MSI natural decoders 22 The Quintessential PIC Microcontroller The NAND gate networks shown in Fig 2.5 are typical MSI-complexity ICs Remembering that the output of a NAND gate is logic 0 only when all its inputs are logic 1 (see Fig 1.2(c) on page 13) then we see that for any combination of the Select inputs B A (21... is High, then irrespective of the state of B A (the X entries in the truth table denote a ‘don’t care’ situation) all outputs remain deselected – logic 1 An example of the use of the 74LS139 is given in Fig 2.23 The 74LS138 of Fig 2.5(b) is similar, but implements a 3 to 8-line decoder function The state of the three address lines C B A (22 21 20 ) n selects one only of the eight outputs Yn The 74LS138... integrated circuit together with support circuitry, memories and peripheral interface devices Although the MCU is often confused with its better known cousin the microprocessor in its role of the driving force of the ubiquitous personal computer, the vast majority of both microprocessors and microcontrollers are embedded into an assemblage of other digital components The first microprocessors in the early 1970s... Appreciate the function of a RAM The first integrated circuits, available at the end of the 1960s, were mainly NAND, NOR and NOT gates The most popular family of logic functions was, and still is, the 74 series transistor transistor logic (TTL); introduced by Texas Instruments and soon copied by all the major major semiconductor manufacturers 18 The Quintessential PIC Microcontroller [74LS00] 1A 3Y 8... microprocessor, the world is seen in terms of patterns of digits The decimal (or denary) system represents quantities in terms of the ten digits 0…9 Together with the judicious use of the symbols +, − and any quantity in the range ±∞ can be depicted Indeed non-numeric concepts can be encoded using numeric digits For example the American Standard Code for Information Interchange (ASCII) defines the alphabetic... 1.3 The inclusive-OR operation The inclusive-OR operator gives an anything function Here the outcome is true when any input or inputs are true (hence the ≥ 1 label in the logic symbol) In Fig 1.3 two inputs are shown, but any number of variables may be ORed together ORing is sometimes referred to as a logic sum, and the + used as the mathematical operator; thus f = B + A In an analogous manner to the ... Thus the latch is reset by pulsing the R input 30 The Quintessential PIC Microcontroller In the normal course of events – that is assuming that the R and S inputs are not both active at the same... the 1D input On each at the Clock input C1 the data at the 1D input will be latched in to appear at the Q output As it is the complement of this output that is fed back to the input, then the. .. back to 0, then the lower gate remains (as the Q feedback is 1) and the top gate output also remains unaltered Thus the latch is set by pulsing the S input • If the R input goes to 1, then output