Mitigating voltage sags by optimal placement of series compensation devices using genetic algorithm

MITIGATING VOLTAGE SAGS BY OPTIMAL PLACEMENT OF SERIES COMPENSATION DEVICES USING GENETIC ALGORITHM YU ZHEMIN NATIONAL UNIVERSITY OF SINGAPORE 2003 MITIGATING VOLTAGE SAGS BY OPTIMAL PLACEMENT OF SERIES COMPENSATION DEVICES USING GENETIC ALGORITHM YU ZHEMIN A THESIS SUBMITTED FOR THE DEGREE OF MASTER OF ENGINEERING DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2003 ACKNOWLEDGMENTS The author takes this opportunity to place on record his sincere thanks and gratitude towards his supervisor Associate Professor C S Chang, Department of Electrical and Computer Engineering, National University of Singapore for his valuable suggestions, continuous encouragements, timely advice and skilful guidance throughout the research work and writing of the thesis The author would also like to thank his wonderful family, for their many years of support and encouragement that prepared for his Master’s degree Not forgetting his dearest wife for her patience and constant support Also thankful to Mr H C Seow, Senior Laboratory Technologist, Department of Electrical and Computer Engineering, NUS for his timely assistance regarding computer problems Finally, special appreciations to his colleagues in the Power System Laboratory, and all others who have helped in way or other during the entire period of the research work i TABLE OF CONTENTS ACKNOWLEDGMENTS i TABLE OF CONTENTS ii LIST OF FIGURES vii LIST OF TABLES x LIST OF PUBLICACTIONS xii ABSTRACT xiii CHAPTER INTRODUCTION 1-1 1.1 BACKGROUND OF THE RESEARCH 1-1 1.1.1 1.1.2 1.1.3 1.1.4 Power Quality Phenomena 1-1 Definition of Voltage Sag 1-2 The Necessity of Mitigating Sag 1-5 Previous Works on Voltage Sag Mitigation 1-6 1.2 OBJECTIVE OF THIS THESIS 1-11 1.3 ORGANIZATION OF THIS THESIS .1-12 CHAPTER MITIGATION OF SAGS BY OPTIMAL PLACEMENT OF COMPENSATION DEVICES 2-1 2.1 DISTRIBUTED MITIGATION VS CENTRAL MITIGATION .2-1 ii 2.2 SELECTING SAG COMPENSATION DEVICES .2-3 2.3 EVALUATING CANDIDATE SOLUTION .2-4 2.3.1 Step 1: Obtain System Sag Data 2-5 2.3.2 Step 2: Obtain Equipment Tolerance Performance .2-6 2.3.3 Step 3: Evaluation and Optimization 2-7 2.4 OPTIMIZATION BY HEURISTIC ALGORITHMS .2-8 CHAPTER MODELING OF THYRISTOR VOLTAGE REGULATOR 3-1 3.1 INTRODUCTION 3-1 3.2 PRINCIPLE DESCRIPTION 3-2 3.3 MERITS OF TVR .3-4 3.4 SIMULATION OF REGULATING CHARACTERISTIC 3-5 3.4.1 3.4.2 3.4.3 3.4.4 3.5 Description of Simulation Model 3-5 Signal Detection 3-6 Control Circuit .3-7 Two Simulation Cases (One Phase Only) 3-9 SIMULATION OF SAG MITIGATION IN DISTRIBUTION SYSTEM 3-12 3.5.1 3.5.2 3.5.3 3.5.4 Modeling Description 3-12 Simulation of Single-line-to-ground Fault .3-14 Comparison Delta Connection to Star Connection 3-17 Switching Dynamic Process and Response Time 3-22 3.6 HYSTERESIS LOOP CONTROL TO IMPROVE STABILITY 3-24 3.7 CONCLUSIONS .3-31 CHAPTER PQ IMPROVEMENT BY OPTIMAL PLACEMENT OF TVR 4-1 4.1 INTRODUCTION 4-1 4.2 DESCRIPTION OF STUDY SYSTEM AND VOLTAGE SAG PROBLEM 4-2 4.2.1 System Configuration and Technical Data 4-2 4.2.2 Computation of Study System .4-5 iii 4.3 REGULATING VOLTAGE BY TVR 4-8 4.3.1 Equivalent Model of TVR 4-8 4.3.2 Installation and Effect of TVR 4-12 4.4 FORMULATION OF OBJECTIVE FUNCTION .4-14 4.5 SEARCHING OPTIMAL SOLUTION 4-18 4.6 PROGRAMMING AND RESULTS 4-22 4.7 DISCUSSIONS ABOUT APPLICATION OF GA 4-26 4.7.1 Problem of Stagnancy and Stop Criteria 4-26 4.7.2 Parameters Selection of GA .4-27 4.8 CONCLUSIONS .4-29 CHAPTER STOCHASTIC ECONOMIC ASSESSMENT OF VOLTAGE SAG MITIGATION .5-1 5.1 INTRODUCTION 5-1 5.2 PLACEMENT OF DVR AND TVR FOR VOLTAGE SAG MITIGATION 5-2 5.2.1 Placement of DVR and TVR .5-2 5.2.2 Equivalent Model of DVR 5-3 5.3 METHODS OF ECONOMIC ANALYSIS FOR SAG MITIGATION SOLUTION .5-5 5.3.1 Selection of Economic Analysis Tool 5-5 5.3.2 Cost Function Using Equivalent First Cost Method 5-6 5.3.3 Conflict Between Cim and Cr .5-7 5.4 COST OF SAG MITIGATION SOLUTION - Cim .5-7 5.5 COST TO CONSUMERS AFTER INSTALLATION OF COMPENSATION DEVICES – C r 5-9 5.5.1 Difficulties of Traditional Method .5-9 5.5.2 Proposed Weighted Sampling Method .5-10 5.5.3 Voltage Seen by Individual Consumers During Voltage Sags at PCC 5-13 5.6 SEARCHING FOR OPTIMUM PLACEMENT .5-14 5.6.1 Definition of Objective Function .5-14 5.6.2 Sectionalized Coding of Solution 5-15 iv 5.6.3 Reversion of GA Strings 5-17 5.7 CONCLUSIONS AND DISCUSSIONS 5-19 CHAPTER CASE STUDIES AND RESULT ANALYSIS 6-1 6.1 INTRODUCTION 6-1 6.2 DATA OF CASE STUDIES 6-1 6.2.1 Sag Data .6-1 6.2.2 Customer Tolerance Characteristics 6-4 6.2.3 Combination of Data for Case Studies 6-4 6.3 NUMERICAL RESULTS AND ANALYSIS 6-5 6.4 PERFORMANCE COMPARISON 6-9 6.4.1 Performance Under Various Initial Conditions 6-9 6.4.2 Performance Under Various Coding System 6-10 6.5 CONCLUSIONS .6-12 CHAPTER CONCLUSIONS AND FUTURE WORK 7-1 7.1 CONCLUSIONS 7-1 7.2 CONTRIBUTIONS FROM THE PROJECT .7-3 7.3 RECOMMENDATIONS OF FUTURE WORK 7-4 APPENDIX A DYNAMIC VOLTAGE RESTORER A-1 A.1 BASIC PRINCIPLE A-1 A.2 VOLTAGE SOURCE INVERTER (VSI) A-2 APPENDIX B GENETIC ALGORITHM B-1 B.1 INTRODUCTION B-1 B.2 BASIC CONCEPTS B-1 v APPENDIX C MATLAB MODELS OF TVR C-1 APPENDIX D BUS ADMITTANCE MATRIXES OF STUDY SYSTEM C-1 REFERENCES Ref-1 vi LIST OF FIGURES Figure 1.1 Typical waveform of sag 1-2 Figure 1.2 Voltage divider model for a voltage sag 1-4 Figure 1.3 Percentages of PQ events observed by semiconductor companies 1-5 Figure 1.4 Establishment of the sag problem and various ways of mitigation 1-6 Figure 1.5 Effect of DVR to a sag caused by three-phase fault .1-9 Figure 2.1 Central mitigation and distributed mitigation 2-2 Figure 2.2 Problem-solving flow chart for sags .2-4 Figure 2.3 Scatter diagram of sags obtained by one year of monitoring at an industrial site 2-6 Figure 2.4 Example of the range of ASD sag tolerances 2-7 Figure 3.1 TVR circuit (one-phase only) 3-2 Figure 3.2 Simulation block diagram of TVR (one-phase) .3-5 Figure 3.3 Control pulse generation of TVR 3-8 Figure 3.4 Control logic circuit of TVR 3-8 Figure 3.5 Regulating characteristic of TVR in Case (1) 3-10 Figure 3.6 Regulating characteristic of TVR in Case (2) 3-12 Figure 3.7 TVR in distribution system to protect a sensitive load 3-13 Figure 3.8 Voltage regulation ability of TVR in a SLG fault (Delta connection) 3-15 Figure 3.9 Voltage regulation ability of TVR in a SLG fault shown in rms value (Delta connection) 3-17 Figure 3.10 Phasor diagram of sag at the two sides of the Y/d11 transformer 3-18 Figure 3.11 Comparison of delta connected TVR and star connected TVR .3-19 Figure 3.12 Voltage regulation by star connected TVR 3-21 vii Figure 3.13 Switching process and response time of half cycle rms detection .3-23 Figure 3.14 Response time of one cycle rms detection .3-23 Figure 3.15 Hysteresis loop control of TVR .3-25 Figure 3.16 Block diagram of hysteresis loop control 3-26 Figure 3.17 Comparison of hysteresis and non-hysteresis control under flicker noise 3-27 Figure 3.18 Pulse generation under different control methods 3-28 Figure 3.19 Pulse under different control methods 3-29 Figure 3.20 Comparison of hysteresis and non-hysteresis control under Gaussian noise 3-30 Figure 4.1 Connection of study system .4-2 Figure 4.2 Voltage magnitudes of the study system 4-7 Figure 4.3 Equivalent model of TVR 4-9 Figure 4.4 Installation of TVR and the effect to the system 4-13 Figure 4.5 Function for f and f max 4-17 Figure 4.6 A typical GA string 4-19 Figure 4.7 Flow chart of GA optimization for TVR placement 4-21 Figure 4.8 Optimal TVR placement and voltage distribution 4-22 Figure 4.9 Convergence performance .4-23 Figure 4.10 TVR placement and voltage distribution for two sub-optimal solutions 4-25 Figure 4.11 Performance comparison under various values of Pc (fixed Pm = 0.01 ) 4-28 Figure 4.12 Performance comparison under various values of Pm (fixed Pc = 0.75 ) 4-28 Figure 5.1 Placement of DVR and TVR 5-2 viii APPENDIX D APPENDIX D Bus Admittance Matrixes of Study System BUS ADMITTANCE MATRIXES OF STUDY SYSTEM The base values for the per unit computation are: Capacity base value: S B = 100 MVA Voltage base value: VB = 10kV Then the impedance base value is: ZB = V B2 =1 SB D-1 APPENDIX D Bus Admittance Matrixes of Study System Table D.1 Bus admittance matrix of the study system (to be continued) node 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 4.0643 - 3.096i -4.0643 + 1.6674i 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4.0643 + 1.6674i 8.5003 - 3.4878i -4.4338 + 1.819i 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4.4338 + 1.819i 10.145 - 3.1319i -3.1366 + 0.87069i 0 0 0 0 0 -2.5746 + 0.4422i 0 0 0 0 0 0 0 0 0 0 -3.1366 + 0.87069i 6.5894 - 1.8297i -3.4502 + 0.95775i 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3.4502 + 0.95775i 6.9031 - 1.9168i -3.4502 + 0.95775i 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3.4502 + 0.95775i 8.0845 - 1.7537i -2.0597 + 0.35376i 0 0 0 0 0 0 0 0 0 -2.5746 + 0.4422i 0 0 0 0 0 0 -2.0597 + 0.35376i 7.2089 - 1.2382i -2.5746 + 0.4422i 0 0 0 0 0 0 0 0 0 0 -2.5746 + 0.4422i 0 0 0 0 0 -2.5746 + 0.4422i 4.2936 - 0.73825i -1.7164 + 0.2948i 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1.7164 + 0.2948i 4.2936 - 0.73825i -2.5746 + 0.4422i 0 0 0 0 0 0 0 0 0 0 0 0 D-2 APPENDIX D Bus Admittance Matrixes of Study System (Continued) Table D.1 Bus admittance matrix of the study system (to be continued) node 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 10 0 0 0 0 -2.5746 + 0.4422i 4.4496 - 0.76505i -1.8724 + 0.3216i 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 -1.8724 + 0.3216i 4.4496 - 0.76505i -2.5746 + 0.4422i 0 0 0 0 0 0 0 0 0 0 0 12 0 0 0 0 0 -2.5746 + 0.4422i 5.15 - 0.88475i -2.5746 + 0.4422i 0 0 0 0 0 0 0 0 0 0 13 0 0 0 0 0 -2.5746 + 0.4422i 4.2993 - 0.741i -1.7164 + 0.2948i 0 0 0 0 0 0 0 0 0 0 14 0 0 0 0 0 0 -1.7164 + 0.2948i 1.7172 - 0.29515i 0 0 0 0 0 0 0 0 0 0 15 0 -2.5746 + 0.4422i 0 0 0 0 0 5.15 - 0.88475i -2.5746 + 0.4422i 0 0 0 0 0 0 0 0 0 16 0 0 0 0 0 0 0 -2.5746 + 0.4422i 6.8883 - 1.6398i -4.3128 + 1.1972i 0 0 0 0 0 0 0 0 17 0 0 0 0 0 0 0 -4.3128 + 1.1972i 7.1889 - 1.9958i -2.8752 + 0.79813i 0 0 0 0 0 0 0 0 18 0 0 0 0 0 0 0 0 -2.8752 + 0.79813i 5.4185 - 1.3774i -2.5407 + 0.57805i 0 0 0 0 0 0 0 D-3 APPENDIX D Bus Admittance Matrixes of Study System (Continued) Table D.1 Bus admittance matrix of the study system (to be continued) node 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 19 0 0 0 0 0 0 0 0 -2.5407 + 0.57805i 5.084 - 1.1573i -2.5407 + 0.57805i 0 0 0 0 0 0 0 20 0 0 0 0 0 0 0 0 0 -2.5407 + 0.57805i 5.3381 - 1.2151i -2.7948 + 0.63585i 0 0 0 0 0 0 21 0 0 0 0 0 0 0 0 0 -2.7948 + 0.63585i 4.8571 - 0.99086i -2.0597 + 0.35376i 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 -2.0597 + 0.35376i 4.122 - 0.70877i -2.0597 + 0.35376i 0 0 0 0 0 23 0 0 0 0 0 0 0 0 0 0 -2.0597 + 0.35376i 4.122 - 0.70877i -2.0597 + 0.35376i 0 0 0 0 0 24 0 0 0 0 0 0 0 0 0 0 0 -2.0597 + 0.35376i 3.7787 - 0.64981i -1.7164 + 0.2948i 0 0 0 0 25 0 0 0 0 0 0 0 0 0 0 0 -1.7164 + 0.2948i 1.7254 - 0.29915i 0 0 0 0 26 0 0 -2.5746 + 0.4422i 0 0 0 0 0 0 0 0 0 4.4496 - 0.76505i -1.8724 + 0.3216i 0 0 0 27 0 0 0 0 0 0 0 0 0 0 0 0 -1.8724 + 0.3216i 4.448 - 0.76428i -2.5746 + 0.4422i 0 0 0 D-4 APPENDIX D Bus Admittance Matrixes of Study System (Continued) Table D.1 Bus admittance matrix of the study system node 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 28 0 0 0 0 0 0 0 0 0 0 0 0 0 -2.5746 + 0.4422i 2.5756 - 0.44268i 0 0 0 29 0 0 0 -2.5746 + 0.4422i 0 0 0 0 0 0 0 0 0 0 5.1502 - 0.88488i -2.5746 + 0.4422i 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2.5746 + 0.4422i 4.292 - 0.73748i -1.7164 + 0.2948i 0 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1.7164 + 0.2948i 3.4354 - 0.59085i -1.7164 + 0.2948i 0 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1.7164 + 0.2948i 4.2936 - 0.73825i -2.5746 + 0.4422i 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2.5746 + 0.4422i 5.1518 - 0.88565i -2.5746 + 0.4422i 34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2.5746 + 0.4422i 2.5772 - 0.44345i D-5 APPENDIX D Bus Admittance Matrixes of Study System Table D.2 Bus admittance matrix of the study system under the optimal TVR placement (to be continued) node 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 4.0643 - 3.096i -3.8814 + 1.5924i 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3.8814 + 1.5924i 8.1428 - 3.3411i -4.4338 + 1.819i 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -4.4338 + 1.819i 10.145 - 3.1319i -3.1366 + 0.87069i 0 0 0 0 0 -2.5746 + 0.4422i 0 0 0 0 0 0 0 0 0 0 -3.1366 + 0.87069i 6.5894 - 1.8297i -3.4502 + 0.95775i 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3.4502 + 0.95775i 6.9031 - 1.9168i -3.295 + 0.91466i 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -3.295 + 0.91466i 7.781 - 1.6695i -2.0597 + 0.35376i 0 0 0 0 0 0 0 0 0 -2.5746 + 0.4422i 0 0 0 0 0 0 -2.0597 + 0.35376i 7.2089 - 1.2382i -2.5746 + 0.4422i 0 0 0 0 0 0 0 0 0 0 -2.5746 + 0.4422i 0 0 0 0 0 -2.5746 + 0.4422i 4.2936 - 0.73825i -1.6392 + 0.28154i 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1.6392 + 0.28154i 4.1426 - 0.71232i -2.5746 + 0.4422i 0 0 0 0 0 0 0 0 0 0 0 0 D-6 APPENDIX D Bus Admittance Matrixes of Study System (Continued) Table D.2 Bus admittance matrix of the study system under the optimal TVR placement (to be continued) node 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 10 0 0 0 0 -2.5746 + 0.4422i 4.4496 - 0.76505i -1.8724 + 0.3216i 0 0 0 0 0 0 0 0 0 0 0 11 0 0 0 0 -1.8724 + 0.3216i 4.4496 - 0.76505i -2.5746 + 0.4422i 0 0 0 0 0 0 0 0 0 0 0 12 0 0 0 0 0 -2.5746 + 0.4422i 5.15 - 0.88475i -2.5746 + 0.4422i 0 0 0 0 0 0 0 0 0 0 13 0 0 0 0 0 -2.5746 + 0.4422i 4.2993 - 0.741i -1.7164 + 0.2948i 0 0 0 0 0 0 0 0 0 0 14 0 0 0 0 0 0 -1.7164 + 0.2948i 1.7172 - 0.29515i 0 0 0 0 0 0 0 0 0 0 15 0 -2.5746 + 0.4422i 0 0 0 0 0 5.15 - 0.88475i -2.5746 + 0.4422i 0 0 0 0 0 0 0 0 0 16 0 0 0 0 0 0 0 -2.5746 + 0.4422i 6.8883 - 1.6398i -4.1187 + 1.1433i 0 0 0 0 0 0 0 0 17 0 0 0 0 0 0 0 -4.1187 + 1.1433i 6.8095 - 1.8904i -2.8752 + 0.79813i 0 0 0 0 0 0 0 0 18 0 0 0 0 0 0 0 0 -2.8752 + 0.79813i 5.4185 - 1.3774i -2.5407 + 0.57805i 0 0 0 0 0 0 0 D-7 APPENDIX D Bus Admittance Matrixes of Study System (Continued) Table D.2 Bus admittance matrix of the study system under the optimal TVR placement (to be continued) node 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 19 0 0 0 0 0 0 0 0 -2.5407 + 0.57805i 5.084 - 1.1573i -2.5407 + 0.57805i 0 0 0 0 0 0 0 20 0 0 0 0 0 0 0 0 0 -2.5407 + 0.57805i 5.3381 - 1.2151i -2.7948 + 0.63585i 0 0 0 0 0 0 21 0 0 0 0 0 0 0 0 0 -2.7948 + 0.63585i 4.8571 - 0.99086i -1.967 + 0.33784i 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 -1.967 + 0.33784i 3.9408 - 0.67765i -2.0597 + 0.35376i 0 0 0 0 0 23 0 0 0 0 0 0 0 0 0 0 -2.0597 + 0.35376i 4.122 - 0.70877i -2.0597 + 0.35376i 0 0 0 0 0 24 0 0 0 0 0 0 0 0 0 0 0 -2.0597 + 0.35376i 3.7787 - 0.64981i -1.7164 + 0.2948i 0 0 0 0 25 0 0 0 0 0 0 0 0 0 0 0 -1.7164 + 0.2948i 1.7254 - 0.29915i 0 0 0 0 26 0 0 -2.5746 + 0.4422i 0 0 0 0 0 0 0 0 0 4.4496 - 0.76505i -1.8724 + 0.3216i 0 0 0 27 0 0 0 0 0 0 0 0 0 0 0 0 -1.8724 + 0.3216i 4.448 - 0.76428i -2.5746 + 0.4422i 0 0 0 D-8 APPENDIX D Bus Admittance Matrixes of Study System (Continued) Table D.2 Bus admittance matrix of the study system under the optimal TVR placement node 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 27 0 0 0 0 0 0 0 0 0 0 0 0 -1.8724 + 0.3216i 4.448 - 0.76428i -2.5746 + 0.4422i 0 0 0 28 0 0 0 0 0 0 0 0 0 0 0 0 0 -2.5746 + 0.4422i 2.5756 - 0.44268i 0 0 0 29 0 0 0 -2.5746 + 0.4422i 0 0 0 0 0 0 0 0 0 0 5.1502 - 0.88488i -2.5746 + 0.4422i 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2.5746 + 0.4422i 4.292 - 0.73748i -1.7164 + 0.2948i 0 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1.7164 + 0.2948i 3.4354 - 0.59085i -1.6392 + 0.28154i 0 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1.6392 + 0.28154i 4.1426 - 0.71232i -2.5746 + 0.4422i 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2.5746 + 0.4422i 5.1518 - 0.88565i -2.5746 + 0.4422i 34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2.5746 + 0.4422i 2.5772 - 0.44345i D-9 Reference REFERENCES [1] Robert D Hof “The ‘Dirty Power’ Clogging Industry’s Pipeline”, April 8, 1991, Business Week [2] “Electromagnetic compatibility (EMC) - Part 2: Environment - Section 1: Description of the environment - Electromagnetic environment for low-frequency conducted disturbances and signalling in public power supply systems”, IEC/TR3 61000-2-1, 1990-05 [3] “Electromagnetic compatibility (EMC) - Part 2: Environment - Section 5: Classification of electromagnetic environments”, IEC/TR2 61000-2-5, 1995-09 [4] “IEEE Recommended Practice for Monitoring Electric Power Quality”, IEEE Std 1159-1995, Approved June 14, 1995 [5] “IEEE Recommended Practice for the Design of Reliable Industrial and Commercial Power Systems”, IEEE Std 493-1997, Approved 16 December 1997 [6] Bollen, Math H J “Understanding Power System Problems: voltage sags and interruptions”, 2000, the Institute of Electrical and Electronic Engineering, Inc., New York, NY 10016-5997 [7] Roger C Dugan, Mark F McGranaghan, H Wayne Beaty “Electrical Power Systems Quality”, New York, McGraw Hill, c1996, p39 [8] Salzer, J.M “Worldwide Review of Power Disturbances”, IEEE Aerospace and Electronics Systems Magazine, Volume: 3, Issue: 4, April 1988 Ref-1 Reference [9] Shih-An Yin, Chan-Nan Lu, Edwin Liu, Yu-Chang Huang, Chinug-Yi Huang “A Survey on High Tech Industry Power Quality Requirements”, Transmission and Distribution Conference and Exposition, 2001 IEEE/PES, Volume: 1, 2001, Page(s): 548 –553 [10] “IEEE Recommended Practice for Evaluating Electric Power System Compatibility With Electronic Process Equipment”, IEEE Std 1346-1998, Approved May 1998 [11] Sannino, A.; Miller, M.G.; Bollen, M.H.J “Overview of voltage sag mitigation”, Power Engineering Society Winter Meeting, 2000, IEEE, Volume: 4, 2000, Page(s): 2872 -2878 vol.4 [12] Heine, P.; Lehtonen, A.; Lakervi, E “Voltage sag analysis taken into account in distribution network design”, Power Tech Proceedings, 2001 IEEE Porto, Volume: vol.3, 2001, Page(s): pp vol.3 [13] Degeneff, R.C.; Barss, R.; Carnovale, D.; Raedy, S.; “Reducing the effect of sags and momentary interruptions: a total owning cost prospective”, Harmonics and Quality of Power, 2000 Proceedings Ninth International Conference on, Volume: 2, 2000, Page(s): 397 -403 vol.2 [14] Tosato, F.; Quaia, S “Reducing voltage sags through fault current limitation”, Power Delivery, IEEE Transactions on, Volume: 16, Issue: 1, Jan 2001, Page(s): 12-17 [15] Chang, C.S.; Loh, P.C “Designs synthesis of resonant fault current limiter for voltage sag mitigation and current limitation”, Power Engineering Society Winter Meeting, 2000 IEEE, Volume: 4, 2000, Page(s): 2482 -2487 vol.4 [16] Tenorio, A.R.M.; Daconti, J.R “Voltage sag mitigation by means of thyristor controlled series capacitors”, Harmonics and Quality of Power Proceedings, 1998 Proceedings 8th International Conference On, Volume: 1, 1998, Page(s): 572-576 vol.1 [17] Woodley, N.H.; Morgan, L.; Sundaram, A.; “Experience with an inverter-based dynamic voltage restorer”, Power Delivery, IEEE Transactions on, Volume: 14 Issue: 3, Jul 1999, Page(s): 1181 –1186 [18] Sensarma, P.S.; Padiyar, K.R.; Ramanarayanan, V.; “Analysis and performance evaluation of a distribution STATCOM for compensating voltage fluctuations”, Power Delivery, IEEE Transactions on, Volume: 16 Issue: 2, Apr 2001, Page(s): 259 -264 [19] Changjiang Zhan; Ramachandaramurthy, V.K.; Arulampalam, A.; Fitzer, C.; Kromlidis, S.; Bames, M.; Jenkins, N.; “Dynamic voltage restorer based on voltageRef-2 Reference space-vector PWM control”, Industry Applications, IEEE Transactions on, Volume: 37 Issue: 6, Nov/Dec 2001 Page(s): 1855 -1863 [20] Lima, M.C.; Tenorio, A.R.M.; “Design modifications and system studies to relocate a static VAr compensator in a power system with power quality problems”, Harmonics and Quality of Power, 2000 Proceedings Ninth International Conference on, Volume: 2, 2000 Page(s): 652 -657 vol.2 [21] Chang, C.S.; Yang, S.W “Optimal multiobjective planning of dynamic series compensation devices for power quality improvement”, Generation, Transmission and Distribution, IEE Proceedings-, Volume: 148, Issue: 4, July 2001 [22] Fitzer, C.P.; Lim, Y.S.; Zhan, C.; Ramachandaramurthy, V.K.; Arulampalam, A.; Barnes, M.; Strbac, G.; Jenkins, N.; “Mitigation of voltage sags embracing a prediction technique and the use of a dynamic voltage restorer”, Electricity Distribution, 2001 Part 1: Contributions CIRED 16th International Conference and Exhibition on (IEE Conf Publ No 482) , Volume: , 2001, Page(s): pp vol.2 [23] Kazuya Omata, et al, “Development and Application of New Voltage Regulator with Thyristor Based Tap Changer for Improving Power Quality”, International Conference on Electrical Engineering 2001, (ICEE2001), No 0238, Volume 2, p1076-1079, Xi’an, China, 2001 [24] Heine, P et al; “A method for estimating the frequency and cost of voltage sags”, Power Systems, IEEE Transactions on, Volume: 17 Issue: 2, May 2002, Page(s): 290 – 296 [25] Gunther, E.W.; Mebta, H “A survey of distribution system power quality-preliminary results”, Power Delivery, IEEE Transactions on, Volume: 10, Issue: 1, Jan 1995, Page(s): 322 -329 [26] Koval, D.O.; Bocancea, R.A.; Kai Yao; Hughes, M.B “Canadian national power quality survey: frequency and duration of voltage sags and surges at industrial sites”, Industry Applications, IEEE Transactions on, Volume: 34, Issue: 5, Sept.-Oct., 1998, Page(s): 904 -910 [27] Tzong-Yih Guo, J.T Lin, C.J.Liao “Power Quality Monitoring Systems Implementation and Monitoring Results Study at Science-Based Industrial Park of Taiwan Power System”, Proceedings, International Power Quality Conference, IPQC2002, Volume 1, 2002, Page(s): 193-203 [28] Qader, M.R.; Bollen, M.H.J.; Allan, R.N “Stochastic prediction of voltage sags in a large transmission system”, Industry Applications, IEEE Transactions on, Volume: 35, Issue: 1, Jan.-Feb 1999, Page(s): 152 -162 Ref-3 Reference [29] Alves, M.F.; Fonseca, V.R.C “Voltage sag stochastic estimate”, Industry Applications Conference, 2001, Thirty-Sixth IAS Annual Meeting, Conference Record of the 2001 IEEE, Volume: 3, 2001, Page(s): 1665 -1669 vol.3 [30] Barry W Kennedy “Power quality primer”, Chapter 8, “Power Quality Economics”, New York, McGraw Hill, 2000 [31] Kai Hwang, “Advanced Computer Architecture: Programmability”, McGraw-Hill, Inc., 1993 [32] Toune, S.; Fudo, H.; Genji, T.; Fukuyama, Y.; Nakanishi, Y “Comparative study of modern heuristic algorithms to service restoration in distribution systems”, Power Delivery, IEEE Transactions on, Volume: 17, Issue: 1, Jan 2002 Page(s): 173 -181 [33] Colin R Reeves [editor], “Modern heuristic techniques for combinatorial problems”, Blackwell Scientific Publications, 1993 [34] Edited by V.J Rayward-Smith, et al “Modern Heuristic search methods”, J Wiley and Sons; UNICOM, c1996 [35] Gerbex, S.; Cherkaoui, R.; Germond, A.J “Optimal location of multi-type FACTS devices in a power system by means of genetic algorithms”, Power Systems, IEEE Transactions on, Volume: 16, Issue: 3, Aug 2001, Page(s): 537 –544 [36] Chang, C.S.; Lem Poh Lern “Application of tabu search strategy in solving nondifferentiable savings function for the calculation of optimum savings due to shunt capacitor installation in a radial distribution system”, Power Engineering Society Winter Meeting, 2000 IEEE, Volume: 4, 2000, Page(s): 2323 -2328 vol.4 [37] Yann-Chang Huang; Hong-Tzer Yang; Ching-Lien Huang, “Solving the capacitor placement problem in a radial distribution system using Tabu Search approach”, Power Systems, IEEE Transactions on, Volume: 11, Issue: 4, Nov 1996, Page(s): 1868 –1873 [38] Chang, C.S.; Huang, J.S “Optimal multiobjective SVC planning for voltage stability enhancement”, Generation, Transmission and Distribution, IEE Proceedings-, Volume: 145 Issue: 2, March 1998 [39] Leung, H.C.; Chung, T.S “Optimal placement of FACTS controller in power system by a genetic-based algorithm”, Power Electronics and Drive Systems, 1999, PEDS ' 99, Proceedings of the IEEE 1999 International Conference on, Volume: 2, 1999, Page(s): 833 -836 vol.2 Parallelism, Scalability, Ref-4 Reference [40] Miu, K.N.; Chiang, H.-D.; Darling, G “Capacitor placement, replacement and control in large-scale distribution systems by a GA-based two-stage algorithm”, Power Systems, IEEE Transactions on, Volume: 12 Issue: 3, Aug 1997 [41] Yong-Hua Song; Malcolm R Irving “Optimisation techniques for electrical power systems Part Heuristic optimisation methods”, Power Engineering Journal, June 2001, Page(s): 151-160 [42] Toh, C.W.; Lock, C.S.; Chen, S.; Choi, S.S “A voltage quality improvement solution using step dynamic voltage regulator”, Power System Technology, 2000 Proceedings, PowerCon 2000, International Conference on, Volume: 2, 2000, Page(s): 983 -988 vol.2 [43] Math H.J Bollen “IEEE Tutorial on voltage sag analysis”, New York, IEEE Press, October 1999 [44] He Yangzan, et al “Power system analysis”, Press of Huazhong Technology University, Wuchang, 1996 [45] Chis, M.; Salama, M.M.A.; Jayaram, S “Capacitor placement in distribution systems using heuristic search strategies”, Generation, Transmission and Distribution, IEE Proceedings-, Volume: 144 Issue: 3, May 1997, Page(s): 225 –230 [46] John J Grainger, William D Stevenson, Jr “Power system analysis”, New York: McGraw-Hill, c1994, pages 284-286 [47] David Ginat “Genetic Algorithm: a function optimizer”, College Park, MD: University of Maryland, 1988 [48] Zhang Wenxiu, Leung Yee “Mathematical Foundation of Genetic Algorithms”, Xi’an, Xi’an Jiaotong University Press, 2000 [49] Becker, C.; Braun, et al; “Proposed chapter for predicting voltage sags (dips) in revision to IEEE Std 493, the Gold Book”, Industry Applications, IEEE Transactions on, Volume: 30 Issue: 3, May/Jun 1994, Page(s): 805–821 [50] Conrad, L.; Little, K.; Grigg, C.; “Predicting and preventing problems associated with remote fault-clearing voltage dips”, Industry Applications, IEEE Transactions on, Volume: 27 Issue: 1, Jan/Feb 1991, Page(s): 167 –172 Ref-5 Reference [51] Wagner, V.E.; Andreshak, A.A.; Staniak, J.P.; “Power quality and factory automation”, Industry Applications, IEEE Transactions on, Volume: 26 Issue: 4, Jul/Aug 1990, Page(s): 620 –626 [52] Alan F Karr “Probability”, New York: Springer-Verlag, c1993 [53] Heine, P.; Pohjanheimo, P.; Lehtonen, M.; Lakervi, E.; “Estimating the annual frequency and cost of voltage sags for customers of five Finnish distribution companies”, Electricity Distribution, 2001 Part 1: Contributions CIRED 16th International Conference and Exhibition on (IEE Conf Publ No 482), Volume: 2, 2001 Page(s): pp vol.2 [54] Ned Mohan, Tore M Undeland, William P Robbins, “Power electronics: converters, applications, and design”, New York: Wiley, c1995, 2nd ed, page 228 Ref-6 [...]... Mitigation of Sags by Optimal Placement of Compensation Devices CHAPTER 2 MITIGATION OF SAGS BY OPTIMAL PLACEMENT OF COMPENSATION DEVICES The methodology of optimal placement of compensation devices for sag mitigation is presented in this chapter Normally, three processes are needed to find the optimum mitigation scheme: selecting the types of compensation devices, evaluating possible candidate solutions... Mitigation of Voltage Sag by Optimal Placement of Series Compensation Devices Based on Stochastic Assessment” has been approved for publication in the IEEE Transactions on Power Systems xii ABSTRACT This thesis deals with the mitigation of voltage sag, which is the most common powerquality problem experienced in power systems This thesis presents a method of optimal placement of two series compensation devices, ... mitigation 2-2 Chapter 2 2.2 Mitigation of Sags by Optimal Placement of Compensation Devices SELECTING SAG COMPENSATION DEVICES Sag mitigation devices should be selected to best fit the supply system configuration, consumer susceptibility and characteristics of voltage sag In this research, the two series compensation device DVR and TVR are chosen as the candidates to be optimally placed in the supply system,... described by three elements: frequency (how often sags occur), distribution of magnitude and duration The most straightforward way of presenting the stochastic characteristics of sag events is through a scatter diagram by plotting each sag characterized by its magnitude and duration Figure 2.3 shows such an example 2-5 Chapter 2 Figure 2.3 Mitigation of Sags by Optimal Placement of Compensation Devices. .. considered for providing coarse compensation for non-sensitive loads A detailed description of this device is presented in the next chapter 2-3 Chapter 2 Mitigation of Sags by Optimal Placement of Compensation Devices In this thesis, the algorithm aims at the optimal placement of DVRs and TVRs across the supply system in the distributed mitigation configuration Sensitive customers often have high cost/disruption... amount of computing resources may be required when a group of dispersed consumers are taken into consideration 1.2 OBJECTIVE OF THIS THESIS The objective of the present thesis is to develop algorithms for optimal placement of compensation devices for sag mitigation In order to achieve this objective, mitigation of sag using Thyristor Voltage Regulator (TVR) will be investigated The TVR is a series compensation. .. Adjustable Speed Drive (ASD) has been shown in Figure 2.4 2-6 Chapter 2 Mitigation of Sags by Optimal Placement of Compensation Devices Figure 2.4 2.3.3 Example of the range of ASD sag tolerances [10] Step 3: Evaluation and Optimization As mentioned above, a sag mitigation scheme consists of a placement of compensation devices Normally, such a mitigation scheme is evaluated according to an economical... (2) To give an algorithm for the optimum placement scheme of TVRs in distribution systems under the heavy load conditions using GA optimization (3) To propose the algorithm for optimal mix and placement of DVRs and TVRs according to the stochastic assessment model using a more extensive version of GA search The validity of the proposed method by case studies is shown using various sets of sag data and... which consists of more than one type of sag compensation devices The impact of these compensation devices upon the whole system, which has not been considered sufficiently in previous studies [18] [19], is also in need of careful study To summarize, the aims of this study are: (1) To describe and demonstrate the voltage regulation ability of TVRs through modeling study using SimPowerSystems of MATLAB (2)... the effect of noise as switching on error, hysteresis control has been proposed and demonstrated The late part of this project is devoted to the optimal placement of series compensation devices for sag mitigation in two case studies, which are performed on a 34-node supply system In the simple case where sags are caused by predictable events such as sudden load changes, the optimal placement of TVRs is .. .MITIGATING VOLTAGE SAGS BY OPTIMAL PLACEMENT OF SERIES COMPENSATION DEVICES USING GENETIC ALGORITHM YU ZHEMIN A THESIS SUBMITTED FOR THE DEGREE OF MASTER OF ENGINEERING DEPARTMENT OF ELECTRICAL... summary of the contributions of this thesis and suggestions for future work are presented 1-13 Chapter Mitigation of Sags by Optimal Placement of Compensation Devices CHAPTER MITIGATION OF SAGS BY OPTIMAL. .. description of this device is presented in the next chapter 2-3 Chapter Mitigation of Sags by Optimal Placement of Compensation Devices In this thesis, the algorithm aims at the optimal placement of DVRs