Design of self tuning frequency synthesizer

DESIGN OF A SELF-TUNING FREQUENCY SYNTHESIZER WEE TUE FATT DAVID (B.ENG. (FIRST CLASS), UNSW) A THESIS SUBMITTED FOR THE DEGREE OF MASTER OF ENGINEERING DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2005 Name: Wee Tue Fatt David Degree: Master of Engineering Department: Electrical and Computer Engineering Thesis Title: Design of a Self-Tuning Frequency Synthesizer Summary This thesis describes the design and implementation of a self-tuning frequency synthesizer. The aim is to design a frequency synthesizer that is able to self-tune when there is a process, temperature and voltage variation. This allows the designers to design a low gain frequency synthesizer system, which produces a low phase noise without process variation constraint. The simulation results and the experimental results are presented in this report. The frequency synthesizer is fabricated in a 0.25 µm six level metal Silicon Germanium (SiGe) process. With a supply voltage of 2.5 V, the test results show that the frequency synthesizer is able to calibrate itself even though there is a frequency drift of around 250 MHz in the Voltage Controlled Oscillator (VCO). The measured phase noise of the frequency synthesizer is -81.50 dBc at 10 kHz offset. Keywords: Frequency Synthesizer, Self-Tuning, Transceiver, LC Oscillator, Phase Lock Loop (PLL). i Acknowledgements I would like to use this opportunity to thank my supervisor, Professor Xu Yong Ping for his guidance and advises during the period of my research work. In addition, I would also like to thank him for accepting my proposed idea for this thesis. Next, I would like to express my appreciation to my manager, Mr. Chee Piew Yoong and colleagues in the Institute for Infocomm Research (I2R) for their valuable advices and technical discussion during the period of the project. Finally yet importantly, I would like to thank my family members for their encouragement and support during this period. ii Table of Contents List of Figures ................................................................................................................. v List of Tables ...............................................................................................................viii 1. 2. 3. Introduction............................................................................................................. 1 1.1. Background and Motivation ........................................................................... 1 1.2. Aims and Scope .............................................................................................. 4 1.3. Organization of Thesis .................................................................................... 6 Frequency Synthesizer ............................................................................................ 7 2.1. Basic Concept of the Frequency synthesizer .................................................. 7 2.2. Phase Detector Characteristics........................................................................ 8 2.3. VCO Characteristics ..................................................................................... 10 2.4. Linear Model of the Frequency Synthesizer................................................. 12 2.4.1. Dynamic Response of Frequency Synthesizer...................................... 12 2.4.2. Static Phase Error.................................................................................. 16 2.5. Noise Analysis of the Frequency Synthesizer System.................................. 18 2.6. Relationships of Design Parameters ............................................................. 21 Design of Frequency Synthesizer ......................................................................... 23 3.1. System Architecture...................................................................................... 23 3.2. Self tuning Circuit Design ............................................................................ 27 3.2.1. Frequency Synthesizer Tuning Range .................................................. 27 3.2.2. Self-Tuning Concept ............................................................................. 31 3.3. Simulation Result.......................................................................................... 34 iii 4. 5. Circuit Level Design ............................................................................................. 39 4.1. Phase Frequency Detector............................................................................. 39 4.2. Charge Pump................................................................................................. 41 4.3. Voltage Controlled Oscillator ....................................................................... 45 4.4. Self-Tuning Circuit ....................................................................................... 58 4.5. Divider .......................................................................................................... 59 4.6. System Simulation Results ........................................................................... 65 4.7. Layout Design and Considerations ............................................................... 68 4.8. Floor Plan of the Frequency Synthesizer ...................................................... 70 Measurement Result.............................................................................................. 71 5.1. Measurement Setup....................................................................................... 71 5.2. Measurement Result...................................................................................... 72 5.2.1. VCO Tuning Voltage Characteristic..................................................... 73 5.2.2. Frequency Synthesizer Phase Noise Performance ................................ 77 5.2.3. Measured Result of Self-Tuning Circuit............................................... 81 5.3. 6. Discussion of Result ..................................................................................... 83 Conclusions........................................................................................................... 84 6.1. Conclusion .................................................................................................... 84 6.2. Future Work .................................................................................................. 85 References..................................................................................................................... 87 Appendix A................................................................................................................... 91 Appendix B ................................................................................................................... 93 iv List of Figures Figure 1-1 Frequency Synthesizer Design Factors ......................................................... 3 Figure 2-1 Basic Frequency synthesizer ......................................................................... 8 Figure 2-2 Characteristic of an ideal phase detector....................................................... 9 Figure 2-3 Model of Phase Detector............................................................................... 9 Figure 2-4 Characteristics of an ideal VCO.................................................................. 10 Figure 2-5 Model of VCO............................................................................................. 11 Figure 2-6 Linear Model of Frequency Synthesizer ..................................................... 12 Figure 2-7 Open loop and Closed loop response of Frequency Synthesizer ................ 14 Figure 2-8 Single-pole RC loop filter ........................................................................... 14 Figure 2-9 Frequency Response of 2nd order Frequency Synthesizer (ζ = 0.707) ....... 16 Figure 2-10 Linear model of Frequency Synthesizer with added noise sources .......... 19 Figure 3-1 Local Oscillator System Diagram ............................................................... 23 Figure 3-2 Typical Direct Up and Down Conversion Topology in Transceiver .......... 24 Figure 3-3 Frequency of Operation for Mode 1 Device [17]........................................ 25 Figure 3-4 System Architecture of Frequency Synthesizer .......................................... 26 Figure 3-5 Typical Tuning Range Curve of Oscillator................................................. 29 Figure 3-6 Tuning Voltage of Proposed System........................................................... 32 Figure 3-7 Flow Chart of Tuning Circuit...................................................................... 33 Figure 3-8 Block Diagram of Tuning Circuit ............................................................... 33 Figure 3-9 Third Order Low Pass Filter ....................................................................... 34 v Figure 3-10 Gain and Phase Margin of Frequency Synthesizer ................................... 37 Figure 3-11 System Phase Noise Simulation................................................................ 38 Figure 4-1 Schematic Diagram of Phase Frequency Detector...................................... 40 Figure 4-2 PFD State Diagram ..................................................................................... 40 Figure 4-3 PFD Simulation Result................................................................................ 41 Figure 4-4 Schematic of Charge Pump ......................................................................... 43 Figure 4-5 Charge Pump Current Mismatch Simulation Result................................... 44 Figure 4-6 Expanded View of the Current Mismatch Simulation Result..................... 44 Figure 4-7 Schematic of LC Oscillator ......................................................................... 47 Figure 4-8 Oscillator Small Signal Equivalent Circuit ................................................. 48 Figure 4-9 VCO Tuning Range (Typical Process Corner) ........................................... 54 Figure 4-10 Post Layout VCO Tuning Range (Typical Process Corner) ..................... 56 Figure 4-11 VCO Phase Noise...................................................................................... 57 Figure 4-12 Schematic of Self-tuning Controller ......................................................... 59 Figure 4-13 Divider Block Diagram ............................................................................. 60 Figure 4-14 ECL D-Flip Flop ....................................................................................... 61 Figure 4-15 Master/Slave ECL D Flip Flop ................................................................. 61 Figure 4-16 Divider by Three Counter ......................................................................... 63 Figure 4-17 Simulation result of Divider Output.......................................................... 64 Figure 4-18 Output of Divider (44MHz) ...................................................................... 65 Figure 4-19 Control Voltage of Frequency Synthesizer (Based on VCO and LPF) .... 67 Figure 4-20 Control Voltage of Frequency Synthesizer ............................................... 68 Figure 4-21 Proposed Layout Plan ............................................................................... 69 vi Figure 4-22 Die Micrograph ......................................................................................... 70 Figure 5-1 Test board Setup.......................................................................................... 72 Figure 5-2 Measured VCO Tuning Characteristics ...................................................... 75 Figure 5-3 VCO Tuning Voltage Characteristics ......................................................... 77 Figure 5-4 Lock Detect Signal ...................................................................................... 78 Figure 5-5 Control voltage, VCNTRL Signal Response .............................................. 79 Figure 5-6 Measured Frequency Synthesizer Output Spectrum at 4.224 GHz............. 79 Figure 5-7 Self-Tuning Transient Response ................................................................. 82 Figure Appendix B-1 VCO Tuning Range (Slow Process Corner) .............................. 93 Figure Appendix B-2 VCO Tuning Range (Fast Process Corner) ............................... 93 Figure Appendix B-3 Post Layout VCO Tuning Range (Slow Process Corner).......... 94 Figure Appendix B-4 Post Layout VCO Tuning Range (Fast Process Corner) ........... 94 Figure Appendix B-5 Spectrum Analyzer’s Phase Noise Configuration ..................... 95 Figure Appendix B-6 Measured Frequency Synthesizer Phase Noise @ 10 kHz ........ 95 Figure Appendix B-7 Measured Frequency Synthesizer Phase Noise @ 100 kHz ...... 96 Figure Appendix B-8 Measured Frequency Synthesizer Phase Noise @ 1 MHz ........ 96 Figure Appendix B-9 Measured Frequency Synthesizer Phase Noise @ 10 MHz ...... 97 vii List of Tables Table 2-1 Cause and Effect of Increased KPD ............................................................... 22 Table 3-1 Technical Specification of Frequency Synthesizer ...................................... 25 Table 3-2 Different Standard Absolute and Relative Tuning Range ............................ 28 Table 3-3 Frequency Spread due to Process variation.................................................. 30 Table 3-4 System Phase Noise for different KVCO Setting............................................ 35 Table 3-5 Filter Parameter for Different KVCO Setting ................................................. 36 Table 3-6 Frequency Synthesizer Parameters............................................................... 36 Table 3-7 System Phase Noise Result .......................................................................... 37 Table 4-1 Current Mismatch Data ................................................................................ 45 Table 4-2 Effect of VCO Frequency on Process Skew Parameter ............................... 49 Table 4-3 Overlap Frequency (Schematic Simulation Result) ..................................... 50 Table 4-4 KVCO Gain for Different Setting (Schematic Simulation Result) ................. 51 Table 4-5 Overlap Frequency (Post Layout Simulation Result)................................... 52 Table 4-6 KVCO Gain for Different Setting (Post Layout Simulation Result) .............. 52 Table 4-7 VCO Schematic Simulation Result .............................................................. 53 Table 4-8 VCO Post Layout Simulation Result............................................................ 55 Table 4-9 VCO Phase Noise ......................................................................................... 57 Table 4-10 State Table of a Divider-by-Three counter................................................. 62 Table 4-11 Flip-Flop Input Table ................................................................................. 62 Table 5-1 VCO Tuning Voltage Measurement Result ................................................. 73 viii Table 5-2 Measurement Overlap Frequency................................................................. 74 Table 5-3 KVCO Gain for Different Setting (Measurement Result)............................ 74 Table 5-4 Summarized Result between Simulation and Measurement ........................ 76 Table 5-5 Overlap Frequency Comparison................................................................... 76 Table 5-6 KVCO Gain Comparison ................................................................................ 76 Table 5-7 Measured Frequency Synthesizer Noise Performance ................................. 80 Table 5-8 Phase Noise Comparison.............................................................................. 81 Table 5-9 Measured Crystal Oscillator Phase Noise Performance ............................... 81 Table 5-10 Frequency Synthesizer Desired Frequency Band of operation .................. 82 ix CHAPTER 1: Introduction 1. Introduction 1.1. Background and Motivation The Frequency synthesizer is one of the most important building blocks in integrated communication systems as it is used to provide an accurate frequency source for up/down conversion, modulation and demodulation in any transceiver system. It can also be used to provide clock conversion, clock generation and timing references in integrated systems. Frequency synthesizer design remains one of the most challenging designs in Radio Frequency (RF) systems because it must meet very stringent requirements [1]. In recent years, there are growing requirements to integrate the entire transceiver systems on a single silicon chip [2]-[4]. This is due to the advancement of Complementary Metal Oxide Semiconductor (CMOS) semiconductor technology in the past decade. This advancement in sub micron technology allows manufacturers to integrate the entire transceiver systems on a single silicon chip, which leads to a rapid growth in the communication. The higher scales of integration have created new constraints and tighten the design requirements for circuit designers, who are designing frequency synthesizer. Figure 1-1 shows the factors that designers have to take into consideration when designing frequency synthesizers. Although these factors listed in Figure 1-1 influence the design, circuit designer do not have control in factors like technology, communication 1 CHAPTER 1: Introduction specifications and supply voltage. The choice of technology uses greatly depends on factors like cost of the product, performance objectives, production capacity, time to market and other commercial strategies rather than on the circuit design. On the other hand, standard for voice and data applications like Global System for Mobile Communication (GSM), Digital European Cordless Telephone (DECT), Personal Communication Services (PCS), 802.11 Wireless Local Area Network (WLAN), Bluetooth and so on will predefined the communication specification and supply voltage. From the standard, the system engineer will specifies the design specification like frequency, tuning range, phase noise, and so on for the frequency synthesizer. Although these three factors are not within the control of the designers, they have great influence on the design process. This is especially so for technology factor, as supply voltage is closely inter-related with advancement of technology. With each scaling of technology node1, the power supply of the system has to be scaled down as well [5]. The scaling down of the supply voltage would therefore reduce the dynamic range of voltage that can be used in the design. This will increases the complexity of the frequency synthesizer design in low voltage domain. In addition, circuit designers have to consider additional parameters like supply voltage variation, temperature and process variation. Circuit designers have to ensure that the frequency synthesizer is able to work according to the specifications that are defined by the system engineer. In order to ensure that the frequency synthesizer is 1 Technology node is use to describe generations of semiconductor processing technology by international Technology Roadmap for Semiconductors (ITRS) 2 CHAPTER 1: Introduction able to meet the specification, circuit designers would therefore have to modify or simulate a circuit several times before a satisfactory result can be achieved. This process is time consuming. This is especially true for process variation, which depends on the foundry process. The foundry will normally provide the limits of the process at which the wafer will be rejected. In another word, these limits do not provide much insight in circuit design as they simply demonstrate a lack of robustness in the process [6]. Even though, there is many efforts being spend in the foundry to improve the yield of the process. This process variation issue will always haunt circuit designer. Thus, designers need to run many simulations to make sure every circuit are working within the limitation of the process and this took a huge amount of simulation time. Sometime, the circuit fails to meet the specification due to process variation. Figure 1-1 Frequency Synthesizer Design Factors A major challenge for circuit designers is to find ways to design the frequency synthesizer with tightening constraints and ever-increasing stringent requirement for 3 CHAPTER 1: Introduction communication system. Since circuit designers do not have control on the supply voltage, specification of communication system and technology, designers have to focus on supply voltage variation, temperature and process variation factors and find ways in the circuit design to minimize the effect of these three factors in fulfilling the requirement of the specification. One good example is the gain of the oscillator uses in the design of the frequency synthesizer as it has great impact on the noise performance of the frequency synthesizer. Furthermore, with reducing dynamic range, gain of the Voltage Controlled Oscillator (VCO) will increase due to the fact the VCO must cover the same range of the frequency in the same communication system. This would increases the phase noise of the frequency synthesizer, which will have a major impact on the specification of the communication system, as phase noise is one of the most important factors in defining the specification of the frequency synthesizer. The challenge for circuit designers is to take care of the various factors and come out with an innovative design that can meet specification of the communication system. 1.2. Aims and Scope Since noise from charge pump and loop amplifier is amplified by the VCO gain around the loop bandwidth. VCO gain is usually large because of limited control voltage range and large frequency range required by the application. In addition, designer need to design the VCO gain to be larger than the intend application due to the fact of constraint posed by voltage, temperature and process variation. Normally, the gain of 4 CHAPTER 1: Introduction the VCO will normally impose the limit of the noise performance of the frequency synthesizer. This research focuses on the design technique to reduce phase noise and improve the system noise performance of the frequency synthesizer. The design technique reduces the effect of the VCO dependence on factors like process variation, temperature and supply voltage variation. This would allow a designer to concentrate on the design of the frequency synthesizer based on the communication specification instead The effect of reduced supply voltage, process, temperature and voltage variation on the gain of the VCO on the design of the frequency synthesizer are investigated in this thesis and a solution to reduce the dependence on these factors is presented as well. To verify the effectiveness of the design technique, a self-tuning frequency synthesizer was designed and fabricated in a 0.25 µm IBM SiGe process [7]. Although the process allows the use of bipolar devices, only CMOS devices are used to design the entire frequency synthesizer, as this is the project requirement. The frequency synthesizer is able to self-tune the output frequency of the VCO to the desired frequency when the system starts up. This allows the designer to design a low gain VCO, which results in better noise performance. The major achievement of this work is that designer does not have to over design the gain of the VCO to cover for reduced tuning voltage, process variation and operation condition but just concentrate on the specification of the VCO based on communication specification. Thus, the phase noise will be better compared to a system that has to consider these factors. In other words, the phase noise will be lower compared to a system that has to consider these factors. A self-tuning block has 5 CHAPTER 1: Introduction been implemented to the traditional Frequency Synthesizer to reduce the VCO gain effect to improve the ease of designing VCO based on communication specification rather than include the effect of process, voltage and temperature variation in the design of the VCO. 1.3. Organization of Thesis This thesis is organized into six chapters. In this chapter, the background and aim of this thesis is presented. In Chapter 2, the basic concept and the characteristics of the frequency synthesizer will be discussed. In Chapter 3, the idea and design of the frequency synthesizer for this thesis will be presented. In Chapter 4, the circuit level design of the major blocks in the frequency synthesizer will be presented. There will be a discussion on the simulation result and problems faced during the implementation of the frequency synthesizer. In Chapter 5, the test results of the frequency synthesizer are presented. Finally, the conclusion of the thesis will be presented in Chapter 6. 6 CHAPTER 2: Frequency Synthesizer 2. Frequency Synthesizer Modern communication systems use frequency synthesizers for quite a number of purposes, namely to recover the clock from digital data signals, synthesize frequencies for receiver tuning, recover the carrier signal from satellite transmission signals, and perform frequency and phase modulation. In this chapter, an overview and analysis of the frequency synthesizer will be discussed. In addition, the basic concept of the frequency synthesizer will be presented and equations for the various building blocks will be derived. After that, the dynamic response of the frequency synthesizer is introduced and the parameters that affect the design of frequency synthesizer are presented. Finally, the noise analysis of the frequency synthesizer is being studied. 2.1. Basic Concept of the Frequency synthesizer PLL based frequency synthesizer has a frequency divider in the feedback loop. The basic frequency synthesizer system is shown in Figure 2-1. It consists of a phase detector, low pass filter, voltage controller oscillator and a divider [8]. A frequency synthesizer is a feedback system with its main purpose to ensure the output signal, θout, tracks the input signal, θi. The input and output signal of the system can be in frequency or phase. The system is considered locked when the output signal is equal to the input signal over a period of time. 7 CHAPTER 2: Frequency Synthesizer Figure 2-1 Basic Frequency synthesizer The purpose of the phase detector is to compare the phase of the divided output signal, θo, with the phase of the input signal, θi. The phase detector will develop a voltage proportional to the phase difference. This voltage, VD is applied to a low pass filter, which will determine the bandwidth of the system as well as to reduce the high frequencies phase error. The voltage at the low pass filter, VLPF is applied to the voltage-controlled oscillator to adjust the oscillator frequency. Through the feedback system, the system will ensure both the phase and the frequency of the oscillator are locked to the phase and frequency of the input signal. 2.2. Phase Detector Characteristics An ideal phase detector produces an output voltage proportional to the difference between the phases of two input signals, which are periodic [9]. The typical phase detector characteristic is shown in Figure 2-2. It is assumed that when ∆θ is equal to zero, the phase of the output signal, θo, is equal to the phase of the input signal, θi. 8 CHAPTER 2: Frequency Synthesizer VOUT VOUT Figure 2-2 Characteristic of an ideal phase detector With the above assumption, the phase error, ∆θ, (specified in radians) is defined as ∆θ = θ i − θ o (2-1) The gain of the phase detector, KPD (specified in Volts/radians) is expressed as K PD ≡ d VOUT / d∆θ (2-2) In the linear region, the phase detector voltage, VOUT (specified in Volts) is modeled by VOUT = K PD ∆θ (2-3) that is represented by the model representation shown in Figure 2-3. VOUT Figure 2-3 Model of Phase Detector 9 CHAPTER 2: Frequency Synthesizer 2.3. VCO Characteristics An ideal VCO will generate a periodic output signal whose frequency is a linear function of a control voltage, VC. The frequency of the VCO will increase or decrease depending on the control voltage, VC. A typical characteristic of a VCO is shown in Figure 2-4. ωo ω fr VC Figure 2-4 Characteristics of an ideal VCO It can be noticed from the VCO characteristics that the VCO will still generate a periodic signal even though the control voltage, VC is equal to zero. This frequency is called the free running frequency, ωfr of the VCO. This indicates that the VCO frequency does not need to approach zero for practical range of VC. The output frequency of the VCO, ωo, (specified in radian/s) is expressed as ωo = K VCO VC + ω fr (2-4) where KVCO (specified in radians/s/V) is the gain of the VCO. 10 CHAPTER 2: Frequency Synthesizer From equation (2-4), it can be noticed that changes in the output frequency are a function of the control voltage, VC that is applied to the VCO. This relationship is very important when modeling the relationship between the VCO’s input control voltage and the phase of its output signal [10]-[11]. The VCO model that is going to be presented is a small signal model, which relates changes about an operation point. As the free running frequency, ωfr does not changes with the control voltage, as it is a nonchanging bias term [10], the term ωfr can be ignored in the modeling of the VCO, thus the output frequency, ωo is expressed as ωo = K VCO VC (2-5) dθ dt (2-6) Since ω = The phase of the VCO can be obtained by integrating VCO’s output frequency [13] θ o ( t ) = ∫ ω o ( t )dt (2-7) If Laplace transform is performed on (2-7), equation (2-7) is expressed as θ o (s) = ω o (s) K VCO = VC (s) s s (2-8) where s is jω. which is represented by the model representation shown in Figure 2-5. θ o (s) Figure 2-5 Model of VCO 11 CHAPTER 2: Frequency Synthesizer 2.4. Linear Model of the Frequency Synthesizer The description and basic concept of the phase detector and VCO have been covered in previous two sections. As a result of the derivation of the linear models of the phase detector and VCO in the previous section, the linear model of the frequency synthesizer will be illustrated in this section under the assumption that ∆θ and ωo stay in the linear range of the phase detector and VCO [14]. When the loop is locked, the phase of the divided output signal θo accurately tracks the phase of the reference signal θi. The linear model of frequency synthesizer is shown in Figure 2-6. VOUT Figure 2-6 Linear Model of Frequency Synthesizer With the help of the linear model, the dynamic response and the static phase error will be presented in the next two sections. 2.4.1. Dynamic Response of Frequency Synthesizer With reference to Figure 2-6, the open loop and closed loop transfer function of the frequency can be derived. With the derived transfer function, the dynamic response of 12 CHAPTER 2: Frequency Synthesizer the frequency synthesizer can be studied and this facilitates the design of the frequency synthesizer in this thesis. The divided output phase of the frequency synthesizer is expressed as θ o (s) = ∆θ K PD F(s)K VCO sN (2-9) In addition, the phase transfer function or closed loop response is expressed as H(s) = θ o (s) KF(s) = θ i (s) S + KF(s) where K = (2-10) K PD K VCO N The open loop transfer function of the frequency synthesizer is expressed as H OL (s) = θ o (s) KF(s) = θ i (s) s (2-11) The open loop and closed loop response of the frequency synthesizer when |F(s)| =1 is plotted in Figure 2-7. The frequency synthesizer bandwidth is defined as the frequency when the open-loop gain drops to unity and it is determined by the open loop gain, K. 13 CHAPTER 2: Frequency Synthesizer H (s ) s Figure 2-7 Open loop and Closed loop response of Frequency Synthesizer It can be noticed that the 3dB point of the closed loop response of frequency synthesizer depends on the open loop gain K as well. The above case describes the closed loop response of the frequency synthesizer when |F(s)| =1. Now, a single pole RC loop filter, which is shown in Figure 2-8 is added to the closed loop system. R VIN VOUT C Figure 2-8 Single-pole RC loop filter 14 CHAPTER 2: Frequency Synthesizer The transfer function of the loop filter is expressed as followed: F(s) = ω LPF 1 = 1 + sRC s + ω LPF where ω LPF = (2-12) 1 RC The closed loop transfer function of the frequency synthesizer becomes H(s) = Kω LPF s + sω LPF + Kω LPF (2-13) 2 By adding the single pole filter, the frequency synthesizer system becomes a secondorder system. In circuit and control theory, it is common practice to write the denominator of the transfer function in s 2 + 2ζω n s + ω 2n form, where ζ is the damping factor and ωn is the natural frequency of the system [13]. Thus, Equation (2-13) is expressed as followed: ω 2n H(s) = 2 s + 2ξω n s + ω 2n (2-14) where ω n = ω LPF K ξ= (2-15) 1 ω LPF 2 K (2-16) From the above equations, it can be seen that ωn is the geometric mean of the -3dB bandwidth of the LPF and the loop gain, K. In addition, the damping factor, ζ is inversely proportional to the square root of the loop gain. The frequency response of 15 CHAPTER 2: Frequency Synthesizer such a system is shown in Figure 2-9. Equation (2-15) and (2-16) are one of the design parameters that define the characteristics of the frequency synthesizer. H ( jω ) ∞ Open Loop Response N K 1 0.707 Closed Loop Response ω3dB ωLPF ω Figure 2-9 Frequency Response of 2nd order Frequency Synthesizer (ζ = 0.707) 2.4.2. Static Phase Error In addition to the phase transfer function, a phase-error transfer function, He(s) can be defined as well [8]. The error transfer function describes the frequency synthesizer response to a sudden change in input phase or input frequency. From Figure 2-6, the phase error is defined as 16 CHAPTER 2: Frequency Synthesizer (2-17) ∆θ = θ i − θ o The phase-error transfer function is expressed as H e (s) = s 2 + 2ξω n s ∆θ(s) = 1 − H(s) = 2 θ i (s) s + 2ξω n s + ω 2n (2-18) Firstly, the effect of phase change at the input is being studied and if there is a sudden change of phase at the input, the phase signal change can be expressed as θ i ( t ) = u ( t )dθ (2-19) where u(t) is the unit step function and dθ is the size of the phase step. The Laplace transform of Equation (2-19) is therefore θ i (s) = dθ s (2-20) Equation (2-20) can be inserted into Equation (2-18) to yield ∆θ = H e (s)θ i (s) = (s 2 + 2ζω n s)dθ (s 2 + 2ζω n s + ω 2n )s (2-21) whose final value is given by ∆θ( t → ∞) = lim sH e (s) = 0 (2-22) s →0 The phase error, which also known as static phase error; will eventually reach zero when the system is left alone for a long period. Static phase error is defined as the phase error when time approaches infinity (t →∞) [8]. Next, the effect of frequency change can be studied. If a frequency step is applied at the input of the frequency synthesizer, the angular frequency of the reference signal becomes 17 CHAPTER 2: Frequency Synthesizer (2-23) ωin ( t ) = ωinitial + ∆ωu ( t ) where ∆ω is the magnitude of the frequency step and Equation (2-23) can be integrated to get input phase, which is express as followed θ i = ∆ωt (2-24) The Laplace transform of Equation (2-24) is θ i (s) = ∆ω s2 (2-25) The phase error becomes (s 2 + 2ξω n s)∆ω ∆θ = H e (s)θ i (s) = 2 (s + 2ξω n s + ω 2n )s 2 (2-26) and the final phase error is expressed as ∆θ( t → ∞) = lim sH e (s) = s →0 ∆ω2ξ ∆ω = ωn K (2-27) From Equation (2-27), the phase error due to a sudden change in frequency in the input can be reduced by K. 2.5. Noise Analysis of the Frequency Synthesizer System With the introduction of the basic concept of the frequency synthesizer in the previous section, a brief analysis of noise in the frequency synthesizer will be presented in this section. The frequency synthesizer linear model with the various major noise contributions diagram is shown in Figure 2-10. The main noise contribution comes 18 CHAPTER 2: Frequency Synthesizer from the main components of the frequency synthesizer; they are the reference clock, the phase detector, the low pass filter, the divider and finally the VCO [15]-[16]. K VCO s Figure 2-10 Linear model of Frequency Synthesizer with added noise sources Since the frequency synthesizer is a linear time-invariant system, the noise sources in the linear model are modeled as an additive component in the system. It can be assumed that θr(s), θPFD(s), θLPF(s), θosc(s), θdiv(s) and θi(s) are uncorrelated so that these entire noise sources can be set to zero when the individual transfer function is derived. The transfer function for the various noise input nodes can be expressed as follows: H r (s) = θ out (s) Kω LPF = 2 ( N) θ r (s) s + sω LPF + Kω LPF (2-28) H PD (s) = θ out (s) Kω LPF N = 2 ( ) θ PD (s) s + sω LPF + Kω LPF K PD (2-29) H LPF (s) = θ out (s) Kω LPF N ( ) = 2 θ LPF (s) s + sω LPF + Kω LPF K PD F(s) (2-30) 19 CHAPTER 2: Frequency Synthesizer 2 H osc (s) = θ out (s) Kω LPF s + sω LPF = 2 ( ) θ osc (s) s + sω LPF + Kω LPF Kω LPF (2-31) H div (s) = θ out (s) Kω LPF N = 2 θ osc (s) s + sω LPF + Kω LPF (2-32) where Hr(s) is the reference clock noise transfer function, HPD(s) is the phase detector noise transfer function, HLPF(s) is the LPF noise transfer function, Hosc(s) is the VCO noise transfer function and finally, Hdiv(s) is the divider phase noise transfer function. The total phase noise contributed by each source can be expressed as θ 2 out  2 θ 2PFD θ 2LPF 2  =  θ r + θ div + 2 + K PD [K PD F(s)]2  2  2 2  s + sω LPF  H(s) 2 N 2 + θ osc H(s)     Kω LPF   2 (2-33) From the above equations, it can be seen that the frequency synthesizer acts as a low pass filter for phase noise arising in the reference signal, phase detector, low pass filter and frequency divider. However, the frequency synthesizer acts as a high pass filter for phase noise generated in the VCO. Therefore, to minimize the output noise due to the VCO, the loop bandwidth must be as large as possible. On the other hand, to minimize the phase noise within the loop bandwidth, the in-band noise contributed by the other loop components must be kept to a minimum. It is also important to note that the loop bandwidth must be less than the input reference frequency (around 8 – 10 times) [12] to keep the loop stable and to suppress the spurs at the output due to the reference leakage signal [13]. 20 CHAPTER 2: Frequency Synthesizer 2.6. Relationships of Design Parameters The dynamic response, static phase error and noise analysis of the frequency synthesizer system were analyzed in the previous sections. In this section, the relationship of the design parameters will be studied, as it will provide a guideline in the design of the frequency synthesizer in this thesis. The important factors that affect the design of the frequency synthesizer are summarized as followed: 1. Loop Gain, K 2. Damping factor, ζ 3. Bandwidth of Frequency Synthesizer, ωn 4. Output phase noise of Frequency Synthesizer, θout2 With the above in mind, it can be seen from Equation (2-33) that a high KPD will help to reduce the output phase noise of the system. However, this increase in KPD will cause the bandwidth of the frequency synthesizer to increase as well. This would result in a higher noise in the system, as more phase noise from the input clock will transfer to the output. Fortunately, the reference clock used for this application comes from a clean source like an external crystal, which is generally very low in noise. Despite of this usefulness, there will be a limitation on the increment of loop gain, K, because the damping ratio, ζ, is closely related to the loop gain, K as well. As the increment of the loop gain, K will degrade the settling behavior of the system. Normally in control theory, a well-designed second-order system should have a damping ratio, ζ equal to 0.707 to provide an optimally flat frequency response. Furthermore, the bandwidth of the system must be less than the phase detector update rate to avoid instability issues 21 [12]. The cause and effect of increasing KPD CHAPTER 2: Frequency Synthesizer is summaried in Table 2-1. With each of the above parameters closely interrelated to each other, this creates a dilemma in optimizing the frequency synthesizer system. Table 2-1 Cause and Effect of Increased KPD KPD ↑ Loop Gain, K Increased Static Phase Error Improved Output Phase Noise Improved Bandwidth, ωn Worse Damping Factor, ζ Worse 22 CHAPTER 3: Design of Frequency Synthesizer 3. Design of Frequency Synthesizer The important aspect of the frequency synthesizer has been discussed in the previous chapter. This chapter will focus on the frequency synthesizers that will be implemented in this thesis. Firstly, a brief review on application and specification of the frequency synthesizer will be presented. Thereafter, the important concept and idea in implementing the self-tuning frequency synthesizer will be discussed. 3.1. System Architecture The intended application for our frequency synthesizer is to provide a Local Oscillator (LO) signal for the mixer in the transceiver system for the purpose of up and down conversion of baseband and RF signals respectively. The local oscillator system diagram is shown in Figure 3-1 and a typical up and down conversion topology of a transceiver system is shown in Figure 3-2. Frequency Synthesizer (4.224GHz) Select 1/8 1/2 264MHz 44MHz 528MHz SSB 792MHz SSB Figure 3-1 Local Oscillator System Diagram 23 LO Signal CHAPTER 3: Design of Frequency Synthesizer LPF BPF LNA 0 90 PA LPF ADC AGC LPF ADC LPF DAC LO LPF BPF AGC 0 + 90 LO LPF DAC Figure 3-2 Typical Direct Up and Down Conversion Topology in Transceiver The local oscillator system requires a frequency synthesizer to provide a fixed frequency of 4.224 GHz for the single sideband mixer (SSB) to generate an LO signal at 3432MHz, 3960MHz, and 4488MHz. This LO signal is then applied to the mixer in the transceiver system for the up and down conversion. This local oscillator system is used in the Ultra-Wideband (UWB) Multiband Orthogonal Frequency Division Multiplexing (MBOFDM) system [17]. The MBOFDM standard requires a minimum of band group 1 and the frequency operation for a mode 1 device in shown in Figure 3-3 [17]. The specification of the frequency synthesizer design is summarized in Table 3-1 and the system architecture of the frequency synthesizer is shown in Figure 3-4. 24 CHAPTER 3: Design of Frequency Synthesizer Band #1 Band #2 Band #3 3432 MHz 3960 MHz 4488 MHz f Figure 3-3 Frequency of Operation for Mode 1 Device [17] Table 3-1 Technical Specification of Frequency Synthesizer Process Technology IBM SiGe BICMOS 6HP (0.25µm) Supply Voltage 2.5 Volt Temperature 0 to 100oC Frequency 4.224 GHz Frequency Synthesizer System Phase Margin 55.88° Frequency Synthesizer System Bandwidth 60 kHz Tuning Voltage 1 Volt (0.75 V to 1.75 V) Tuning Circuit Upper Limited Trigger Point 1.85 V Tuning Circuit Lower Limited Trigger Point 0.65 V Phase Noise @ 10KHz -65 dBc/Hz @ 100 KHz -80 dBc/Hz @ 1MHz -100 dBc/Hz @ 10 MHz -120 dBc/Hz Crystal Frequency 44 MHz +/- 20 PPM 25 CHAPTER 3: Design of Frequency Synthesizer Auto Tuning Circuit Lock Detector Oscillator (44MHz) PFD Low Pass Filter CP VCO (4.224GHz) Divider (1/96) PFD : Phase Frequency Detector CP : Charge Pump Figure 3-4 System Architecture of Frequency Synthesizer The Frequency Synthesizer consists of the following blocks: 1. Phase Frequency Detector (PFD) 2. Charge Pump (CP) 3. Low Pass Filter (LPF) 4. Voltage Controller Oscillator (VCO) 5. Divider 6. Lock Detector 7. Self tuning Circuit – the theory and operation will be discussed in the next section 8. Crystal Oscillator 26 CHAPTER 3: Design of Frequency Synthesizer 3.2. Self tuning Circuit Design In section 2.6, the advantages and disadvantages of increasing the KPD is presented and it is known that K is directly proportional to KVCO and KPD. In addition, K is also inversely proportional to N, which means that there are ways to increase KPD without increasing K. One way of increasing the KPD without affecting the frequency synthesizer bandwidth, ωn, and damping factor, ζ, is to reduce KVCO proportionally or increasing N to keep the loop gain, K in constant. The latter is not a good choice, as it will increase the output phase noise as indicated by Equation (2-33). Furthermore, the choice of N is greatly restricted by the application. Thus, any increase in KPD has to be counterbalanced by reducing KVCO. Fortunately, this is a good choice for designer to proceed as the output frequency; ωo, indicated by Equation (2-4) is directly related to the gain of the VCO, KVCO and the control voltage, VC. This means that the VCO is less sensitive to the noise at the control port. 3.2.1. Frequency Synthesizer Tuning Range The tuning range is one of the important specifications in frequency synthesizer design. It determines the range of frequencies covered by a frequency synthesizer. Table 3-2 shows the absolute and relative tuning range for different standards [18]. 27 CHAPTER 3: Design of Frequency Synthesizer Table 3-2 Different Standard Absolute and Relative Tuning Range Absolute Tuning Relative Tuning Range Range (MHz) (%) Standard FM Radio 87.5 – 108 21 TV Receiver 41-960 184 GSM Transmitter 890-915 2.8 GSM Receiver 925-960 3.7 Bluetooth 2400-2483 3.4 UWB MBOFDM Band 1 3168-4752 40.8 UWB MBOFDM Band 1 to Band 5 3168-10560 127.8 With the information of the absolute tuning range, the designer can roughly calculate the tuning constant or VCO gain, KVCO. For example, the absolute tuning range for a GSM receiver is 925 MHz to 960 MHz (35 MHz) and the tuning voltage is around 2 V, the estimated KVCO will be 17.5 MHz/V. A typical oscillator tuning range curve is shown in Figure 3-5. The tuning range of the oscillator is almost linear in most portion of the tuning voltage except at the beginning and at the end of the tuning voltage, where parasitics start to affect the KVCO. Another reason for this phenomenon is the voltage, VC , reach the upper or lower limit of the design. 28 CHAPTER 3: Design of Frequency Synthesizer FREQ Oscillator Frequency Non Linear Tuning Voltage Volt Figure 3-5 Typical Tuning Range Curve of Oscillator While the roughly calculated KVCO gain is around 17.5 MHz/V for the GSM case, one may wonder what could be the KVCO gain for this thesis. As mentioned in the previous section, the frequency synthesizer is supposed to be designed for UWB MFOFDM Band 1 system. This indicates that the KVCO would need 792 MHz/V for a 2 V tuning voltage to cover the whole range. This is undesirable as the system design would require a low KVCO to compensate for the higher KPD design but this is not the case, as the local oscillator system does not require the frequency synthesizer to cover the whole range but rather to provide an accurate frequency of 4.224 GHz. The oscillator system will create the desired frequency using frequency translation method. The same concept is used to create the other frequencies for Band 2 to 5 in the UWB MBOFDM standard. Another important reason to use the frequency translation method to generate different desired frequency bands is that the channel switch time’s requirement is 9 ns. Although the frequency synthesizer is only required to provide one fixed frequency for the oscillator system, this does not mean that there is no tuning range specification for the frequency synthesizer. Other than the standard tuning range, when designing the 29 CHAPTER 3: Design of Frequency Synthesizer VCO, the designer has to consider process variation as well. The process spread during fabrication can contribute 30% drift in the oscillating frequency in the VCO. Normally, the designer is required to run corner simulation or Monte Carlo simulation to determine the maximum process spread in the process. This maximum process spread will determine the tuning range required for this thesis. A study is done on the process spread using the IBM SiGe BICMOS 6HP (0.25µm) process on the VCO design (the circuit level of the VCO will be discussed in Chapter 4) in order to estimate the rough KVCO gain. A control voltage of 1.25 V, which is the mid point of the tuning voltage, is applied to the VCO for different process corner. Table 3-3 shows the frequency spread due to the process variation. It is noticed that there is a spread of 234 MHz under the worst-case condition. Based on the tuning voltage of 1 V, it would require a minimum KVCO gain of 468 MHz/V to tune the VCO to 4.224 GHz under the worst-case condition. Otherwise, the frequency synthesizer will not be able to lock if the KVCO gain is less than 468 MHz/V. This would set the minimum KVCO gain for the frequency synthesizer design. Table 3-3 Frequency Spread due to Process variation Frequency (GHz) Frequency Difference (Compared to Typical) Typical 4.224 0 Slow 4.026 -198 MHz Fast 4.458 234 MHz Process Corner 30 CHAPTER 3: Design of Frequency Synthesizer 3.2.2. Self-Tuning Concept In the beginning of the section, the way to improve the noise performance of the frequency synthesizer design is to increase KPD and decrease KVCO accordingly. However, the process spread will limit the minimum KVCO of the VCO design. Furthermore, with advancements in CMOS technology, the supply voltage will decrease too and it would cause KVCO to increase further as the dynamic range of the tuning voltage of the VCO is reduced. This really creates a huge challenge in frequency synthesizer design. In this section, the concept and idea of the tuning circuit will be presented. The purpose of the tuning circuit is to tune the VCO to the desired frequency when the frequency synthesizer system is started up. This would allow the designer to design a low KVCO VCO. The proposed tuning of the VCO is shown in Figure 3-6. Instead of designing an excessively high gain, KVCO to cover the entire tuning range, an overlapping low gain, KVCO, which covers the desired frequency is designed [19]. This allows a low gain KVCO to be designed. 31 CHAPTER 3: Design of Frequency Synthesizer FREQ Excessively High Gain, KVCO Desired Frequency Overlap Tuning Voltage Volt Figure 3-6 Tuning Voltage of Proposed System The tuning circuit will monitor the control voltage of the frequency synthesizer system. If the divided frequency of the VCO is higher than the reference frequency, the PFD and CP will work together to decrease the control voltage to the VCO, which will reduce the VCO frequency. The opposite will occur when the divided frequency of the VCO is lower than the reference frequency. The control voltage will gear toward ground for the former and control voltage will gear toward VDD for the latter. With the understanding of control voltage behavior, the tuning circuit will monitor the control voltage and increase or decrease the frequency of the VCO until the frequency synthesizer is locked. The flow chart of the tuning circuit is shown in Figure 3-7 and the block diagram of the tuning circuit is shown in Figure 3-8. The two comparators in the tuning circuit will monitor the control voltage and compare it with a predefined upper and lower voltage boundary, when the control voltage exceeds the upper or fall 32 CHAPTER 3: Design of Frequency Synthesizer below the lower boundary, it will assert a control signal to the tuning circuit controller. The controller will increase or decrease the frequency of the VCO based on the control signal. The tuning circuit will cease its operation when the system is phase locked. START Monitor Control Voltage, VC VC>VH Monitor Lock Signal VC[...]... effectiveness of the design technique, a self- tuning frequency synthesizer was designed and fabricated in a 0.25 µm IBM SiGe process [7] Although the process allows the use of bipolar devices, only CMOS devices are used to design the entire frequency synthesizer, as this is the project requirement The frequency synthesizer is able to self- tune the output frequency of the VCO to the desired frequency when... Response of Frequency Synthesizer With reference to Figure 2-6, the open loop and closed loop transfer function of the frequency can be derived With the derived transfer function, the dynamic response of 12 CHAPTER 2: Frequency Synthesizer the frequency synthesizer can be studied and this facilitates the design of the frequency synthesizer in this thesis The divided output phase of the frequency synthesizer. .. introduced and the parameters that affect the design of frequency synthesizer are presented Finally, the noise analysis of the frequency synthesizer is being studied 2.1 Basic Concept of the Frequency synthesizer PLL based frequency synthesizer has a frequency divider in the feedback loop The basic frequency synthesizer system is shown in Figure 2-1 It consists of a phase detector, low pass filter, voltage... Damping Factor, ζ Worse 22 CHAPTER 3: Design of Frequency Synthesizer 3 Design of Frequency Synthesizer The important aspect of the frequency synthesizer has been discussed in the previous chapter This chapter will focus on the frequency synthesizers that will be implemented in this thesis Firstly, a brief review on application and specification of the frequency synthesizer will be presented Thereafter,... MBOFDM standard requires a minimum of band group 1 and the frequency operation for a mode 1 device in shown in Figure 3-3 [17] The specification of the frequency synthesizer design is summarized in Table 3-1 and the system architecture of the frequency synthesizer is shown in Figure 3-4 24 CHAPTER 3: Design of Frequency Synthesizer Band #1 Band #2 Band #3 3432 MHz 3960 MHz 4488 MHz f Figure 3-3 Frequency. .. introduction of the basic concept of the frequency synthesizer in the previous section, a brief analysis of noise in the frequency synthesizer will be presented in this section The frequency synthesizer linear model with the various major noise contributions diagram is shown in Figure 2-10 The main noise contribution comes 18 CHAPTER 2: Frequency Synthesizer from the main components of the frequency synthesizer; ... design parameters will be studied, as it will provide a guideline in the design of the frequency synthesizer in this thesis The important factors that affect the design of the frequency synthesizer are summarized as followed: 1 Loop Gain, K 2 Damping factor, ζ 3 Bandwidth of Frequency Synthesizer, ωn 4 Output phase noise of Frequency Synthesizer, θout2 With the above in mind, it can be seen from Equation... result and problems faced during the implementation of the frequency synthesizer In Chapter 5, the test results of the frequency synthesizer are presented Finally, the conclusion of the thesis will be presented in Chapter 6 6 CHAPTER 2: Frequency Synthesizer 2 Frequency Synthesizer Modern communication systems use frequency synthesizers for quite a number of purposes, namely to recover the clock from digital... to the square root of the loop gain The frequency response of 15 CHAPTER 2: Frequency Synthesizer such a system is shown in Figure 2-9 Equation (2-15) and (2-16) are one of the design parameters that define the characteristics of the frequency synthesizer H ( jω ) ∞ Open Loop Response N K 1 0.707 Closed Loop Response ω3dB ωLPF ω Figure 2-9 Frequency Response of 2nd order Frequency Synthesizer (ζ = 0.707)... MHz -120 dBc/Hz Crystal Frequency 44 MHz +/- 20 PPM 25 CHAPTER 3: Design of Frequency Synthesizer Auto Tuning Circuit Lock Detector Oscillator (44MHz) PFD Low Pass Filter CP VCO (4.224GHz) Divider (1/96) PFD : Phase Frequency Detector CP : Charge Pump Figure 3-4 System Architecture of Frequency Synthesizer The Frequency Synthesizer consists of the following blocks: 1 Phase Frequency Detector (PFD) ... 3: Design of Frequency Synthesizer Design of Frequency Synthesizer The important aspect of the frequency synthesizer has been discussed in the previous chapter This chapter will focus on the frequency. .. specification of the frequency synthesizer design is summarized in Table 3-1 and the system architecture of the frequency synthesizer is shown in Figure 3-4 24 CHAPTER 3: Design of Frequency Synthesizer. .. effect of frequency change can be studied If a frequency step is applied at the input of the frequency synthesizer, the angular frequency of the reference signal becomes 17 CHAPTER 2: Frequency Synthesizer