Characterization and numerical simulation of gallium nitride based metal oxide semiconductor high electron mobility transistor with high k gate stack

CHARACTERIZATION AND NUMERICAL SIMULATION OF GALLIUM NITRIDE-BASED METAL-OXIDE-SEMICONDUCTOR HIGH ELECTRON MOBILITY TRANSISTOR WITH HIGH-K GATE STACK LOW KIM FONG EDWIN (B. ENG (HONS.), NATIONAL UNIVERSITY OF SINGAPORE) A THESIS SUBMITTED FOR THE DEGREE OF MASTER OF ENGINEERING DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE ACKNOWLEDGEMENTS The author would like to acknowledge his heartfelt gratitude to his supervisors, Associate Professor Tan Leng Seow and Dr. Yeo Yee Chia as well as his mentor from the Data Storage Institute, Dr. Lee Hock Koon. Their guidance and attitude towards excellence has always been a source of inspiration. Their care and concern for the author makes this journey to be one of not only academic in nature but also spiritual. Their knowledge and integrity has taught the author that only when one possesses both can success be possible. In addition, the author would also like to take this opportunity to thank the mentors at GlobalFoundries Singapore. Special thanks go to Dr. Lap Chan, Dr. Ng Chee Mang and Mr. Leong Kam Chew. Without this scholarship opportunity, the author would not have been able to go on this enlightening journey. The author would also like to thank the staff and friends in Silicon Nano Devices Laboratory (SNDL) and Data Storage Institute (DSI) for their help and companionship. It has been a challenging journey but enlightening nonetheless. Last but not least, the author would like to thank his friends and family for putting up with him throughout this journey. Without their encouragement and support, this journey would not have been possible. Special mention is given to the author’s girlfriend, Charmaine Yeong, for enduring these difficult times with the author together. Thank you. I CONTENTS ACKNOWLEDGEMENTS I CONTENTS II SUMMARY V LIST OF TABLES LIST OF FIGURES LIST OF SYMBOLS AND ABBREVIATIONS Chapter 1 Introduction VIII IX XV 1 1.1 Background 1 1.2 Scope and Purpose 5 1.3 Organisation of Thesis 8 Chapter 2 Theory of GaN-based Heterojunction Structures and Devices 2.1 GaN Crystalline Structure 2.2 Polarisation effect in AlGaN/GaN Heterostructure 9 9 10 2.2.1 Spontaneous Polarisation 11 2.2.2 Piezoelectric Polarisation 15 2.3 High Electron Mobility Transistor 17 2.4 Metal-Oxide-Semiconductor High Electron Mobility Transistor 18 Chapter 3 Device Fabrication and Characterisation 3.1 Mask Design 21 21 3.1.1 Mesa Isolation 22 3.1.2 Source-Gate/Drain-Gate Separation 22 II 3.1.3 3.2 Other Test Structures 23 Device Fabrication Procedure 29 3.2.1 Surface Passivation 33 3.2.2 Diamond-like Carbon (DLC) Layer 34 3.3 Electrical Characterisations of the MOSHEMTs 37 3.3.1 Effect of Surface Passivation on the ID-VGS Characteristics 38 3.3.2 Effect of Surface Passivation on ID-VDS Plot 39 3.3.3 Effect of DLC Liner on C-V characteristics 40 3.3.4 Effect of DLC liner on the ID-VGS Characteristics 41 3.3.5 Effect of DLC compressive stress liner on the ID-VDS Characteristic 43 Chapter 4 Numerical Simulation Fundamentals 4.1 Simulation Basics 45 45 4.1.1 Device Structure 49 4.1.2 Carrier Transport 56 4.1.3 Mobility Model 58 4.2 Effect of different AlGaN Layer thickness 63 4.3 Effect of Interface Traps on Device Operations 73 4.3.1 Effect of Surface Passivation Chapter 5 Simulation of the Effect of Stress on AlGaN/GaN MOSHEMT 77 80 5.1 Device Structure and Stress Model 81 5.2 Effect of Stress on Electrical Characteristics 87 5.3 Effect of Stress on Carrier Concentration 89 5.4 Effect of Stress on Carrier Mobility 91 III Chapter 6 Conclusion 6.1 Possible Future Work 94 96 References 97 Appendix A 111 Appendix B 117 List of Publications 124 IV SUMMARY In this work, the fabrication of the AlGaN/GaN MOSHEMT was performed and the process was preceded by the design of the necessary mask set. In addition to the devices that were required for characterisation, several other support and test structures were designed and included into the mask layout. These structures included the Van Der Pauw structure, Vernier Alignment Scale structure, Transmission Line Model (TLM) structure, Step Coverage structure and devices with long gate widths. In the fabrication of the devices, the splits of the experiments with different configurations were discussed with focus on the objective of these processes and their characterisation. Electrical measurement was the main mode of characterisation in this work. Methods such as the C-V, ID-VGS and ID-VDS measurement were performed on experimental devices. The enhancements in device performance due to certain fabrication processes employed in the experiments were evident from the results of the electrical characterisations. In order to better understand these enhancements, a numerical simulation project was undertaken and the results of these simulations are presented in this thesis. Sentaurus TCAD simulation suite was used for the device simulations. The simulation physics and models were discussed before some preliminary simulation results were presented. The simulation results presented was generally in line with the device physics understood from various literatures and in some cases shed light on the possible V mechanism of the performance enhancement of the devices by some of the fabrication techniques introduced in the experiments. Firstly, simulation of the effect of different thickness of AlGaN barrier layer and their effect on device performance was performed and this gave results that were in line with the literature as described by Ibbetson in [1]. Next, the effect of interface states on device performance was simulated. The reduction of donor-like states in the interface between the AlGaN and high-k gate dielectric caused the 2DEG density to reduce accordingly, resulting in a lower drive current. However, this is not consistent with the surface passivation technique discussed in the fabrication process. This process was shown in the electrical characterisation to improve the drive current by more than 50%. Thus, a different mechanism was proposed in the simulation. Acceptor-like traps and donor-like traps were postulated to be present at the abovementioned interface. The hypothesis is that the surface passivation technique would tend to passivate more acceptor-like traps. This effect was simulated and the results of the simulation show a close resemblance of the effect seen in the characterisation of the experimental devices. Finally, the effect of a Diamond-Like Carbon (DLC) stress liner on the MOSHEMT was also simulated and it was shown that this compressive stress liner not only VI provided a compressive stress in the gate region but also a coupled tensile stress in the region beyond the gate region. This change in carrier distribution resulted in a positive shift in threshold voltage as well as a slight enhancement in drive current. It is noted that in this simulation, the stress was simulated using a separate simulation program and the resulting polarisation charge was input into the Sentaurus TCAD simulation suite separately, thus the effect of change in mobility due to band structure deformation [2] and change in trap concentration [3] were not simulated accordingly. For this reason, this simulation could only be a qualitative description of the actual effect of stress on AlGaN/GaN MOSHEMTs. VII LIST OF TABLES Table I. A comparison of semiconductor material parameters at 300K is presented [4]. Table II. 2 Competitive Advantage of GaN devices in terms of the requirements of different types of devices is presented [5]. Table III. A comparison of the lattice constants, spontaneous and piezoelectric constants/coefficients of GaN and AlN [6]. Table IV. 53 The default coefficients for GaN in the Masetti model [7]. Table V. 3 60 The default coefficients for Silicon in the Lombardi Model [7]. These coefficients are used for the simulation due to a lack of these values for GaN in the literature. Table VI. 63 The configurations of device used for simulation with varying AlGaN thickness. 65 VIII LIST OF FIGURES Figure 1.1. Illustration of a typical structure of a Heterojunction Field Effect Transistor. 4 Figure 2.1. A wurtzite structure of GaN crystal (Ga-faced) and its various planes [20].9 Figure 2.2. A Wurtzite crystal of GaN (N-face) with lattice constants c and a [9]. 11 Figure 2.3. The GaN crystal is often represented by the tetrahedral stick and ball figure - P0 refers to the polarisation vector in the structure [10]. 12 Figure 2.4. A representation of the polarisation profile of a nitride-based semiconductor heterostructure [10]. 13 Figure 2.5. A graphical representation of the spontaneous polarisation in nitride-based alloys according to Vegard's Law interpolation [26]. 15 Figure 2.6. The tetrahedral stick and ball representation of GaN undergoing tensile strain [10]. 16 Figure 2.7. The energy band diagram of AlGaN/GaN Heterojunction. 19 Figure 2.8. A typical illustration of a Metal-Oxide-Semiconductor High Electron Mobility Transistor. 20 Figure 3.1. a) A typical transistor design for the purpose of DC characterisation. W, L and LD-G referred to the gate width, gate length and drain-gate separation respectively. b) The width of a mesa island would dictate the gate width of a transistor. 22 Figure 3.2. The design of a Van Der Pauw Structure in this mask set design. 23 Figure 3.3. The design of the Vernier Alignment Scale Structure used in this mask set design. 24 IX Figure 3.4. The design of the Transmission Line Model (TLM) Structure used in this mask set design. 25 Figure 3.5. An example of a typical Resistance vs. Contact spacing plot extracted from TLM measurement. 26 Figure 3.6. An 3D illustration of the gate metal being deposited over a step of the mesa island. 27 Figure 3.7. The design of the step coverage test structure used in this mask set design. 27 Figure 3.8. The design of the long gate width transistor design. 28 Figure 3.9. The starting layer structure of HEMT wafer before the fabrication process. 29 Figure 3.10. The fabrication process of AlGaN/GaN MOSHEMT [31]. 30 Figure 3.11. An illustration of the device schematic of a completed AlGaN/GaN MOSHEMT. 32 Figure 3.12. An illustration of the device schematic of an AlGaN/GaN MOSHEMT with a DLC stress liner. 33 Figure 3.13. The average compressive stress induced in the channel due to 40 nm DLC simulated for various LG: 300 nm, 500 nm and 700 nm [31]. 36 Figure 3.14. The effect of the surface passivation technique on the ID-VGS plot of MOSHEMTs with LG = 2 µm. Incorporation of In situ SiH4 passivation improved subthreshold swing to 100 mV/decade and gm of 95 mS/mm [31]. 38 Figure 3.15. The effect of surface passivation on ID-VDS plot of MOSHEMT with LG = 2 µm. ID,sat of 624 mA/mm measured at VD = 10 V and VG = 4 V was observed. 39 X Figure 3.16. The C-V characteristics of a control device and the device with 40 nm DLC liner deposited on a MOSHEMT with LG = 300nm. 40 Figure 3.17. The effect of the DLC stress liner (Compressive Stress) on the ID-VGS charactieristics of a MOSHEMT with LG = 300 nm. Low SS of 110 mV/decade and high gm of 88 mS/mm were achieved for the device with DLC liner [31]. 42 Figure 3.18. The effect of the DLC Stress liner (Compressive Stress) on the ID-VDS characteristic with LG = 300 nm [31]. 43 Figure 4.1. A flowchart showing the process of device simulation (Names in bracket denote name of program used for that purpose). 46 Figure 4.2. An example of a Meshing Strategy for a 2D device in Sentaurus simulation program [7]. 48 Figure 4.3. The schematic diagram of the simulated structure in Sentaurus TCAD. 49 Figure 4.4. An illustration of the interfaces with its polarisation and the respective induced polarisation charges. 52 Figure 4.5. The graph of the 2DEG density measured as a function of Al0.34Ga0.66N barrier thickness @ room temperature. Solid dots are experimental data, curve represent least square fit of equation (4.22) up to 15 nm [1]. 64 Figure 4.6. Simulated ID-VGS characteristics of devices (VDS = 0.1 V) with different AlGaN thickness. The threshold voltage are, VTH(20 nm) = -4.20 V, VTH(15 nm) = 3.25 V, VTH(10 nm) = -2.25 V, VTH(5 nm) = N.A. 66 Figure 4.7. The electron density mapping in device with 5nm thick AlGaN layer. 67 Figure 4.8. The electron density mapping in device with 10 nm thick AlGaN layer. 68 Figure 4.9. The electron density mapping in device with 15 nm thick AlGaN layer. 68 XI Figure 4.10. The electron density mapping in device with 20 nm thick AlGaN layer. 69 Figure 4.11. A plot showing the simulated 2DEG density as a function of Al0.25Ga0.75N barrier thickness. The 2DEG density ranges from 8.69×104 cm-2 @ 5nm to 5.90×1012 cm-2 @ 20nm AlGaN layer thickness. 70 Figure 4.12. The energy band diagram of AlGaN/GaN MOSHEMT with 5 nm thick AlGaN layer extracted from the simulation. 71 Figure 4.13. The energy band diagram of AlGaN/GaN MOSHEMT with 20 nm thick AlGaN layer extracted from the simulation. 72 Figure 4.14. A schematic diagram showing where energy level of donor-like surface states reside in a) thin AlGaN layer that is < critical thickness b) thicker AlGaN layer > critical thickness [1]. 73 Figure 4.15. The energy level of the trap in a device with 20 nm thick AlGaN layer being programmed in this simulation run. 74 Figure 4.16. A ID-VGS plot of simulated devices with different donor-like trap concentration. 75 Figure 4.17.The simulated space charge data on AlGaN/GaN MOSHEMT at gate region extracted from the simulation. 76 Figure 4.18. The ID-VGS plot of devices with different concentration of acceptor-like trap. 78 Figure 4.19. The ID-VDS plot of devices with different concentration of acceptor-like traps. 79 XII Figure 5.1. The schematic view of the AlGaN/GaN MOSHEMT with a compressive Diamond-Like Carbon (DLC) liner. The 2-DEG density decreases with application of compressive stress. 81 Figure 5.2. The schematic diagram of the device being simulated in Sentarus TCAD and Abaqus for the effect of compressive stress liner. The X and Y-axes denote the device geometry that was used in this simulation. 82 Figure 5.3. A map depicting the StressXX distribution that is experienced in a simulated AlGaN/GaN device with LG = 300 nm due to 40nm of DLC compressive stress liner. 83 Figure 5.4. A plot of the average StressXX distribution that is experienced in the AlGaN layer of the device structure shown in Figure 5.2. 85 Figure 5.5. a) Polarisation induced charges at the interface of AlGaN/GaN due to compressive stress by the DLC stress liner, dashed horizontal line denotes the uniform polarisation charge in a non-stressed device. b) A corresponding device schematic illustrating the device geometry. 86 Figure 5.6. The ID-VGS plot of the MOSHEMT device with and without the DLC stress liner. The gate length of the devices, Lg = 300nm. 87 Figure 5.7. The effect of compressive stress from DLC stress liner on the ID-VDS plot of simulated device with Lg = 300nm. 88 Figure 5.8. A plot of the simulated 2DEG density in the x-direction of the device at a depth of 1 nm below the AlGaN/GaN interface. A reduction of electron density is observed in the channel region under the gate while a slight increase in electron density is observed outside the gate region. 90 XIII Figure 5.9. A plot of the simulated electron mobility value along the x-axis of the MOSHEMT with and without stress, at a depth of 1 nm below the AlGaN/GaN interface. 91 Figure 5.10. A plot of the simulated vertical electric field along the x-direction of the MOSHEMT with and without stress, at a depth of 1nm below the AlGaN/GaN interface. 93 XIV LIST OF SYMBOLS AND ABBREVIATIONS ABBREVIATIONS DESCRIPTION/ EXPANSION GaN Gallium Nitride AlGaN Aluminium Gallium Nitride TaN Tantalum Nitride HFET Heterojunction Field Effect Transistor MODFET Modulation Doped Field Effect Transistor HEMT High Electron Mobility Transistor MOSFET Metal-Oxide-Semiconductor Field Effect Transistor MESFET Metal-Semiconductor Field Effect Transistor 2-DEG 2-Dimensional Electron Gas CFOM Combine Figure of Merit SiC Silicon Carbide AlN Aluminium Nitride GaAs Gallium Arsenide i-GaN Intrinsic Gallium Nitride DC Direct Current RIE Reactive Ion Etching MOCVD Metal Organic Chemical Vapour Deposition PDA Post Deposition Anneal FCA Filtered Cathodic Arc DLC Diamond-like Carbon XV TLM Transmission Line Model VA Vacuum Annealing C-V Capacitance-Voltage DUT Device Under Test SYMBOL DESCRIPTION/ EXPANSION Eg Band Gap vsat Saturation Velocity χ Thermal Conductivity ε Dielectric constant µe Electron Mobility LS-G Source-Gate Length LD-G Drain-Gate Length Rc Contact Resistance LT Transfer Length Vth Threshold Voltage Cox Oxide Capacitance VGS Gate Voltage VDS Drain Voltage ID Drain Current SS Sub-threshold Swing PPE Piezoelectric Polarisation XVI PSP Spontaneous Polarisation ϵ Strain Polarisation Charge ψ Electrostatic Potential Lg Gate Length NA Density of ionised acceptor ND Density of ionised donor XVII Chapter 1 Introduction 1.1 Background Group III-Nitride semiconductors have long been hailed as promising materials for optoelectronic devices, high power or high temperature electronic devices as well as for high-frequency applications. This is due largely to the intrinsic properties of these nitride semiconductors. Thus, the semiconductor industry has shown particular interest in Gallium Nitride (GaN)-based transistors. The global market for GaN-based devices experienced a 260% growth in 5 years from 1998 to 2003 [8]. However this growth is largely limited to the optoelectronics market as the microelectronics market for GaN is still at its infancy. Several other III-V compound semiconductors, such as Arsenide-based and Phosphide-based semiconductors, are also being aggressively researched on. However, GaN with its excellent material properties and electron transport properties prove to be a suitable material for general electronics with high temperature, high power or high frequency requirements. Table I compares the various parameters of GaN, other III-V compound semiconductors, and Silicon. The combined figure of merit (CFOM) also shows that it is one of the most suitable materials for high temperature, high power or high frequency applications [4]. 1 Table I. A comparison of semiconductor material parameters at 300 K [4]. Property Bandgap Eg (eV) Si GaAs 4H-SiC GaN 1.12 1.42 3.25 3.40 0.25 0.4 3.0 4.0 1350 6000 800 1300 1.0 2.0 2.0 3.0 1.5 0.5 4.9 1.3 11.8 12.8 9.7 9.0 1 8 458 489 Breakdown field EB (MV/cm) Electron mobility µ 2 (cm /V s) Maximum velocity vsat 7 (10 cm/s) Thermal conductivity χ (W/cm K) Dielectric constant ε CFOM = (χ ε µ vsat EB) / ( χ ε µ vsat EB)Si CFOM: Combined figure of merit for high temperature/high power/high frequency applications. GaN with a large bandgap (Eg = 3.40 eV), large critical breakdown field of 4.0 MV cm-1, coupled with good electron transport properties (theoretical electron mobility, µe, of up to 2000 cm2 V-1s-1 [9] and a peak saturation velocity, vsat, of 3.0×107 cm s-1 at room temperature) and good thermal conductivity makes it the basic material in the nitride class of material that is typically used for all device layers that requires fast 2 Table II. Competitive Advantage of GaN devices in terms of the requirements of different types of devices [5]. Needs Enabling Feature High Power Wide Bandgap, High Field Performance Advantage Compact, Ease of Impedance Matching Eliminate/Reduce need for High Voltage High Breakdown Field voltage conversion Operation Bandwidth, µ-wave/mmHigh Frequency High Electron Velocity wave High dynamic range Low Noise High Gain, High Velocity receivers High Temperature Wide Bandgap Rugged, Reliable Operations Direct Bandgap Technology Leverage Enabler for Lighting carrier transport or a high breakdown voltage. Table II presents the competitive advantages that GaN devices offer. Several types of devices had been fabricated using GaN with the objective of exploiting its outstanding intrinsic property for transistor usage. Research groups around the world are still trying to develop the best baseline process to build devices 3 Figure 1.1. Illustration of a typical structure of a Heterojunction Field Effect Transistor. such as GaN based Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) and Metal-Semiconductor Field Effect Transistor (MESFET). However, due to the immaturity of the technology of material growth [8], it is still a challenge to make high quality epitaxial layer on various substrates. Thus GaN layers often come with high density of defects, primarily due to the difference in lattice constant of GaN and the substrate it is grown on. This makes surface channel devices generally more susceptible to anomalies due to these defects. In order to overcome this challenge, the Heterojunction Field Effect Transistor (HFET) is a generally preferred candidate for the fabrication of GaN-based devices (Figure 1.1) as it presents a buried channel which is less susceptible to these defects. These transistors are also commonly known as Modulation Doped Field Effect Transistors (MODFETs) or High Electron Mobility Transistors (HEMTs). The MODFET generally refers to a HFET where one of the layers is doped to supply the channel 4 layer, which is generally undoped, with carriers to form the conductive channel. This conductive channel is usually confined in a quantum well due to bandgap discontinuity and consequently, band-bending that occurs in such structures. It is the nature of the confinement of this conductive channel that this channel is often known as the 2-Dimensional Electron Gas (2DEG). This buried 2DEG channel eliminates the effect of impurity scattering due to the absence of dopants in the channel. This allows the achievement of high electron mobility. However, the disadvantage of such a device would be a reduction of gate control as the gate would generally be further away from the channel, as compared to a surface-channel device. In a GaN-based HFET, doping of a supply layer is not necessary as there is presence of a strong polarisation effect [10] in an AlGaN/GaN heterojunction. This polarisation effect allows the formation of the 2DEG without any doping involved. The polarisation effect and the operation of the HEMT device will be further elaborated in the next chapter. 1.2 Scope and Purpose Having discussed the advantages of GaN semiconductor material as being a suitable candidate for high power and high temperature purposes, a GaN-based HEMT would thus be the choice candidate for electronic devices capable of withstanding high power and high temperature. However, the GaN HEMT does face some challenges despite the various advantages. 5 Firstly, the GaN growth technology is still at its infancy and GaN epitaxial layers required in HFETs often have high concentration of bulk and surface defects. These defects would include dislocations and possible dangling bonds on the barrier surface. Although the 2DEG is buried, charges trapped by these defects could cause Coulomb scattering to take place in the channel. In addition, it could also degrade highfrequency performance by reducing the cut-off frequency [11, 12] and even affect the breakdown voltage as the defects might enhance impact ionisation due to the electric field concentration at the gate electrode edge [13]. This could pose serious degradation problems in high power and high frequency devices. Secondly, there is a substantial gate leakage current present in such a structure. Unlike the MOSFET structure, the absence of a gate dielectric would be detrimental to the gate current leakage levels. Comparing this gate leakage current to an ideal Schottky gate device shows that in the AlGaN/GaN HEMT device, the Schottky gate leakage current is very much higher than that of an ideal Schottky gate reverse current requirements [14, 15]. Thus a MOSHEMT would be able to overcome these difficulties faced by a HEMT device. There is also a problem of self-heating in such structure. It was mentioned previously that GaN has good thermal conducting properties. However, as the GaN epitaxial layer is most often grown on sapphire, being the most cost effective substrate available currently, heat might be not be efficiently channelled away through the sapphire substrate which is a poor thermal conductor. Solutions have been offered such as 6 changing the substrate to silicon (Si) or silicon carbide (SiC) [16] as these substrates have lattice constant that are closer to that of GaN and are able to conduct heat better than sapphire. However, the growth process of GaN on such substrates is usually more difficult or expensive. One of the more pressing challenges that the GaN-based HEMT faces is the realisation of enhancement-mode devices. GaN HEMTs are usually depletion-mode devices which are less desirable in electronic circuit applications. In order to realise enhancement-mode devices, several different techniques has been proposed. These include recessed gate technique [17], surface treatment [18] and an addition of a cap layer [19] to alter the band structure. In this thesis, experimental devices with some of these techniques used in its fabrication will be characterised. In addition, simulations will also be carried out to better understand these processes. In this thesis, characterization and simulation studies were performed to study the possible performance enhancement of GaN-based HEMTs for applications in highpower electronics. Simulation work was performed to understand the effect of different parameters on the electrical performance of the device. Effect of various parameters such as barrier layer thickness, concentration and energy level of interface traps as well as thermal effects were investigated. The simulation of the effect of stress due to the DLC liner on the performance of the GaN MOSHEMTs is also done. 7 1.3 Organisation of Thesis This thesis is organised into 6 main chapters. Chapter 2 provides insights on the theoretical background of heterojunction structures and introduces the different devices that are characterised and simulated in this work. Chapter 3 presents the characterisation techniques that are used in this project as well as the relevant characterisation results that had been performed. Chapter 4 explains the fundamental models that are used in this simulation work and the initial simulation work done. It also discusses the capability of the simulation software to implement the theoretical models that had been presented in the literature. Chapter 5 describes the simulation work that was done to explore the effect of stress on GaN-based HEMTs, which among other things, could possibly lead to eventually fabricating of an enhancementmode device in future. Chapter 6 concludes this thesis and suggests future research directions. 8 Chapter 2 Theory of GaN-based Heterojunction Structures and Devices In order to gain useful insights in the work performed here, it is essential to first have a good understanding of the GaN material as well as phenomena that are observed in GaN-based heterostructures. 2.1 GaN Crystalline Structure It is not the scope of this thesis to present an extensive description of the GaN crystal structure. However, to achieve a meaningful discussion in this work, a concise understanding of the GaN crystalline structure is necessary. GaN can exist in three different crystalline structures, namely, wurtzite, zincblende and rocksalt structures. The wurtzite structure is thermodynamically most stable for bulk GaN and is shown in a stick and ball representation in Figure 2.1. Figure 2.1. A wurtzite structure of GaN crystal (Ga-faced) and its various planes [20]. 9 The c-plane is the most common plane that GaN-based devices are built on, due to its polar nature and existence of the strongest polarisation effect in that plane. The direction that is perpendicular to the c-plane is known as the c-direction and is also known as the (0001) direction. In this thesis, all the GaN-based crystal structure used in devices is of the wurtzite structure configuration. 2.2 Polarisation effect in AlGaN/GaN Heterostructure Polarisation effects in crystalline structure had long been observed in GaN or in wurtzite structure due to the non-centro-symmtrical structure. However it was R. D. King-Smith’s theoretical calculations [21] that provided detail study of these polarisation effects quantitatively, especially those in GaN-based heterostructure. It is this polarisation effect that allows the GaN-based HFET to be fabricated with nominally intrinsic layers in its heterostructure, i.e. without any deliberate doping. However, this brings about the debate of where the carriers that are present at the interface of these devices come from, given the intrinsic nature of its heterostructure layers. Observations of the 2DEG density having a close dependence on the thickness and composition of the AlGaN barrier layer has led many to believe that these carriers may originate from the surface donor states of the AlGaN surface. It is useful to note that 10 these polarisation effects alone do not cause the formation of the 2DEG [1]. Instead, it influences the concentration and distribution of these carriers [22]. There are fundamentally two kinds of polarisation effects that exist in a GaN-based heterostructure; namely, spontaneous polarisation and piezoelectric polarisation. These will be discussed in detail in the following sub-sections. 2.2.1 Spontaneous Polarisation Polarisation is dependent on the polarity of the crystal structure. This is especially so for spontaneous polarisation (polarisation at zero strain), which is primarily due to bonds between the cation (Ga) site and the anion (N) site along the c-direction (0001) in a GaN crystal structure (Figure 2.2) being non-centro-symmetric in structure [23]. (0001) Figure 2.2. A Wurtzite crystal of GaN (N-face) with lattice constants c and a [9]. 11 Figure 2.3. The GaN crystal is often represented by the tetrahedral stick and ball figure - P0 refers to the polarisation vector in the structure [10]. It is beyond the scope of this thesis to fully discuss polarisation charges in the extensive manner, which is presented in [24] [25], [21]. However, it is possible to adopt a simplified understanding that allows for a comprehensive calculation of relevant charges that are induced by these polarisation effects. The polarisation vector in a GaN crystal can be clearly illustrated by the tetrahedral stick and ball figure as shown in Figure 2.2. The directions of the polarisation in the structure are defined as such due to the electron clouds being closer to the N atoms [10]. This difference in electronegativity together with the non-centro-symmetrical structure causes a polarisation dipole to exist between the cation (Ga) site and anion (N) site in the GaN stick and ball model shown in Figure 2.3. The horizontal component of the polarisation is usually assumed to have cancelled each other out. It 12 is useful to note that in the discussion of spontaneous polarisation, the vertical component of the polarisation (under no strain) in the three diagonal bonds have been taken into account. The polarisation dipole itself would not have constituted a polarisation charge existing at the interface of the heterojunction. Instead it is the difference in polarisation across the interface that would result in a polarisation charge at this heterointerface. Depending on the composition of the adjacent layers that are deposited, the difference in electronegativity across the heterointerfaces can be very different, thus resulting in different polarisation. This difference in polarisation between two nitride semiconductors will manifest itself as a polarisation charge across the heterointerface. Figure 2.4. A representation of the polarisation profile of a nitride-based semiconductor heterostructure [10]. 13 The polarisation charges due to spontaneous polarisation are not always well-defined as it requires the polarisation between two phases to be connected by a pseudomorphic boundary. Such a transition between two phases can be found in GaN-based heterojunctions. For example (Figure 2.4), another nitride-based semiconductor, an AlN layer, is grown pseudomorphically on GaN to form such a heterojunction. The resulting polarisation induced charge, governed by Gauss’s Law [22], can then be given by , where ( 2.1 ) refers to the gradient of polarisation in space, i.e. difference in polarisation across the heterointerface. Spontaneous polarisation in various nitride-based semiconductors can be easily calculated by making use of a Vegard-like rule. The use of Vegard’s Law in polarisation is a valid estimation as shown in [26]; this includes ternary or quaternary nitride alloys. In quaternary nitrides, Vegard’s interpolation would be estimated by, ( ( ) ( ) ) ( ) ( ( 2.2 ) ) ( ). This equation can also be loosely represented by Figure 2.5. 14 Figure 2.5. A graphical representation of the spontaneous polarisation in nitride-based alloys according to Vegard's Law interpolation [26]. 2.2.2 Piezoelectric Polarisation Spontaneous polarisation is also commonly known as the polarisation that exists without strain. However, in nitride-based heterostructures, there is rarely a case of zero strain. The difference in lattice constant (Figure 2.5) or a difference in thermal coefficient of expansion between the GaN layer and AlGaN layer would give rise to either a compressive or tensile strain to be present in the epitaxial layers that are grown. Due to the non-centro-symmetrical nature of nitride-based crystal structure, this stress would alter the polarisation due to the non-vertical triple bonds that exist in these nitride-based crystal structures. To illustrate this point more clearly, it is useful to consider a perfect tetrahedral stick and ball figure of GaN (Figure 2.6). 15 Figure 2.6. The tetrahedral stick and ball representation of GaN undergoing tensile strain [10]. When the GaN layer undergoes a tensile strain, there is a reduction of the vertical polarisation component from the three diagonal bonds and thus it would represent a change of polarisation. This difference in polarisation would then result in a polarisation charge which is confined to the interface of the heterojunction. Unlike the spontaneous polarisation where the polarisation is dependent solely on the alloy type and composition of the alloy, piezoelectric polarisation would require more information on different parameters to determine its resulting polarisation. These parameters would include strain, piezoelectric coefficients and elastic constants, all of which might be directly or indirectly affected by the composition of nitride alloys. Theoretical calculations of both the spontaneous and piezoelectric polarisation and its induced charges will be elaborated in Chapter 4 where such values will be used for simulation purposes. 16 2.3 High Electron Mobility Transistor After a discussion of the various polarisation effects, it is appropriate that the discussion extends to the kind of devices that would utilise the benefits of such polarisation charges that are present in a heterojunction. As mentioned previously, the MODFET was first conceived to make use of the heterojunction characteristics. The MODFET was more commonly a GaAs-based device. However, GaAs has very weak polarisation effect compared to GaN and thus modulation doping was the defining factor for the GaAs MODFET. When the polarisation factor in GaN was discovered, people started to pay more attention to the heterojunction field effect transistor (HFET) as a general class of devices. Also known as the High Electron Mobility Transistor (HEMT), the ability to induce a conductive 2 DEG in intrinsic GaN heterostructure layers of the device has ignited interest of many people. In the rest of this thesis, we will be working on the AlGaN/GaN HEMT structure that is currently the de facto norm for GaN-based HEMTs. The High Electron Mobility Transistor (HEMT) presents a few advantages over the usual Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). In the HEMT structure, the conduction band offset due to the heterojunction causes a triangular quantum well to form just after the GaN/AlGaN interface (Figure 2.7). Carriers that originate from surface donor states of the AlGaN surface [1] are thus confined in this 17 quantum well. The buried 2-DEG channel eliminates the effect of impurity scattering due to absence of dopants in the channel, thus allowing for an enhancement in the mobility of such a device. 2.4 Metal-Oxide-Semiconductor High Electron Mobility Transistor The HEMT structure may be the choice device for GaN-based transistors. However, like most devices, it is not without its own unique problems. It is observed that the HEMT structure is similar to a MESFET structure where the Schottky gate is in contact directly with the semiconductor. This inherently causes a problem of a relatively high gate leakage current. A device without a gate dielectric would also prove to be more susceptible to breakdown as compared to the MOSFET. In addition, the HEMT, also tends to experience a phenomenon known as current collapse. Current collapse is the reduction of drain current after certain conditions that a transistor is subjected to. It is commonly seen when a GaN-based transistor is subjected to a high drain-source bias. This could also lead to an increase in knee voltage [61]. 18 AlxGa1-xN GaN Triangular Quantum Well Figure 2.7. The energy band diagram of AlGaN/GaN Heterojunction. Current collapse could be caused by a few possible reasons: 1) deep levels in the barrier layer under the metal gate, 2) deep levels in the interface and/or in the buffer layer, and 3) surface states [27]. The effect is notably caused by electrons being trapped by these traps that reside in the area between the drain and the gate during high voltage operations. This induces a virtual gate formation between the drain and the gate, thus causing the phenomenon of drain current reduction. In order to overcome these challenges, a gate dielectric is inserted between the gate metal and the AlGaN layer. This addition of the gate dielectric in the structure gives rise to a structure known as the Metal-Oxide-Semiconductor High Electron Mobility Transistor (MOSHEMT) as shown in Figure 2.8. 19 Figure 2.8. A typical illustration of a Metal-Oxide-Semiconductor High Electron Mobility Transistor. The MOSHEMT structure is able to effectively reduce gate leakage current and in thus improving the drive current capacity. In addition, the way the gate dielectric is deposited allows the surface traps to be partially passivated to reduce the effect of current collapse. In this thesis, the MOSHEMT structure is the dominant structure that is being used for various studies. The details on the various materials used as well as composition of the various alloys will be discussed in detail in the chapters that follow. 20 Chapter 3 Device Fabrication and Characterisation This chapter documents results of the design fabrication and characterisation of AlGaN/GaN MOSHEMTs. Before the fabrication process is presented, a discussion of the various considerations in the design of the device and other test structures is done. The fabrication of the device is then described followed by the characterisation techniques. Characterisation of AlGaN/GaN MOSHEMTs was performed in order to study the effect of different techniques in fabrication, such as device passivation and deposition of Diamond-Like Carbon (DLC) stress liner. Device fabrication and characterisation was a collaborative work with graduate students Liu Xinke and Liu Bin. While the author’s main contribution in this project is the mask design and certain lithography steps, the author would like to acknowledge Liu Xinke’s contribution in the fabrication process particularly in development of mesa etching process, gate stack formation process, surface passivation process and the contact formation process. The author would also like to acknowledge the contribution of Liu Bin in the development of the DLC deposition process. 3.1 Mask Design Several mask set designs were fabricated in the course of this work. There were a few basic considerations that require close attention in order to design a useful and functional mask set. Figure 3.1a shows a typical device design used for DC device characterisation. 21 b) a) Gate Gate Width Drain Source Figure 3.1. a) A typical transistor design for the purpose of DC characterisation. W, L and LD-G referred to the gate width, gate length and drain-gate separation respectively. b) The width of a mesa island would dictate the gate width of a transistor. 3.1.1 Mesa Isolation The formation of the mesa is an important step that requires several considerations. The mesa isolation defines the gate width (Figure 3.1b) as well as the external resistance of the device. 3.1.2 Source-Gate/Drain-Gate Separation Apart from having a variety of devices with different gate dimensions such as gate length and gate width, one of the factors that has to be taken into account for this mask set was the Source-Gate (LS-G) and Drain-Gate (LD-G) separation. The device design or layout depends on the application. For high power or high voltage application, the separation between the drain and gate is an important parameter. In high voltage 22 applications, the drain voltage can be very high, e.g. 500 V. On the contrary, the gate voltage would be relatively lower, e.g. 5 V. The potential difference between the gate and drain would give rise to a very high electric field which could cause the device to breakdown. In order to reduce this electric field between the gate and drain, it would be useful to increase the Drain-Gate separation. However, an increase in this length would also result in an increase in extrinsic series resistance. Thus, it would be necessary to optimise this separation. 3.1.3 Other Test Structures Apart from the devices that are being designed on the mask set, it is useful to have an assortment of test structures in the same die. These structures are important in process debugging as well as characterization of various device or material parameters. 100um Figure 3.2. The design of a Van Der Pauw Structure in this mask set design. 23 3.1.3.1 Van der Pauw Structure The Van Der Pauw Structure (Figure3.2) allows for the characterisation of the electron mobility using the principles of the Hall Effect [28]. In the case of the GaN-based HEMT structure, the drive current would be linearly dependent on the electron mobility, in addition to the electron density in the 2DEG. 3.1.3.2 Vernier Alignment Scale Structure Misalignment of the various mask layers during fabrication could be an issue if the magnitude of misalignment is beyond tolerance. This could cause a device to fail due to a short circuit or an open circuit depending on the direction and magnitude of the misalignment. The Vernier Alignment Scale (Figure 3.3) structure allows for a quick and effective evaluation of the degree of misalignment between two layers. Figure 3.3. The design of the Vernier Alignment Scale Structure used in this mask set design. 24 3.1.3.3 Transmission Line Model (TLM) Structure The Transmission Line Method is a common method used to determine contact resistance which can be also used to calculate the sheet resistance, specific contact resistance as well as the transfer length [29],[30]. The TLM structure consists of an active region (mesa) with metal contacts placed at positions spaced apart at different distances as shown in Figure 3.4. In order to obtain the contact resistance, the resistance between two pads at each separation distance are measured by a simple I-V measurement. After all the resistances are measured, the data is used to plot a resistance versus contact spacing graph, as shown in Figure 3.5. The intercept on the Y axis (Total Resistance) would give the value of two times of the contact resistance (2 Rc) while the intercept of the X axis would provide the value of two times the transfer length (2 LT). 100um Figure 3.4. The design of the Transmission Line Model (TLM) Structure used in this mask set design. 25 Total resitance RT) 1600 1400 1200 1000 800 600 400 -100 0 100 200 300 400 Contact Spacing d (m) 500 Figure 3.5. An example of a typical Resistance vs. Contact spacing plot extracted from TLM measurement. The sheet resistance and specific contact resistance can then be calculated by equation (3.1) and (3.2) respectively; ( 3.1 ) ( 3.2 ) where W is the width of the contact pads on the TLM structure. 3.1.3.4 Step Coverage Structure It is observed, in the device design, that there are several process steps in the fabrication that would require deposition of materials over an etched step. This is clearly illustrated at the step where Tantalum Nitride (TaN, material for the metal gate) is deposited over an island after the mesa isolation etching, as shown in Figure 3.6. 26 Gate Metal Mesa Isolation Gate Dielectric Figure 3.6. An 3D illustration of the gate metal being deposited over a step of the mesa island. A break in the gate metal could occur if the etched depth of the mesa isolation is too deep. This breakage can be difficult to detect through the optical microscope. The step coverage structure (Figure 3.7) was design to effectively determine if there is any discontinuity in the gate metal deposition. 100um Figure 3.7. The design of the step coverage test structure used in this mask set design. 27 The thin green lines are representation of the gates with various gate lengths while the red boxes are the mesa isolations. If there is any discontinuity in the gate metal deposition, a simple I-V measurement across the two corresponding pads would show a high resistance reading. 3.1.3.5 Long Gate Width Device Structure GaN-base devices are most often used for high power applications. In such high power applications, the devices are usually designed with very long gate width, in an interdigitated structure. In order to have an indication of the device performance with long gate width, this device design (Figure 3.8) was included as a test structure. This device structure would give a gate width of approximately 3.05 mm. 100um Gate Drain Source Figure 3.8. The design of the long gate width transistor design. 28 After ascertaining that all the test structures are compatible with the device fabrication process, the design was sent out for the fabrication of the mask set. 3.2 Device Fabrication Procedure The fabrication process of the test devices will be discussed in this section. The fabrication process starts with blank wafers shown in Figure 3.9. The thickness of the intrinsic GaN layer is usually between 1-5 µm, while the thickness of the AlGaN layer is in the range of 5-30 nm. This thickness depends on the application of the devices and thus different layer engineering would cater to different applications. The aluminium mole concentration of the AlGaN is 0.25 in our experiments and simulations. In this work, the AlGaN layer is 20 nm thick while the GaN layer is 2 µm thick. A summary of the fabrication process is shown in Figure 3.10. Figure 3.9. The starting layer structure of HEMT wafer before the fabrication process. 29 Figure 3.10. The fabrication process of AlGaN/GaN MOSHEMT [31]. The AlGaN/GaN epitaxial wafer was subjected to a round of lithography and Cl2based reactive ion etching (RIE) to form the mesa isolation. After the active region was formed, the wafer was subjected to pre-gate cleaning. The wafer was washed using HCl to remove any native oxide, followed by a dip in (NH4)2S as an ex-situ surface passivation process. After the pre-gate cleaning, the wafer was loaded into a Metal Organic Chemical Vapour Deposition (MOCVD) multi-chamber gate cluster system. In one of the chambers, in-situ passivation was performed [32]. The wafer was baked in the MOCVD chamber at a temperature of 300 °C under high vacuum (~1×10-6 Torr) (Vacuum Annealing). This would decompose any remaining native oxide that might be left over during the pre-gate cleaning process. A silane (SiH4) treatment at a temperature of 400 °C for 1 minute at a pressure of 5 Torr was performed, for the 30 purpose of surface passivation. The flow rates of SiH4 and N2 were 60 and 250 sccm respectively. High-k dielectric (either Aluminium Oxide (Al2O3) or Hafnium Aluminium Oxide (HfAlO)) was then deposited on the wafer without breaking vacuum. A Post Deposition Anneal (PDA) was then performed to improve the quality of the high-k dielectric film. This PDA was performed at 500 °C in N2 ambient for 60 s. TaN was then sputtered on the wafer, followed by a photolithography step to define the gate pattern by plasma etching while wet etching (in dilute HF) was done to remove the HfAlO in source/drain regions. Ohmic contacts were then formed by depositing a layer of Titanium (30 nm) followed by a layer of Aluminium (70 nm) which were patterned by a lift-off process. Finally an alloying process was carried out to complete the process of the ohmic contact formation. This was done at a temperature of 650 °C in N2 ambient for a period of 30 s. The resulting structure is shown in Figure 3.11. 31 20nm 2µm Figure 3.11. An illustration of the device schematic of a completed AlGaN/GaN MOSHEMT. After the alloying process, the baseline structure is completed and ready for characterization. In order to study the effect of stress on these GaN-based MOSHEMT structures, a layer of Diamond-like Carbon (DLC), 40 nm thick, was deposited using a Filtered Cathodic Arc (FCA) System on some of the devices. A lift-off process was done to define the pattern of the DLC layer. Characterization was performed mainly on three sets of devices. These three sets of devices are: 1) Devices with no surface passivation (which will act as control samples), 2) Devices with surface passivation and 3) Devices with surface passivation and DLC layer. The final structure with DLC liner layer is shown in Figure 3.12. The effect of these differences in fabrication steps on the device performance will be discussed in the following sections. 32 20nm 2µm Figure 3.12. An illustration of the device schematic of an AlGaN/GaN MOSHEMT with a DLC stress liner. 3.2.1 Surface Passivation Surface passivation is one of the most important steps in modern device fabrication. Even in silicon-based devices, surface treatment is important in passivating the dangling bonds at interfaces. Without surface passivation, these traps will trap carriers during operations and cause undesirable effects such as the reduction in drive current as well as threshold voltage (Vth) shift [33]. Surface passivation studies of Gallium Arsenide (GaAs) [34] provided an important guide to the surface passivation studies of GaN as both are Gallium-based material. In [34], a SiH4 and Ammonia surface passivation technique was used to improve the 33 interface of GaAs-based device. However, it was found in [32] that Ammonia was not beneficial to the purpose of surface passivation in GaN, thus only Vacuum Annealing and SiH4 treatment was used for surface passivation of GaN-based devices. GaN MOSHEMTs that were subjected to Vacuum Annealing (VA) at 300 °C and SiH4 treatment at 400 °C. These treatments effectively decompose any native oxide and passivate any dangling bonds or any other kind of defects that may manifest as interface states at the interface between the high-k dielectric (HfAlO) and the AlGaN barrier layer [32]. This work sets out to characterise two groups of samples: 1) devices with no surface passivation (control samples) and 2) device with the above mentioned passivation process. Results of electrical measurements will be compared and a short discussion will follow. The passivation studies were performed on long channel devices thus the gate length of the devices characterised for this study is 2 µm. 3.2.2 Diamond-like Carbon (DLC) Layer Previous studies had shown that stress would affect the device performance of AlGaN/GaN HEMTs [35, 36]. Due to the difference in lattice constants between the AlGaN layer and the GaN buffer layer, intrinsic tensile stress exists in the AlGaN layer. This intrinsic tensile stress causes an increase in 2DEG concentration due to a change in piezoelectric polarisation across the heterojunction as discussed in chapter 2. 34 In [36], additional tensile stress was induced by inducing a mechanical stress on the device. This additional tensile stress increases the piezoelectric polarisation and thus the 2DEG concentration increases accordingly. This increase in 2DEG concentration improves the conductivity of the channel and enhances the DC performance of the transistor. However, an increase in the 2DEG concentration degraded the transient performance in [36] and this was attributed to the increase in electron density due to increase in piezoelectric polarisation. This would result in a more negative threshold voltage. Thus, in order to fabricate an AlGaN/GaN enhancement mode transistor, one should reduce the 2DEG concentration with a trade-off of a lower conductivity [35]. DLC was first deposited on p-channel silicon transistors to induce a high compressive stress on the channel so as to improve the performance of these transistors [37]. In the fabrication process of the AlGaN/GaN MOSHEMT described in the previous section [38], it was mentioned that a layer of DLC was deposited to induce stress on the device (Figure 3.12). DLC, with an intrinsic stress of 6 GPa [37], would be effective at providing a compressive stress in the AlGaN/GaN transistor. This compressive stress would effectively reduce the intrinsic tensile stress present due to the lattice constant difference between AlGaN and GaN. A reduction in the intrinsic tensile stress would reduce the piezoelectric polarisation in the structure and thus reduce the 2DEG concentration. This could be beneficial in the objective of achieving an enhancement mode device [31]. 35 Devices with and without DLC layers will be subjected to DC characterization to study the effect of such a DLC liner. In order to maintain consistency in the experiment, these two groups of devices will be put through the same surface passivation process mentioned previously. It was observed that the effect of a 40nm DLC stress liner had greater effect on short channel devices as the average stress induced on the 2DEG is generally greater for devices with shorter channels [31]. The average stress was simulated using Abaqus simulation suite and the result is shown in Figure 3.13. This Abaqus simulation was Average Channel Stress (MPa) done by Liu Bin. -200 -300 -400 -500 -600 -700 -800 -900 300 400 500 600 Gate Length LG (nm) 700 Figure 3.13. The average compressive stress induced in the channel due to 40 nm DLC simulated for various LG: 300 nm, 500 nm and 700 nm [31]. 36 In view of the effect of the DLC liner on short channel devices, the study on DLC deposition on AlGaN/GaN MOSHEMT was done primarily on short channel devices. The characterised devices in this work have a gate length of 300nm. 3.3 Electrical Characterisations of the MOSHEMTs A few typical electrical characterization techniques were used to characterise the performance of the devices. The results of the characterisation are presented in the following section. The layer structure and fabrication details are the same in all devices as described in section 3.2. 37 Effect of Surface Passivation on the ID-VGS Characteristics Drain Current ID (A/mm) 2 10 1 10 0 10 -1 10 -2 10 -3 10 -4 10 -5 10 -6 10 250 Device without passivation Device with passivation VD = 5 V 200 150 VD = 1 V 100 50 -8 -6 -4 -2 0 2 Gate Voltage VG (V) 4 0 Transconductance gm (mS/mm) 3.3.1 Figure 3.14. The effect of the surface passivation technique on the ID-VGS plot of MOSHEMTs with LG = 2 µm. Incorporation of In situ SiH4 passivation improved subthreshold swing to 100 mV/decade and gm of 95 mS/mm [31]. The VA and SiH4 surface passivation techniques are expected to remove any native oxide present on the AlGaN surface as well as passivate the interface states that exist between the AlGaN layer and the HfAlO high-k dielectric layer. Figure 3.14 shows the effect of the surface passivation on the ID-VGS plot of the device with a gate length of 2 µm. The surface treatment reduces the off-state leakage current by about 2 orders of magnitude. Due to the reduction in off-state leakage current and the increase in onstate current, the Ion/Ioff ratio sees an improvement of about 2 orders. In addition to the reduced off-state leakage, the sub-threshold swing is also improved from 150 38 mV/decade to less than 100 mV/decade. This improvement could be due to the suppression of trap-assisted tunneling current through the high-k dielectric which has effectively passivated the interface states. The threshold voltage moves towards a slightly more negative value as the improved interface might have resulted in a higher 2DEG density. 3.3.2 Effect of Surface Passivation on ID-VDS Plot It is observed in the previous section that surface treatment reduces the off-state leakage current, increases the on-state drain current and improves the sub-threshold (SS) in general. That effect is also seen in the ID-VDS plot of the device with gate Drain Current ID (mA/mm) length of 2 µm, as shown in Figure 3.15. 900 Device without passivation Device with passivation 750 VG,max = 4 V, Step = - 1 V 600 450 300 150 0 0 2 4 6 8 10 12 Drain Voltage VD (V) 14 Figure 3.15. The effect of surface passivation on ID-VDS plot of MOSHEMT with LG = 2 µm. ID,sat of 624 mA/mm measured at VD = 10 V and VG = 4 V was observed. 39 From Figure 3.15, it is observed that the saturation drain current experience a 53% enhancement for devices with in situ VA and SiH4 treatment as compared to the control device. The drain current enhancement was taken at VGS - VT = 7 V and VD = 15 V. This result is consistent with what that obtained in the ID-VGS plot and the surface passivation proves to be an effective technique in enhancing the performance of AlGaN/GaN MOSHEMTs. 3.3.3 Effect of DLC Liner on C-V characteristics Capacitance C (pF) 120 Control Device with DLC 100 80 60 40 20 0 -8 -7 -6 -5 -4 -3 -2 Gate Voltage VG (V) -1 0 Figure 3.16. The C-V characteristics of a control device and the device with 40 nm DLC liner deposited on a MOSHEMT with LG = 300nm. 40 The capacitance of a device is defined as (3.3) where dQ is the magnitude of the change in charge stored in a capacitor as a function of dV, the change in bias across the capacitor [39]. By integrating the C-V plot, we are able to determine the charge induced under the gate over a fixed range of sweep of the bias voltages. Figure 3.16 presents the C-V characteristics of the control AlGaN/GaN MOSHEMT and one with a 40 nm of DLC liner, both with gate lengths of 300 nm. It is observed that there is a distinct change in 2DEG concentration, where the density of the 2DEG in the device with the DLC liner is reduced from 1.04×1013 cm-2 to 8.97×1012 cm-2. This reduction in 2DEG density might have effectively caused the threshold voltage to become more positive, and thus the application of a DLC liner to the MOSHEMT is an effective way in working towards the achieving of an enhancement mode device. More details on the threshold voltage will be discussed in the next section. 3.3.4 Effect of DLC liner on the ID-VGS Characteristics The DLC liner was meant to be a stressor to induce compressive stress in the channel region. This compressive stress should relieve some of the intrinsic tensile stress in the AlGaN layer and thus reduce the piezoelectric polarisation in the heterostructure. The effect of this stress liner on the ID-VGS plot of the device with gate length of 300nm is shown in Figure 3.17. 41 Drain Current ID (A/mm) 250 Control Device with DLC 0 10 200 -1 10 150 -2 10 VD = 5 V -3 10 VD = 1 V 100 -4 10 50 -5 10 -6 10 -8 -6 -4 -2 0 Gate Voltage VG (V) 2 4 0 Transconductance gm (mS/mm) 1 10 Figure 3.17. The effect of the DLC stress liner (Compressive Stress) on the ID-VGS charactieristics of a MOSHEMT with LG = 300 nm. Low SS of 110 mV/decade and high gm of 88 mS/mm were achieved for the device with DLC liner [31]. The DLC compressive stress liner has caused the threshold voltage to shift from -5.2V to -4.5V. In addition, the on-state current is observed to have increased. The shift in threshold voltage is consistent with the C-V measurement which suggests that there is a reduction in 2DEG density. It is observed that a low SS is attainable for this device (110mV/decade), thus it causes no degradation to the sub-threshold performance. The increase in on-state current could be due to the coupled tensile stress that is experienced in the contact regions. This issue would be further investigated in the following chapters. 42 Effect of DLC compressive stress liner on the ID-VDS Characteristic Drain Current ID (mA/mm) 3.3.5 900 Control Device with DLC 750 L = 0.3 m, V = 4 V, Step = -2 V G G,max 600 450 300 150 0 0 2 4 6 8 10 12 Drain Voltage VD (V) 14 Figure 3.18. The effect of the DLC Stress liner (Compressive Stress) on the ID-VDS characteristic with LG = 300 nm [31]. The main objective of depositing DLC liner was to attempt to achieve an enhancement mode device and an enhancement in drive current was not expected. However, in the ID-VGS plot, it was observed that there was a slight enhancement in the on-state current. The ID-VDS plot of the same device with a gate length of 300 nm (Figure 3.18) provides further verification that there is enhancement in transistor performance and this could be due to the coupled tensile stress experienced in the contact region as mention above. A 36% enhancement of saturation drain current is observed for the device with a DLC liner as compared to the control device at (VGS - VT) = 6 V and a drain voltage VD of 12 V. 43 From the observations in the electrical characterisation of these experimental devices, it is observed that the surface passivation process would lead to an enhancement in drive current as well as an improved sub-threshold swing. However, the impact on the threshold voltage observed in the ID-VGS plot is not as significant. On the other hand, the presence of a DLC stress liner caused a positive shift in threshold voltage as well as an enhancement in the drive current. The solution to an enhancement device is not single-fold. It would require a multi-fold solution whereby DLC is one of the many possible solutions that could lead to an enhancement operation device. In order to gain a better understanding of the mechanisms that lead to these changes and improvement in device characteristics, device simulations would be useful and would validate the experimental observations. 44 Chapter 4 Numerical Simulation Fundamentals In this chapter, the underlying physics of the phenomena observed in the experimental AlGaN/GaN MOSHEMTs will be studied device simulation. Through device simulation, certain internal device variables which cannot be observed directly from device terminal I-V measurements such as the 2DEG density, energy band diagrams, etc., can be observed clearly. It is thus useful to make use of device simulation to study the different splits of experiments on the AlGaN/GaN MOSHEMT. In this work, a commercial numerical simulation software, Synopsys® Sentaurus TCAD, was used to study the effect of various conditions that might affect the performance of an AlGaN/GaN MOSHEMT. 4.1 Simulation Basics Numerical simulations are typically complex mathematical calculations based on several different models that that can be described by mathematical equations. In order to make use of such models one needs to understand how simulation program typically make use of these models on the device. 45 Device Geometry Construction (Sentaurus Structure Editor) Meshing (Sentaurus Mesh) Running of Simulation (Sentaurus Device) View Results (Tecplot SV & Inspect) Figure 4.1. A flowchart showing the process of device simulation (Names in bracket denote name of program used for that purpose). A flowchart of the device simulation process is shown in Figure 4.1. Numerical simulations usually begin with the construction of the device geometry. In Sentaurus TCAD, users can choose to do a device geometry construction using the Graphical User Interface (GUI) or a batch code scripting scheme (i.e. programming) to do the construction. This process is done in a program in the Sentaurus TCAD suite known as the Sentaurus Structure Editor. This editor is capable of 1D, 2D and 3D structure construction. However, only 2D construction will be implemented in this work as it is sufficient for this study due to the fact that the AlGaN/GaN MOSHEMT is a planar device. 46 Apart from the geometry construction, other parameters such as doping profiles, alloy composition, boundary conditions and definition of meshing grids must be specified at this stage of the device construction. Boundary conditions would dictate how a particular model will behave at the boundaries of different regions of the device. For these models to be applied to the mathematical equations that describe the physical behaviour of the device, meshing of the device needs to be performed. Meshing refers to the process whereby the differential equations governing the operation of a device are approximated by a set of difference equations by dividing the device into a large number of discrete elements. The carrier distribution and electric potential of each element is described by a set of difference equations based on the models chosen to describe the operation of the device. These equations (together with the boundary conditions) are then solved iteratively to find the potential, carrier concentration and other parameters in each element. The meshing definition is done in Sentaurus Structure Editor, but the meshing process is performed by a sub-program known as Sentaurus Mesh. A numerical solver is then used to solve these equations and in the Sentaurus suite, this solver is known as Sentaurus Device. 47 Figure 4.2. An example of a Meshing Strategy for a 2D device in Sentaurus simulation program [7]. The meshing of the device need not be uniform throughout the entire device as there might be regions that are more important than others, such as the channel or interface region. These are regions where rapid changes of the carrier concentration or potential are experienced. Different meshing strategies can then be used to describe the device to optimise the simulation process while ensuring accuracy. An example of a meshed device is shown in Figure 4.2. It is observed in Figure 4.2 that the channel region and interfaces between various regions are more tightly meshed as mentioned previously. 48 4.1.1 Device Structure 300 nm 500 nm 500 nm 20 nm x y Figure 4.3. The schematic diagram of the simulated structure in Sentaurus TCAD. The device structure simulated in this work is designed to match the actual device fabricated in the first part of the project as closely as possible. As such, the same layer structure is specified in the device simulated. The X-Y axis in Figure 4.3 is the reference frame that is used to refer to the device geometry in this thesis. The Y = 0 line refers to the interface between the AlGaN and GaN layer. The X = 0 line refers to the centre of the device (i.e. centre of the gate). The actual device shown in Figure 3.11 featured a sapphire substrate. In the simulated structure (Figure 4.3), the substrate has been omitted. This will not only simplify the construction process of the simulation structure, but will also reduce the duration of the simulation process. This omission would not have a major impact on the results as the boundary condition at the bottom of the simulated structure is an insulating 49 boundary; which is consistent with the sapphire substrate being an insulator. A few other factors were taken into consideration during the construction of the device structure. The considerations are discussed in the sections below. Source/Drain region The actual size of the source and drain contact regions is in the range of tens of microns. However it would be impractical to simulate a device with a 50µm source and drain region as that would require a very long time for the simulation process to complete. In order to reduce the simulation duration but still maintain the accuracy of the simulation, the length of the source/drain region was set at a length of 5µm. It would be reasonable to make such a simplification as practically all the drain and source currents will flow into or out of the 5 um regions only. Therefore the remaining part of the drain and source contacts can be omitted. In the experimental device, the contacts need to be larger so that they can be probed during characterisation process. In this simulation work, the effect of changing the LS-G and LD-G is not studied, thus the two lengths were set to be the same as the basic design of the fabricated devices. In this case, LS-G and LD-G were both set at 500 nm. The device structure was specified with ohmic contacts in the drain and source regions with a contact resistance (RC) of 100Ω. The contact resistance in the fabricated device had values in that range and thus the simulated device was given this value. 50 Gate Region In the previous section, characterisation was done on experimental devices with gate lengths of 2 µm and 300 nm. In order to maintain consistency of the simulation and to allow comparisons to be made, the simulated gate lengths were specified to be in that range as well. In the fabrication process, Tantalum Nitride (TaN) was the metal used for the metal gate. In the simulation, it is not necessary to define the material used for the gate. However, it is necessary to define the workfunction of the metal used for the gate. Thus the workfunction for the gate in this simulation work has been defined to be 4.4 eV which is the value of the workfunction of TaN in literature. Definition of the Induced Polarisation Charge In Chapter 2, the polarisation effect of the AlGaN/GaN heterostructure was discussed. It was evident that this polarisation, though not the sole factor, was one of the more important factors in the formation of the 2DEG. It is thus important that such an effect is accurately accounted for in the device simulations. In order to accurately represent this induced polarisation charge in the various interfaces that might experience this polarisation effect, the polarisation charge is calculated according to [22] and input into the simulation accordingly. Two important interfaces are identified as being the ones that have dominant effect on the 2DEG density. They are the interface between the AlGaN layer and the GaN layer and the 51 interface between the high-k dielectric and the AlGaN layer. One can refer to Figure 4.4 to better understand where these interfaces are. The GaN layer is much thicker than the AlGaN layer and thus it is assumed to be totally relaxed, thus only spontaneous polarisation exists in the GaN layer. Figure 4.4. An illustration of the interfaces with its polarisation and the respective induced polarisation charges. This section will describe the various equations that are used to quantify the polarisation effect so that they can be used to calculate the effective induced sheet charges [10, 22, 23]. Piezoelectric polarisation induced along the c-axis can be described by equation (4.1) ( where ), (4.1) is the strain along the c-axis, and is represented by equation (4.2) ( In equation (4.1), and ) (4.2) are the in-plane strain and are assume to be equal, represented by equation (4.3) 52 ( ) (4.3) where e33 and e31 are the piezoelectric coefficients while a and c are the lattice constants of the strained layer. Table III. A comparison of the lattice constants, spontaneous and piezoelectric constants/coefficients of GaN and AlN [6]. Coefficient/Constant AlN GaN a0 (Å) 3.112 3.189 c0 (Å) 4.982 5.185 PSP (C/m2) -0.081 -0.029 e33 (C/m2) 1.46 0.73 e31 (C/m2) -0.60 -0.49 The relationship between lattice constants in the Wurtzite AlGaN structure is given by ( ( ) ) (4.4) where C13 and C33 are elastic constants. A list of the coefficient values can be found in Table III. Combining equations (4.1) to (4.4), an equation for piezoelectric polarisation as a function of lattice constant is obtained in equation (4.5), ( ) ( ) (4.5) The list of coefficients and constants given in Table III are for the binary nitrides of GaN and AlN. In order to obtain the coefficients and constants for AlxGa1-xN, 53 Vegard’s Law is extended here to interpolate the necessary values. For example, the e33 and e31 piezoelectric coefficients of AlGaN can be obtained by equation (4.6), [ ( ) ( ( )] ) (4.6) This extrapolation is only valid for a small amount of strain as determined in [40]. As the strain increases, the piezoelectric coefficient might be significantly affected by the internal strain component. The elastic constants C13 and C33, on the other hand, can be calculated [22] by, ( ) ( ( ) ( ) (4.7) ) (4.8) The non-strained lattice constant of AlGaN can also be calculated using Vegard’s Law interpolation. The spontaneous polarisation has been determined experimentally by [6] and can be described by equation (4.9), ( ) (4.9) With equation (4.5) and (4.9), we will be able to obtain the piezoelectric and spontaneous polarisations of different regions of the structure. The polarisation induced charges are associated with the gradient of the polarisation in space as governed by Gauss’s Law, given by equation (4.10), (4.10) Assuming these interfaces are abrupt and thus the change of polarisation across the heterostructure is abrupt, the resulting gradient of polarisation would simply be the 54 difference of the polarisations across the interface. Thus the polarisation induced charge density can be described by ( ) ( ) (4.11) where P is the total polarisation (i.e. spontaneous and piezoelectric). The value of the induced bound sheet charge can thus be obtained by dividing equation (4.11) by the value of electronic charge, q. The calculated values of these induced sheet charges are -3.13841×1013 C/cm2 (High-k/AlGaN interface) and 1.328115×1013 C/cm2 (AlGaN/GaN interface). Specification of Interface and Bulk Traps The immaturity of the III-nitride technology coupled with the lattice mismatch between AlGaN and GaN crystal structure results in a structure where significant amount of structural defects are present [8]. These structural defects would effectively translate into traps. In addition, in [1], donor-like surface states have been identified as a possible source of carriers that form the 2DEG. Thus an accurate trap concentration definition is necessary to ensure an accurate simulation. It is still relatively difficult to characterisation of traps in III-nitrides and there is a paucity of literature describing those traps that are present. From some works, such as [41- 43], the density of the bulk traps in most III-nitride material was found to be in the range of 1015 – 1018 cm-3. In this simulation, the bulk trap density in both AlGaN and GaN was set to 5×1017 cm-3 with a cross section of 1×10-15 cm-2. By taking an 55 average of the values from various literature [41, 43, 44], these traps are positioned at 1eV above mid-gap and are defined to be acceptor-like. The interface states present a more challenging task at hand as these would affect the 2DEG directly according to [1]. It is assumed that the AlGaN/GaN interface does not have any traps and thus the main interface traps would be those at the high-k dielectric/AlGaN interface. References [41- 43] show that interface states are usually in the range of 1012-1013 cm-2 eV-1, thus the concentration of the interface state density specified in this simulation was set at 3.0×1013 cm-2 eV-1 and is set to be donor-like (0.2eV above mid-gap of AlGaN) traps as described in [1]. In [32], it was observed that surface passivation can reduce interface state to a level of 1010 – 1011 cm-2eV-1. This effect would also be simulated in the following chapters. More details of the simulation parameters can be found in Appendix A where the simulation script is also listed in detail. 4.1.2 Carrier Transport The Sentaurus TCAD simulation suite supports several different carrier transport models for semiconductors. They include: 1. Drift – Diffusion Model, 2. Thermodynamic Model, 3. Hydrodynamic Model, 4. Monte Carlo Method. 56 In this work, these models were studied carefully and the Drift –Diffusion model was chosen as it provides relatively fast simulation runs as well as an acceptable level of accuracy. In addition, the temperature effect of the AlGaN/GaN MOSHEMT was not studied in this work, thus the Thermodynamic and Hydrodynamic model were not chosen. Drift Diffusion Model The Drift – Diffusion model is one of the most basic carrier transport model in semiconductor physics. The current densities for electrons and holes are given in equation (4.12) and (4.13), ⃗⃗⃗ , (4.12) ⃗⃗⃗ , (4.13) where µn and µp are the electron and hole mobilities respectively and Φn and Φp are the electron and hole quasi-Fermi potentials respectively [7]. The Poisson equation [equation (4.14)], electron continuity equation [equation (4.15)] and hole continuity equation [equation (4.16)], based on the drift-diffusion model, are numerically solved with the appropriate carrier mobility models in place. These equations are  s.E   s2  q( p  n  N ) , n 1  .J n  (G  R) t q and (4.14) (4.15) 57 p  1  .J p  (G  R) t q . (4.16) In the equations above, E is the electric field vector, εs is the semiconductor permittivity and ψ is the electrostatic potential. The term q(p-n+N) would give the total space charge where n and p are the electron and hole carrier concentrations respectively and N is the electrically active net impurity concentration. The terms G and R are the rates of generation and recombination respectively. It is useful to note that in the AlGaN/GaN MOSHEMT structure, the dominant carriers are electrons which make up the 2DEG layer at the interface of the AlGaN and GaN. However for a comprehensive simulation run, the continuity equation for holes is included in the simulations. 4.1.3 Mobility Model The Sentaurus TCAD simulation suite uses a modular approach in its definition of carrier mobilities, thus it is possible to include several models which are in effect in a device. In this work, four kinds of mobility models were identified as relevant and were incorporated into the simulation process. These models include the constant mobility model, Masetti model (doping-dependent mobility), Lombardi model (interface degradation mobility) and Canali Model (high-field saturation mobility). The Sentaurus TCAD simulator makes use of the Matthiessen’s rule [30] to combine the contributions of each model. The values of the various coefficients and constants 58 were provided by Synopsys which were based on values available in the literatures. When such values are not available from literature, the values of GaAs are generally used as a guideline [7]. A brief discussion of the models follows. Constant Mobility Model The constant mobility model [45] is a default model for all simulations performed in Sentaurus TCAD. This model is dependent only on lattice temperature and is given by ( ) (4.17) where µL refers to the mobility due to bulk phonon scattering and is an exponent which can be found from literature. In this work, µL(electrons) = 1200 cm2/Vs and µL(holes) = 20 cm2/Vs. Since variation of temperature is not taken into account for this simulation run, T=300 K and the mobility is generally fixed at its default µL value. Masetti Model (Doping-dependent mobility) Although the structure that is used to fabricate the AlGaN/GaN MOSHEMT consists of intrinsic semiconductor in all the layers, there is usually the presence of unintentional doping in GaN-based semiconductors. This unintentionally doped GaN was believed to be n-type due to nitrogen vacancies [46]. Thus due to the presence of this unintentional doping, there is a degradation of mobility due to this doping effect. This could be simulated by placing a light N-type doping of 3.0×1016 cm–2 in the GaN layer. 59 This model accounts for the degradation in mobility due to impurity scattering in the semiconductor [47]. This model is described by ( ) ( ) (4.18) ( ) The values of the various coefficients and constants in equation (4.18) are given in Table IV, whereas µconst refers to the constant mobility value given in the Constant Mobility model. Table IV. The default coefficients for GaN in the Masetti model [7]. Electrons Holes Units 85 33 cm2/V s 75 0 cm2/V s 50 20 cm2/V s 6.50×1015 5.00×1015 cm3 9.50×1016 8.00×1016 cm3 7.20×1019 8.00×1020 cm3 α 0.55 0.55 - β 0.75 0.7 - Symbol 60 Canali Model (High-field saturation mobility) Presently, the AlGaN/GaN devices are primarily used for high power and high voltage applications due to their large bandgap as well as high electron saturation drift velocity. This drift velocity would be the limiting factor of the mobility when a device experiences a high electric field condition. Thus it is reasonable to include the high field dependence model as one of the mobility models. The Canali Model [48] is based on the Caughey-Thomas model [49] but with temperature-dependent parameters up to 430 K. The Canali mobility model is given by ( where ) ⁄ (4.19) refers to the parallel high field experienced and µlow refers to the low field mobility, which in this case refers to the constant mobility defined previously. β is a temperature dependent exponent which in this case is given as 1.7 (provided by Synopsys) as the temperature effect is not taken into account here. vsat refers to the electron saturation drift velocity of GaN (3.0×107 cm s-1) which is the critical value that determines this mobility value. Lombardi Model (Interface degradation mobility) The Canali model describes the effect of the lateral electric field that is experienced by the carriers. These carriers however, experience not only the lateral electric field, but also the vertical (or gate) electric field. The effect of the vertical electric field on carrier mobility is attributed to acoustic phonon scattering and surface roughness scattering [45]. This is modelled by the Lombardi model which combines the bulk 61 mobility together with the effect of acoustic phonon scattering and surface roughness scattering by Matthiessen’s rule [45]. The acoustic phonon scattering is given by ( ) (4.20) ( ) while surface roughness scattering is given by ( ) (4.21) [ ] where Eref refers to the reference field of 1V/cm to ensure a unitless numerator. A* refers to an exponent which can be calculated by an equation found in [50]. At the point of time this thesis is being written, there is no known literature that gives the value of the coefficients in the Lombardi model for GaN or GaAs. Thus the coefficients used are those of silicon and are given in Table V. 62 Table V. The default coefficients for Silicon in the Lombardi Model [7]. These coefficients are used for the simulation due to a lack of these values for GaN in the literature. Symbol C A* 4.2 Electrons Holes Units 4.75×107 9.925×106 cm/s 5.80×102 2.947×103 cm5/3V-2/3s-1 1 1 cm-3 0.125 0.0317 - 1 1 - 5.82×1014 2.0546×1014 cm3 2 2 - 5.82×1030 2.0546×1030 V2cm-1s-1 Effect of different AlGaN Layer thickness Ibbetson demonstrated in [1], the effect the AlGaN layer thickness has on the 2DEG density. He showed that the AlGaN thickness has a direct correlation to the 2DEG density up to a certain thickness (Figure 4.5). 63 Figure 4.5. The graph of the 2DEG density measured as a function of Al0.34Ga0.66N barrier thickness @ room temperature. Solid dots are experimental data, curve represent least square fit of equation (4.22) up to 15 nm [1]. He postulated that the 2DEG density would increase with AlGaN layer thickness up to a thickness of 15 nm according to equation (4.22), after which there would be significant relaxation in the AlGaN layer and thus a slight reduction in polarisation and consequently, the 2DEG density: ( ) (4.22) where σpz refers to the polarisation-induced charges at the AlGaN/GaN interface and the surface and tcr refers to the critical thickness at which 2DEG is induced. The critical thickness according to [1] is 35 Å as seen from Figure 4.5. 64 In this part of the project, this correlation between the 2DEG and AlGaN barrier thickness is simulated to see if the simulation would behave like Ibbetson’s experimental data. The simulation was done on a device with the following configurations (Table VI). Simulation Results Various simulation runs were performed in order to study the effect of the thickness of AlGaN on device performance in general. AlGaN layer thickness was set at 5, 10, 15 and 20 nm while the other parameters were kept constant to ensure consistency in the results. The study was done by observing a few of the electrostatic and physical results that were obtainable from the simulation program. ID-VGS sweeps were simulated on the devices and the results can be observed in Figure 4.6. Table VI. The configurations of device used for simulation with varying AlGaN thickness. Device Parameters Value AlGaN thickness Vary from 5 – 20 nm GaN thickness 2 µm High-k Dielectric thickness 7 nm (Al2O3) Gate Length (Lg) 300 nm Source-Gate/Drain-Gate Length 500 nm 65 Drain Current ID (uA/um) 120 5nm 10nm 15nm 20nm 100 80 60 40 20 0 -6 -5 -4 -3 -2 Gate Voltage VG (V) -1 0 Figure 4.6. Simulated ID-VGS characteristics of devices (VDS = 0.1 V) with different AlGaN thickness. The threshold voltage are, VTH(20 nm) = -4.20 V, VTH(15 nm) = -3.25 V, VTH(10 nm) = 2.25 V, VTH(5 nm) = N.A. An evident change in the threshold voltage is observed from Figure 4.6. The threshold voltage increases from -4.20 V (device with 20 nm AlGaN layer thickness) to -2.25 V (device with 10 nm AlGaN layer thickness) with decreasing AlGaN layer thickness. The device with a 5 nm AlGaN layer thickness did not yield any drain current as it might not have any 2DEG induced as it might be below the critical thickness required for carrier induction. The 2DEG density can be observed from results that can be extracted from the simulation run. Figure 4.7 to Figure 4.10 show the 2DEG density of each device in the channel region (under the gate). 66 High-K Dielectric (Al2O3) Al0.25Ga0.75N (5nm) GaN Buffer Layer Source Drain Figure 4.7. The electron density mapping in device with 5nm thick AlGaN layer. The interface between the AlGaN layer and the GaN layer is situated at Y=0 and thus the 2DEG should exist at the region just below Y=0. The electron density in devices with 5 nm AlGaN layer appears to be very low. This is in stark contrast with devices with AlGaN layer thickness of ≥10 nm (Figures 4.8-4.10). In Figures 4.7- 4.10, the diagram on the left refers to the electron density mapping that is observable at zero bias; i.e. VD, VS and VG are at 0 V. On the right side, this diagram represents the electron density mapping observable at VS = 0 V, VD = 0.5 V and VG = 5 V (mapping obtained at the end of ID-VGS sweep). Thus the devices should all be in the off-state. 67 Figure 4.8. The electron density mapping in device with 10 nm thick AlGaN layer. Figure 4.9. The electron density mapping in device with 15 nm thick AlGaN layer. 68 Figure 4.10. The electron density mapping in device with 20 nm thick AlGaN layer. It is however difficult to make a quantitative comparison between the 4 figures, thus the electron density between Y=0 and Y=0.01 um (10 nm) was integrated to obtain a number for quantitative comparison. This quantitative comparison is presented in Figure 4.11. 69 -2 12 Electron Density (×10 cm ) 6 5 4 3 2 1 0 4 6 8 10 12 14 16 18 20 22 AlGaN Layer Thickness (nm) Figure 4.11. A plot showing the simulated 2DEG density as a function of Al0.25Ga0.75N barrier thickness. The 2DEG density ranges from 8.69×104 cm-2 @ 5nm to 5.90×1012 cm-2 @ 20nm AlGaN layer thickness. It is observed that the experimental results (Figure 4.5) of Ibbetson in [1] may not have the same trend as the simulated result after the 12 nm mark, as shown in Figure 4.11. This is due to the fact that in this simulation performed, the stress relaxation component was not included. It was observed that in thicker AlGaN layers, there might be changes (reduction) in stress on the GaN layer, influencing the piezoelectric polarisation [51]. This resulted in a reduction of 2DEG density. This is not accounted for in the simulation. Thus the saturation/reduction in 2DEG density after a certain thickness of AlGaN layer is not observed in this simulation. In addition, the lower Al mole fraction in the simulations (x = 0.25) would also result in a lower drive current [52] as compared to that of the experimental results in 70 Ibbetson’s work (x = 0.34). However, a general trend that 2DEG density increases with increasing AlGaN thickness (before stress relaxation sets in) is observed from when AlGaN thickness is 4.5 nm to 12 nm. In addition to electron density mapping, it is also possible to extract the band diagram in each simulation run. From the band diagram extracted (Figure 4.12), it is observed that when the AlGaN layer thickness is 5 nm, the triangular quantum well is not present, as compared to the band diagram (Figure 4.13) for the device with 20 nm AlGaN layer which shows the triangular quantum well that would confine the carriers that form the 2DEG. High-K Dielectric AlGaN Layer Energy Level (eV) GaN Buffer Layer 4 3 2 1 0 -1 -2 -3 -4 EC EF EV -10 0 10 20 30 Y-Axis (nm) 40 50 Figure 4.12. The energy band diagram of AlGaN/GaN MOSHEMT with 5 nm thick AlGaN layer extracted from the simulation. 71 High-K Dielectric AlGaN Layer Energy Level (eV) GaN Buffer Layer 4 3 2 1 0 -1 -2 -3 -4 EC EF EV -20 -10 0 10 20 Y Axis (nm) 30 40 50 Figure 4.13. The energy band diagram of AlGaN/GaN MOSHEMT with 20 nm thick AlGaN layer extracted from the simulation. The thickness of the AlGaN layer would indirectly affect the 2DEG density due to the energy level of the traps being positioned differently at different AlGaN layer thickness. The position of the energy level of these traps would affect the ionization state of these traps and thus affect the 2DEG density directly as described by Ibettson. 72 4.3 Effect of Interface Traps on Device Operations Figure 4.14. A schematic diagram showing where energy level of donor-like surface states reside in a) thin AlGaN layer that is < critical thickness b) thicker AlGaN layer > critical thickness [1]. In section 4.2, the effect of AlGaN thickness on the 2DEG density was demonstrated. That effect on the 2DEG density clearly translated to a change in the drive current. It is thus useful to observe the effect of the concentration of these donor-like states at the AlGaN / high-k dielectric interface and how it affects the 2DEG and other electrical characteristics. In all previous simulation runs, the donor-like traps are positioned slightly above the Fermi level as shown in Figure 4.15. The trap energy was defined by [ ( )] (4.23) where E0 is defined to be 0.2 eV (i.e. 0.2 eV above mid-gap level). 73 High-K Dielectric AlGaN Layer Energy Level (eV) GaN Buffer Layer 4 3 2 1 0 -1 -2 -3 -4 Traps Level EC EF EV -20 -10 0 10 20 Y Axis (nm) 30 40 50 Figure 4.15. The energy level of the trap in a device with 20 nm thick AlGaN layer being programmed in this simulation run. In this set of simulation runs, two different simulations were performed. These two different runs are differentiated solely by the concentrations of the traps that are placed at the interface between the AlGaN layer and high-k gate dielectric. The configurations of these simulations are a) Trap concentration = 3.0×1013 cm-2 eV-1 and b) Trap concentration = 5.0×1013 cm-2 eV-1. All of these traps are assumed to exist at a single energy level (0.2 eV above mid-gap level) as shown in Figure 4.15. 74 Drain Current ID (uA/um) 140 120 13 -2 -1 Trap Conc. = 3.0×10 cm eV 13 -2 -1 Trap Conc. = 5.0×10 cm eV 100 80 60 40 20 0 -10 -8 -6 -4 -2 Gate Voltage VG (V) 0 Figure 4.16. A ID-VGS plot of simulated devices with different donor-like trap concentration. The ID-VGS plot (Figure 4.16) would give a first indication of the qualitative comparison of the device performance in terms of the 2DEG density. It is observed that the device with a higher donor-like trap concentration had a threshold voltage that is much more negative which would most like translate to a much higher induced 2DEG density. By performing a similar integration of the electron density in the first 10 nm of the GaN layer just below the AlGaN/GaN interface, we obtain the 2DEG density for the 2 devices. The integration yielded a 2DEG density of 5.90×1012 cm-2 for the device with a trap concentration of 3.0×1013 cm-2 eV-1 while the device with a trap concentration of 5.0×1013 cm-2 eV-1 yielded 2DEG density of 6.00×1012 cm-2. 75 The difference in 2DEG density seems to suggest that there might be a saturation point at which an increase in donor-like traps would have little impact on the 2DEG density. However, the change in threshold voltage does not justify the small change in 2DEG density. Upon more analysis of the simulation, it seems that in a device with increased donor-like density, this additional ionised charge would manifest itself as a space charge in the upper region of the AlGaN layer. The evidence of this is shown in the data for space charge (in the device at the gate region) extracted from the simulation (Figure 4.17). Trap Density = 5.0×1013 cm-2 eV-1 2DEG Region Trap Density = 3.0×1013 cm-2 eV-1 AlGaN Layer GaN Layer Figure 4.17.The simulated space charge data on AlGaN/GaN MOSHEMT at gate region extracted from the simulation. 76 This manifestation of charge in the AlGaN layer could lead to the more negative threshold voltage as seen in Figure 4.16. However, the actual mechanism of this phenomenon is largely unknown as it requires more study. 4.3.1 Effect of Surface Passivation The previous simulation result does not show consistency with the experimental results of the surface passivation. In the results of the experimental devices, the surface passivation reduces the interface states between the gate dielectric and the AlGaN layer [32]. Thus instead of having a small impact on the threshold voltage as seen in section 3.3, with less interface states, there should be a shift towards the positive region in threshold voltage as seen in the simulation due to a change in 2DEG density. This work postulates that there are both acceptor-like traps as well as donor-like traps at the interface of the gate dielectric and AlGaN layer and that the passivation process is more likely to reduce the acceptor-like traps. Although there is scant literature that shows the presence of acceptor-like traps at the surface, it would be possible to simulate the effect of having both kinds of trap at this interface, and assume that the surface passivation process reduces the density of the acceptor-like traps. For the purpose of simplifying the simulation process, it is assumed that the donor-like traps are not affected by the surface passivation process in the simulation. The configurations of the simulations are thus done with different 77 acceptor-like trap concentration set at: a) No acceptor-like traps, b) 1.0×1012 cm-2 eV-1, c) 5.0×1012 cm-2 eV-1 and d) 1.0×1013 cm-2 eV-1. The donor-like traps at this interface is fixed at 3.0×1013 cm-2 eV-1 with and energy level of E0 = 0.2 eV while the energy level of these acceptor-like traps were specified at E0 = -0.2 eV (i.e. 0.2 eV below mid-gap) . In order for these acceptor-like traps to be ionised they must exist below the Fermi level. The ID-VGS plot (Figure 4.17) gives an indication that the postulate might be plausible. Figure 4.18 shows that when the concentration of acceptor-like traps is reduced (e.g. reduced by the surface passivation process), the drain current increases with little change in threshold voltage. This is in better agreement with the results of the Drain Current ID (uA/um) experimental devices. 100 80 60 40 No Acceptors 12 -2 -1 1.0×10 cm eV 12 -2 -1 5.0×10 cm eV 13 -2 -1 1.0×10 cm eV 20 0 -5 -4 -3 -2 -1 Gate Voltage VGS (V) 0 Figure 4.18. The ID-VGS plot of devices with different concentration of acceptor-like trap. 78 An ID-VDS sweep was done with the same simulated devices with a gate overdrive of VG-VTH = 3.5 V. The plot is shown in Figure 4.19. Drain Current ID (uA/um) 600 500 400 300 No Acceptors 12 -2 -1 1.0×10 cm eV 12 -2 -1 5.0×10 cm eV 13 -2 -1 1.0×10 cm eV 200 100 0 0 2 4 6 8 Drain Voltage VDS (V) 10 Figure 4.19. The ID-VDS plot of devices with different concentration of acceptor-like traps. The ID-VDS characteristics show good agreement with the results of the experimental devices shown in section 3.3. In order to obtain drive current enhancement of >50% like those seen in section 3.3, it is possible that the acceptor-like interface state concentration underwent a reduction of ~ 5 times. A reduction of 50% (1.0×1013 cm-2 eV-1 - 5.0×1012 cm-2 eV-1) of traps resulted in a 75% increase in drive current (200uA/um to 350uA/um) as demonstrated by the simulation results shown in Figure 4.19. However, it should be noted that this is based on an ideal condition where the reduction of acceptor-like traps would unconditionally contribute to an increase in drive current. 79 Chapter 5 Simulation of the Effect of Stress on AlGaN/GaN MOSHEMT In an attempt to achieve an enhancement mode device, a compressive stress liner was deposited to reduce the intrinsic tensile stress that is present in the AlGaN/GaN heterostructure (Figure 5.1). X. K. Liu has demonstrated in [31], that such an approach is feasible experimentally. In addition, Liu explained that a coupled tensile stress is present in the device in the region between the gate and the source/drain. This tensile stress helped to enhance the device performance in a AlGaN/GaN MOSHEMT with DLC stress liner. In this part of the thesis, simulation is used to study the effect of compressive stress on the device performance of AlGaN/GaN MOSHEMTs. Two simulation softwares were used to simulate the effect of stress on the device. Taurus was used to simulate the resulting stress on the device due to the DLC stress liner while Sentaurus TCAD was used to simulate the device performance under stress. 80 Figure 5.1. The schematic view of the AlGaN/GaN MOSHEMT with a compressive DiamondLike Carbon (DLC) liner. The 2-DEG density decreases with application of compressive stress. 5.1 Device Structure and Stress Model The device structure used in this part of the project is similar to the devices simulated in Chapter 4. However, as the simulation suite has not been optimised for III-nitride simulations, the effect of the stress on the AlGaN/GaN heterostructure is not effectively modelled to portray the resulting piezoelectric effect that might result because of this stress. In order to model the polarisation charges effectively, the resulting polarisation induced charges were calculated and input into the simulation code independently. This polarisation charge calculated is based on the piezoelectric and spontaneous polarisations experienced at the interfaces. 81 To effectively simulate the stress that is induced on the device and the resulting effect of this stress, mechanical stress simulation was first performed using the Abaqus simulation suite. This was done by B. Liu whose work on DLC liner as a compressive stress liner provided much of the expertise needed for this experiment and simulation [53- 55]. The Abaqus simulation suite is able to simulate the mechanical stress that is experienced in the entire device due to a stress liner being deposited. The schematic of the structure being simulated in the Abaqus simulation software is shown in Figure 5.2. As the DLC liner is only deposited over the gate region and the regions between the gate and source/drain, only data from those regions were extracted after the simulation in Abaqus. The X- and Y-axes denote the reference frame in which this device’s geometry will be discussed. Figure 5.2. The schematic diagram of the device being simulated in Sentarus TCAD and Abaqus for the effect of compressive stress liner. The X and Y-axes denote the device geometry that was used in this simulation. 82 Uniaxial stress was taken into consideration for this simulation as it was shown in [36] that stress parallel to the gate width had little impact on the performance of the device. The strain experienced along the x-axis due to the uniaxial stress induced on the device (Figure 5.2) is known as stressXX. This is the dominant stress that affects the in-plane piezoelectric polarisation in the AlGaN/GaN heterostructure. Each region of the structure was configured with the appropriate material and its properties. After the mechanical stress simulation was completed, the non-critical regions (where little or no stress was experienced) were taken away to reduce data extraction time. The resulting stress (stressXX) distribution in the AlGaN and GaN layers due to the 40 nm of DLC compressive stress liner is shown in Figure 5.3. High-K Dielectric (Al2O3) Layer AlGaN Layer GaN Layer Figure 5.3. A map depicting the StressXX distribution that is experienced in a simulated AlGaN/GaN device with LG = 300 nm due to 40nm of DLC compressive stress liner. 83 In the previous simulations, the GaN layer is assumed to be totally relaxed as it is much thicker than the AlGaN layer. In order to maintain the consistency with previous simulations, the GaN layer will also be assumed to be totally relaxed for this part of the simulation; thus only the stress that is experienced in the AlGaN layer of the device is taken into consideration in the simulation. The average stress over the 20 nm of the AlGaN layer was computed and is shown in Figure 5.4. A negative value in stress would denote a compressive stress while a positive stress value would denote a tensile stress. It is observed that the stress experienced in the AlGaN layer under the gate region is generally compressive in nature while the AlGaN regions beyond the gate experience a weak tensile stress. This coupling of stress is due to the fact that the DLC liner is deposited over the metal gate stack. In this manner, the compressive stress has been concentrated on the gate edge as seen in Figure 5.3 while the regions beyond the metal gate stack would result in a coupled tensile stress. An empirical method was used in the translation of this stress experienced in the gate region to the polarisation charge induced. Strain in a material [56] can be represented by (5.1), where a is the unstrained bulk lattice constant, is the strained bulk lattice constant, σ is the stress induced and E is the Young’s modulus of the material under stress. The Young’s Modulus of Al0.25Ga0.75N has been documented in literature to be between the values of 320GPa – 350GPa [52, 56-59]. Thus an average value of 335GPa was chosen for this empirical calculation. 84 400 StressXX (MPa) 200 0 -200 -400 -600 -800 -1000 -600 -400 -200 0 Gate Region 200 400 600 X (nm) Figure 5.4. A plot of the average StressXX distribution that is experienced in the AlGaN layer of the device structure shown in Figure 5.2. It is observed that in Figure 5.4, the stress in the simulated region ranges from about 200 to -1000MPa. Thus by making use of results shown in Figure 5.4 and equation (5.1), we will be able to obtain the effective lattice constant at each discreet point of the device due to the stress at that point. This series of effective lattice constants is then substituted into equations (4.1) – (4.11) in section 4.1.1. An effective nonuniform polarisation induced charge distribution at the interface of the AlGaN and GaN layer is obtained and shown in Figure 5.5. The dashed horizontal line denotes the uniform polarisation charge that would exist in a device without the DLC liner. The compressive stress under the gate region gives rise to a polarisation charge value that is lower than that of the uniform charge distribution while the tensile stress beyond the gate region gives rise to a higher value of the polarisation charge. 85 2 1.5 13 Polarization Charge (x10 C/cm ) a) 1.4 1.3 1.2 1.1 1.0 -600 -400 -200 0 200 X (nm) 400 600 Y (nm) b) X (nm) Figure 5.5. a) Polarisation induced charges at the interface of AlGaN/GaN due to compressive stress by the DLC stress liner, dashed horizontal line denotes the uniform polarisation charge in a non-stressed device. b) A corresponding device schematic illustrating the device geometry. This polarisation charge was input into the simulation at discreet points in 10 nm intervals at the AlGaN/GaN interface. Due to a change in piezoelectric polarisation in the AlGaN layer, a similar change in polarisation induced charge distribution is also experienced at the High-k dielectric/AlGaN interface. The corresponding charge distribution at that interface is also calculated and put at discreet points at 10 nm intervals. The simulation was then performed with these changes in polarisation 86 charge distribution due to stress from the DLC liner. Interface states were also included between the AlGaN layer and the high-k dielectric layer. These interface traps were set to be donor-like, at a concentration and energy level of 3.0×1013 cm-2 eV-1 and 0.2 eV above mid-gap respectively. No acceptor-like interface states were included in this simulation. 5.2 Effect of Stress on Electrical Characteristics The ID-VGS characteristics is first analysed. The control ID-VGS plot was taken from the ID-VGS plot in section 4.2 where the effect of the thickness of the AlGaN layer was studied. The ID-VGS plot of the device with DLC stress liner, as well as that of the control device is shown in Figure 5.6. Figure 5.6. The ID-VGS plot of the MOSHEMT device with and without the DLC stress liner. The gate length of the devices, Lg = 300nm. 87 Figure 5.7. The effect of compressive stress from DLC stress liner on the ID-VDS plot of simulated device with Lg = 300nm. A shift in the threshold voltage from -4.20 V (no stress) to -3.50 V (with compressive stress) is observed in the ID-VGS plot in Figure 5.6. The trend observed is consistent with the results of the experimental devices discussed in section 3.3.2 where devices with DLC compressive stress liner were characterised. In addition, in section 3.3.3, an ID-VDS measurement was also performed on these devices where a 36% enhancement in drive current was observed. An ID-VDS sweep was also performed for the simulated device and the result is shown in Figure 5.7. The simulation result did not show a similar amount of enhancement compared to the experimental devices. However, it does show a similar trend of a higher drive current (2.5% enhancement). This could be attributed to the fact that the effect of stress was 88 not fully simulated in this process. Instead, only the change in polarisation induced charge was taken into account. The enhancement of drive current could also be due to a few factors such as a change in the effective mass of the electrons due to a change in band structure [2],[3] or a change in trap concentration [60]. Some of these factors such as change of effective mass is not taken into considerations as it would require one to include the calculations due to change in band structure which is not in the scope of this thesis. 5.3 Effect of Stress on Carrier Concentration Although some factors that could lead to drive current enhancement is not taken into consideration in this simulation, it is still meaningful to look at how the other parameters in this simulated device affect the electrical results. In the previous sections, it is observed that a change in 2DEG density affects the threshold voltage of a device. When stress is induced in the device, a non-uniform polarisation charge is observed. That would give rise to a non-uniform distribution of the carriers in the 2DEG. In this case the 2DEG density of the device at 1 nm below the AlGaN/GaN interface was extracted from the device simulation. The 2DEG density distribution is shown in Figure 5.8. 89 6 2.4 ~ 7% Increase 2.2 2.0 -500 4 -450 -400 -350 -300 -250 X axis (nm) 2 -1000 19 No Stress With Stress Electron Density ( x10 ) 19 Electron Density ( x10 ) 8 ~15-35% Decrease -500 0 500 X Axis X (nm) 1000 Figure 5.8. A plot of the simulated 2DEG density in the x-direction of the device at a depth of 1 nm below the AlGaN/GaN interface. A reduction of electron density is observed in the channel region under the gate while a slight increase in electron density is observed outside the gate region. Figure 5.8 shows that the distribution of the electron density follows the distribution pattern of the polarisation charge shown in Figure 5.5a. It is observed that the region under the gate has about 15-35% less carriers as compared to the device without the DLC stress liner. This reduction in 2DEG density under the gate would thus require a less negative gate voltage to deplete the 2DEG in order to turn off the device. This explains the positive shift in the threshold voltage of the device with the DLC liner, as observed in the ID-VGS plot in Figure 5.6. On the other hand, the tensile stress in the regions beyond the gate has resulted in an average increase of about 3-7% in the 2DEG density in those regions. This slight increase in electron concentrations could have provided a lower external resistance in 90 the LS-G and LD-G region. This higher conductivity in these regions is one of the factors that enhanced the drive current in the ID-VDS plot shown in Figure 5.7. 5.4 Effect of Stress on Carrier Mobility The non-uniform distribution of the polarisation charge could have had other effects than the 2DEG distribution. Thus a plot of the mobility of the electrons in the 2DEG (1 nm below the AlGaN/GaN interface) is extracted from the simulation and is shown in Figure 5.9. 2 Electron Mobility (cm /Vs) 1200 With Stress No Stress 1000 800 6 - 17% Increase 600 400 200 -1000 -500 0 500 1000 X (nm) Figure 5.9. A plot of the simulated electron mobility value along the x-axis of the MOSHEMT with and without stress, at a depth of 1 nm below the AlGaN/GaN interface. 91 The mobility plot in Figure 5.9 indicates a 6-17% increase in mobility of the 2DEG in the region under the gate. This increase in mobility could have been a result of a change in the vertical (y-direction) electric field in the device due to the non-uniform distribution of the polarisation charges. The reduction in 2DEG density, which reduces carrier-carrier scattering, could also be a factor in the increase in electron mobility in the channel. The vertical electric field is extracted from the simulation and is shown in Figure 5.10. Only the vertical electric field is taken into consideration here as the mobility degradation effect would be caused predominantly by the vertical electric field as presented by the Lombardi Model [43],[45]. The electric field shown here is the vertical electric field 1 nm below the AlGaN/GaN interface. By looking at equations (4.20) (Lombardi model) in the previous section (section 4.1.3), it is observed that this model is directly affected by the vertical electric field present in the device. Thus it is reasonable to attribute this change in mobility to the change in electric field shown in Figure 5.10. Equation (4.20) is re-produced here for ease of reference, ( ) ( (4.20). ) 92 -1 Vertical Electric Field (MV/cm ) 1.0 With Stress Without Stress 0.9 0.8 0.7 0.6 0.5 -600 . -400 -200 0 200 X (nm) 400 600 Figure 5.10. A plot of the simulated vertical electric field along the x-direction of the MOSHEMT with and without stress, at a depth of 1nm below the AlGaN/GaN interface. However, it should be noted that this change in mobility is not due to the change in effective mass or change in band structure as the models that describe the mobility change due to these factors are not used in this simulation. The increase in mobility in this region could be one of the factors that resulted in the increase in drive current in the device. However, the values of the fitting parameters such as B and C are not known for GaN materials, thus the model may only give a qualitative evaluation and not a quantitative one. 93 Chapter 6 Conclusion In this thesis, characterisation work had been carried out on experimental AlGaN/GaN MOSHEMT devices. Before that, some preparatory work needs to be done in order to achieve a successful fabrication of the required devices. This thesis had given an overview of the mask design and some of the various designs of test structures that were designed and included in the mask layout. In addition, a brief description of the mechanism and physics of how each test structure works is also presented. After these preparatory works were presented, the fabrication process was described with the various splits in the experiment included. Different electrical characterisation techniques were presented and the results and analysis of each characterisation were also discussed in a succinct manner. The observations in the characterisation work of experimental devices shows that devices with surface passivation (in situ VA and SiH4 treatment) gave a 53% enhancement in saturation drain current over the control device without any surface passivation. However, it had little impact on the threshold voltage which was determined using the ID-VGS measurement. The electrical characterisations of devices with DLC stress liners were also presented. These devices had a +0.7 V threshold voltage shift over the control devices without DLC liners. This change in threshold voltage could be due to the change in 2DEG density under the gate region. In addition to the change in threshold voltage, the devices with DLC liners also saw a 36% enhancement in saturation drain current over devices without DLC liners. This could 94 be a result of a change in mobility of the channel electrons due to the stress induced by the DLC liner. Numerical simulations were performed to complement the experimental work. Various simulation models and the physics used in the simulation were described and explained. The different relevant models were integrated to perform several device simulations. Firstly, the effect of the thickness of the AlGaN barrier layer on the threshold voltage of the AlGaN/GaN MOSHEMT was studied. This part of the work showed consistency with the literature which showed that a thicker AlGaN layer would generally gave rise to a higher 2DEG density before stress relaxation sets in. The effect of interface states were also simulated with different types of traps put into place at the AlGaN/high-k dielectric interface to study their effect on device performance. A postulation was also made with respect to the mechanism of the surface passivation work where it was hypothesized based on simulation result that during the surface passivation, acceptor-like traps are the traps that are being passivated thus improving the device performance. Finally, an AlGaN/GaN MOSHEMT with stress induced by a stress liner was also simulated in order to better understand the effect of the compressive stress that the DLC liner induced on the experimental devices. It is shown in the simulations that the stress induced in the AlGaN layer resulted in a different distribution of polarisation induced charges. This non-uniform distribution of polarisation charges would thus give a non-uniform electron distribution in the 2DEG. As a result of the difference of 95 stress in different parts of the device, a shift in threshold voltage is observed while an enhancement in drive current is also observed due to change in electric field experienced in the device. 6.1 Possible Future Work Future projects can be done as extensions to the simulation work done in this thesis. One of these would be to make use of the stress model that might be available in future versions of Sentaurus TCAD to simulate the effect of stress on device performance. In this simulation work, the effect of stress is configured such that it only affects the polarisation charges and that alone has shown that a shift in threshold voltage and enhancement in drive current is possible. If the other effects of stress such as the effect of stress on the effective mass of the carriers or the energy band structure of the GaN and AlGaN can be incorporated, a more accurate study of the stress effect could be performed. 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Eddy, "Simulation on the Effect of Nonuniform Strain from the Passivation Layer on AlGaN/GaN HEMT," Microelectronics Journal, vol. 36, no. 8, pp. 705-705, 2005. 109 [61] B. Luo, R. Mehandru, J. Kim, F. Ren, B. Gila, A. Onstine et al, "Comparison of surface passivation films for reduction of current collapse in AlGaN/GaN high electron mobility transistors," Journal of the Electrochemical Society, vol. 149, no. 11, pp. G613-G619, 2002. 110 Appendix A The baseline simulation code is given here. The simulation code consists mainly of the structure file (which describes the structure of the device) and the simulation file (which describes the necessary models to be used and the other electrical and material specifications required). Structure File: ;------------------------------------------------------------; ; vertical dimensions (define hAlN 0.100) (define hGaN 2.000) (define hAlGaN 0.020) (define hPass 0.050) (define hDielectric 0.007) ; horizontal dimensions (define Xmin -5.650) (define SrcLngth 5.000) (define DrnLngth 5.000) (define GtLngth 0.300) (define SrcSep 0.500) (define DrnSep 0.500) ; Ohmic contact definitions (define Sep 0.00) (define Dpng 1E20) ; Molefraction definition (define x_AlGaN 0.25) ;----------------------------------------------------------------------; ; Derived quantities ;----------------------------------------------------------------------; (define Xmax (+ Xmin SrcLngth SrcSep GtLngth DrnSep DrnLngth)) (define Ymax (+ hGaN)) (define Ymin (- 0 hAlGaN hPass)) (define Ysrfc (- 0 hAlGaN)) (define Yjnctn (- 0 Sep)) (define (define (define (define Xsrc XgtLft XgtRght Xdrn (+ (+ (+ (+ Xmin SrcLngth)) Xsrc SrcSep)) XgtLft GtLngth)) XgtRght DrnSep)) 111 ;----------------------------------------------------------------------; ; Create structure ;----------------------------------------------------------------------; (sdegeo:create-rectangle (position Xsrc Ymin 0) (position XgtLft (Ysrfc hDielectric) 0) "Nitride" "LeftPassivation" ) (sdegeo:create-rectangle (position Xsrc (- Ysrfc hDielectric) 0) (position Xdrn Ysrfc 0) "Al2O3" "Dielectric") (sdegeo:create-rectangle (position XgtRght Ymin 0) (position Xdrn (Ysrfc hDielectric) 0) "Nitride" "RightPassivation" ) (sdegeo:create-rectangle (position Xmin Ysrfc 0) (position Xmax 0 0) "AlGaN" "AlGaN_barrier" ) (sdegeo:create-rectangle (position Xmin 0 0) (position Xmax Ymax 0) "GaN" "GaN_bulk" ) ; ----------------------------------------------------------------------; Place AlGaN mole fraction ; ----------------------------------------------------------------------(sdedr:define-constant-profile "CP.xMole" "xMoleFraction" x_AlGaN) (sdedr:define-constant-profile-material "CP.xMole" "CP.xMole" "AlGaN" 0 "Replace") ; ----------------------------------------------------------------------; Place doping profiles to emulate metal spikes ; ---------------------------------------------------------------------(sdedr:define-refinement-window "Pl.Source" "Rectangle" (position Xmin Ysrfc 0) (position Xsrc Yjnctn 0)) (sdedr:define-constant-profile "P.source" "PhosphorusActiveConcentration" Dpng) (sdedr:define-constant-profile-placement "P.source" "P.source" "Pl.Source") (sdedr:define-refinement-window "Pl.Drain" "Rectangle" (position Xdrn Ysrfc 0) (position Xmax Yjnctn 0)) (sdedr:define-constant-profile "P.drain" "PhosphorusActiveConcentration" Dpng) (sdedr:define-constant-profile-placement "P.drain" "P.drain" "Pl.Drain") ; ----------------------------------------------------------------------; Place doping profiles to emulate background doping of GaN ; ----------------------------------------------------------------------(sdedr:define-refinement-window "Pl.GaN" "Rectangle" (position Xmin 0 0) (position Xmax Ymax 0)) (sdedr:define-constant-profile "P.gan" "NDopantActiveConcentration" 1E16) (sdedr:define-constant-profile-placement "P.gan" "P.gan" "Pl.GaN") ; ----------------------------------------------------------------------; Create and place all electrodes ; ----------------------------------------------------------------------(sdegeo:define-contact-set "source") (sdegeo:set-current-contact-set "source") (sdegeo:set-contact-edges (find-edge-id (position (+ Xmin 0.001) Ysrfc 0))) (sdegeo:define-contact-set "gate") (sdegeo:set-current-contact-set "gate") (sdegeo:set-contact-edges (find-edge-id (position (+ XgtLft 0.001) (Ysrfc hDielectric) 0))) (sdegeo:set-contact-edges (find-edge-id (position (* 0.5 (+ XgtLft XgtRght)) (- Ysrfc hDielectric) 0))) (sdegeo:set-contact-edges (find-edge-id (position (- XgtRght 0.001) (Ysrfc hDielectric) 0))) 112 (sdegeo:define-contact-set "drain") (sdegeo:set-current-contact-set "drain") (sdegeo:set-contact-edges (find-edge-id (position (+ Xdrn 0.001) Ysrfc 0))) ; ------------------------------------------------------------------------------; Grid refinement definitions ; ------------------------------------------------------------------------------(sdedr:define-refinement-window "Pl.Default" "Rectangle" (position Xmin Ymin 0) (position Xmax Ymax 0)) (sdedr:define-refinement-size "Ref.Default" 0.4 0.2 99 0.01 0.005 66 ) (sdedr:define-refinement-placement "Ref.Default" "Ref.Default" "Pl.Default" ) (sdedr:define-refinement-function "Ref.Default" "DopingConcentration" "MaxTransDiff" 1) (sdedr:define-refinement-window "Pl.eDensity" "Rectangle" (position (- XgtRght 0.05) Ymin 0) (position (+ XgtRght 0.3) 0.1 0)) (sdedr:define-refinement-size "Ref.eDensity" 0.005 99 99 0.005 66 66 ) (sdedr:define-refinement-placement "Ref.eDensity" "Ref.eDensity" "Pl.eDensity" ) (sdedr:define-refinement-window "Pl.channel_h" "Rectangle" (position (- XgtLft 0.1) Ymin 0) (position (+ XgtRght 1) 0.1 0)) (sdedr:define-refinement-size "Ref.channel_h" 0.1 99 99 0.001 66 66 ) (sdedr:define-refinement-placement "Ref.channel_h" "Ref.channel_h" "Pl.channel_h" ) (sdedr:define-refinement-window "Pl.drain_c" "Rectangle" (position (- XgtRght 0.2) Ymin 0) (position (+ XgtRght 0.7) 0 0)) (sdedr:define-refinement-size "Ref.drain_c" 0.04 99 99 0.005 66 66 ) (sdedr:define-refinement-placement "Ref.drain_c" "Ref.drain_c" "Pl.drain_c" ) (sdedr:define-refinement-window "Pl.contact_r" "Rectangle" (position (- XgtRght 0.005) Ymin 0) (position (+ XgtRght 0.05) 0.1 0)) (sdedr:define-refinement-size "Ref.contact_r" 0.005 99 99 0.001 66 66 ) (sdedr:define-refinement-placement "Ref.contact_r" "Ref.contact_r" "Pl.contact_r" ) (sdedr:define-refinement-window "Pl.contact_l" "Rectangle" (position (- XgtLft 0.005) Ymin 0) (position (+ XgtLft 0.005) 0.1 0)) (sdedr:define-refinement-size "Ref.contact_l" 0.005 99 99 0.001 66 66 ) (sdedr:define-refinement-placement "Ref.contact_l" "Ref.contact_l" "Pl.contact_l" ) (sdedr:define-refinement-window "Pl.surface" "Rectangle" (position Xmin Ysrfc 0) (position Xmax 0 0)) (sdedr:define-multibox-size "MB.surface" 99 0.05 99 66 0.001 66 1 2 1 ) (sdedr:define-multibox-placement "MB.surface" "MB.surface" "Pl.surface" ) 113 (sdedr:define-multibox-size "MB.barrier" 99 0.05 99 66 0.0004 66 1 -2 1 ) (sdedr:define-multibox-placement "MB.barrier" "MB.barrier" "Pl.surface" ) (sdedr:define-refinement-window "Pl.surface_Pol" "Rectangle" (position Xmin Ysrfc 0) (position Xmax (+ Ysrfc 0.0001) 0)) (sdedr:define-multibox-size "MB.surface_Pol" 99 0.05 99 66 0.0002 66 1 4 1 ) (sdedr:define-multibox-placement "MB.surface_Pol" "MB.surface_Pol" "Pl.surface_Pol" ) (sdedr:define-refinement-window "Pl.channel" "Rectangle" (position Xmin 0 0) (position Xmax hGaN 0)) (sdedr:define-multibox-size "MB.channel" 99 0.1 99 66 0.0004 66 1 1.5 1 ) (sdedr:define-multibox-placement "MB.channel" "MB.channel" "Pl.channel" ) (sdeaxisaligned:set-parameters "yCuts" (list -0.025 -0.0249 -5e-5 0 5e-5) ) ;--- Generate and save the mesh using Mesh (sde:build-mesh "snmesh" "" "n2_dielec") Simulation file Electrode { { Name="gate" Voltage= -0.8 Workfunction = 4.4 } { Name="source" Voltage= 0 Resist = 500 } { Name="drain" Voltage= 0 Resist = 500 } } File { * Input files Grid= "n2_dielec_msh.tdr" Parameter= "pp4_des.par" * Output files Current= "n4_des.plt" Plot= "n4_des.tdr" Output= "n4_des.log" } Physics { Mobility( Enormal(Lombardi) DopingDependence eHighfieldsaturation ) EffectiveIntrinsicDensity (Nobandgapnarrowing) Fermi Recombination(SRH) RecGenHeat Aniso(Poisson) Thermionic } 114 Physics (Material="GaN") { Traps ( (Acceptor Level Conc= 5e17 EnergyMid= 1.0 EnergySig= 0 FromMidBandGap eXSection= 1e-15 hXSection= 1e-15) ) } Physics (Material="AlGaN") { Traps ( (Acceptor Level Conc= 5e17 EnergyMid= 1.0 EnergySig= 0 FromMidBandGap eXSection= 1e-15 hXSection= 1e-15) ) } Physics (MaterialInterface="AlGaN/GaN") { Charge(Uniform Conc=1.328115e+13 ) } Physics (MaterialInterface="AlGaN/Al2O3") { Charge(Uniform Conc=-3.13841e+13 ) Traps ( (Donor Level Conc= 3.0e13 EnergyMid= 0.2 FromMidBandGap) ) } Plot { Potential Electricfield/Vector eDensity hDensity eCurrent/Vector hCurrent/Vector TotalCurrent/Vector SRH Auger Avalanche eMobility hMobility eQuasiFermi hQuasiFermi eGradQuasiFermi hGradQuasiFermi eEparallel hEparallel eMobility hMobility eVelocity hVelocity DonorConcentration Acceptorconcentration Doping SpaceCharge ConductionBand ValenceBand BandGap Affinity xMoleFraction eTemperature hTemperature eTrappedCharge hTrappedCharge eInterfaceTrappedCharge hInterfaceTrappedCharge } Math { Extrapolate Iterations= 16 Digits= 6 ErrRef(electron) = 1E5 ErrRef(hole) = 1E3 RHSmin= 1e-10 RHSmax= 1e30 CDensityMin= 1e-20 115 DirectCurrentComputation RelTermMinDensity= 1e5 eMobilityAveraging= ElementEdge } Solve { Coupled (Iterations= 100000 LinesearchDamping= 0.001) Coupled (Iterations= 100) {Poisson Electron Hole} {Poisson} **************************************************************** * Zero bias plot **************************************************************** Plot(FilePrefix="300nm_NS_n4_Zero_Bias") **************************************************************** * IdVd curve with Vg=0 V **************************************************************** NewCurrentFile="300nm_NS_IdVd_Vg0_" Quasistationary ( InitialStep= 5e-3 Minstep= 1e-7 MaxStep= 0.05 Increment= 1.55 Goal {Name="drain" Voltage= 10} ) { Coupled {Poisson Electron Hole} } Plot(FilePrefix="300nm_NS_Vg0_Vd10") **************************************************************** * IdVg curve with Vd=0.5 V **************************************************************** *NewCurrentFile="NS_IdVg_Vd10_" *Quasistationary ( * InitialStep= 0.025 Minstep= 1e-7 MaxStep= 0.05 Increment= 1.5 * Goal {Name="gate" Voltage= -5} *) { * Coupled {Poisson Electron Hole} *} * *Plot(FilePrefix="NS_Vg-5_Vd10") } 116 Appendix B The Taurus Abaqus simulation for simulating the stress on the device is shown here. The author would like to thank Liu Bin for his help in providing the simulation source code for this part of the project. TaurusProcess # 1/2 gate length Define (Lg = 150nm) Define (sp = 700nm) # Define the initial simulation domain and the initial grid. Also # initialize the Boron concentration in the silicon substrate. DefineDevice ( xSize = expr(($Lg)+ $sp) ySize = 0.5um #zSize = 0.5um Initialize( Name = phosphorus Value = 1.0e16 ) AmbientHeight = 1um RefinementsFile = refinements_data ) # # # # Add a set of regrid parameters to the current list of refinements. This specifies a maximum mesh spacing to 0.3um overall, and 5nm at region boundaries. The refinements are used later when mesh adaptation and boundary fitting is done during the process flow. Physics( Material=diamond YoungsModulus=760e+9 PoissonRatio=0.20 ) Physics( Material=Silicon C11= 3.9e+11 C12= 1.45e+11 C44= 1.05e+11 ) Physics( Material=Germanium YoungsModulus=3.97e11 ) 117 Refinements( Regrid( MeshSpacing = 0.3um MergeRegionsOfMaterial = oxide MergeRegionsOfMaterial = diamond CriticalFeatureSize = 0.1nm ThinLayer = 1nm Criterion( AllInterfaces MeshSpacing = 5nm ) ) Regrid( MeshSpacing = 0.003um MinX = expr(($sp)-0.1) MaxX = expr(($Lg)+ ($sp)) MinY = 0um MaxY = 0.01um ) Regrid( MeshSpacing = 0.005um MinX = 0.2 MaxX = expr(($Lg)+ ($sp)) MinY = 0um MaxY = 0.2um ) ) # Enable automatic stress history simulation during process flow. Physics( KeepStressHistory Material = silicon Anisotropic = true Bandgap (StressInducedBGNActive = true) ) Physics ( Material=Silicon Equation=Germanium Diffusion( StrainFactor( StrainDependency = true StrainCoefficient = 40.0) ) Equation=Boron Diffusion( StrainFactor( StrainDependency=true StrainCoefficient= -17.0) ) ) # Modify the linear solver and associated solution parameters. Numerics( Linearsolver = direct NewtonResid = 1e-10 ) Numerics (ImbalanceLimit = 10.0) Numerics( Iterations=20 maxDivergenceCount=10 ) 118 # Deposit thin planar oxide and nitride layers, then etch a 0.5 um # deep vertical trench using an etch mask at X = 0.2 um. Deposit( Material = Germanium Thickness = 0.02um ) #Deposit( # Material = oxide # Thickness = 0.01um #) #Deposit( # Material = nitride # Thickness = 0.1um #) #Etch #( # # # # # # # # # #) Thickness = 0.5um EtchType = dry MaskPolygon ( Point(x=0.2um z=-0.3um) Point(x=expr(($Lg)+ ($sp)) z=-0.3um) Point(x=expr(($Lg)+ ($sp)) z= 0.3um) Point(x=0.2um z= 0.3um) ) # Grow liner oxide. #Diffuse #( # Time = 5min # Temperature = 900C # DryO2 # NativeLayerThickness = 50A # InitialTimeStep = 0.5min #) #Deposit #( #Layer( # Material = oxide # thickness = 5nm # Onto(Material = silicon) #) #) Save(MeshFile = SiGe_50nm_nosti01.tdf) # Deposit TEOS infill to form the show trench isolation region, # which has a planar surface within the trench. Then strip the # nitride layer away. #Deposit #( # Material = teos # SurfacePosition = -0.02um #) #Etch #( # Material = nitride # EtchType = all #) #Save(MeshFile = SiGe_50nm_nosti02.tdf) 119 # Perform channel doping. #Implant #( # Name = boron # Energy = 500.0 # Dose = 1e13 # Tilt = 0 # Rotation = 0 # NoRegrid #) #Implant #( # Name = boron # Energy = 140.0 # Dose = 1e13 # Tilt = 0 # Rotation = 0 #) #Implant #( # Name = boron # Energy = 50.0 # Dose = 1e12 # Tilt = 0 # Rotation = 0 #) #Etch #( # Material = oxide # Thickness = 150A # EtchType = dry #) #Save(MeshFile = SiGe_50nm_nosti03.tdf) # Create the gate oxide and the Poly gate layer. Deposit ( Material = hafniumoxide thickness = 7nm ) Deposit ( Material = Tantalum Thickness = 0.1um ) #Save(MeshFile = SiGe_50nm_nosti04.tdf) # Define the poly gate. Etch ( Material = Tantalum EtchType = dry MaskPolygon ( Point(z=-1um Point(z=-1um Point(z= 1um Point(z= 1um ) ) x=expr($sp)) x=expr(($Lg)+ ($sp))) x=expr(($Lg)+ ($sp))) x=expr((($sp)))) 120 #recess etch #Etch #( # # # # # # # # # # # Material = oxide Material = silicon EtchType = dry Thickness = 700A MaskPolygon ( Point(z=-1um Point(z=-1um Point(z= 1um Point(z= 1um ) x=expr($sp)) x=expr(($Lg)+ ($sp))) x=expr(($Lg)+ ($sp))) x=expr((($sp)))) #) #Save(MeshFile = SiGe_50nm_nosti05.tdf) #Deposit( # AnisotropyFactor = 5 # MismatchStrain = True # Material=silicon # SurfacePosition = -0.006um # #25% Ge concentration # Initialize ( # Name=Germanium # Value=1.25e22 # ) #) # silicon atomic density=5e22 #Save(MeshFile = SiGe_50nm_nosti06.tdf) # Do the LDD implant. #Implant #( # Name = Boron # Energy = 5 # Dose = 2.5e14 # Tilt = 0 # Rotation = 0 #) # Liner Oxide Deposition (10nm) #Deposit ( # Material=oxide # Thickness=10nm # ) # Create the nitride spacer. #Deposit #( # Material = nitride # Thickness = 0.04um #) 121 #Save(MeshFile = unstrained_400nm_07.tdf) #Etch #( # Material = nitride # Thickness = 0.08um # EtchType = dry #) #Etch ( # Material=oxide # EtchType=dry # Thickness= 10nm # ) #Save(MeshFile = SiGe_50nm_nosti08.tdf) # Perform the high dose arsenic implant. #Implant #( # Name = Boron # Energy = 4.5 # Dose = 1.0e15 # Tilt = 0 # Rotation = 0 # NoRegrid #) #Save(MeshFile = SiGe_50nm_nosti09.tdf) #Do the RTA. #Diffuse #( # Time = 5s # Temperature = 1000C # NoRegrid #) #Save (MeshFile="SiGe_50nm_nosti10.tdf") #Reflect in the symmetry plane to form the full structure. define(a=0) while ($a[...]... LIST OF SYMBOLS AND ABBREVIATIONS ABBREVIATIONS DESCRIPTION/ EXPANSION GaN Gallium Nitride AlGaN Aluminium Gallium Nitride TaN Tantalum Nitride HFET Heterojunction Field Effect Transistor MODFET Modulation Doped Field Effect Transistor HEMT High Electron Mobility Transistor MOSFET Metal- Oxide- Semiconductor Field Effect Transistor MESFET Metal- Semiconductor Field Effect Transistor 2-DEG 2-Dimensional Electron. .. there is a substantial gate leakage current present in such a structure Unlike the MOSFET structure, the absence of a gate dielectric would be detrimental to the gate current leakage levels Comparing this gate leakage current to an ideal Schottky gate device shows that in the AlGaN/GaN HEMT device, the Schottky gate leakage current is very much higher than that of an ideal Schottky gate reverse current... of the 2DEG without any doping involved The polarisation effect and the operation of the HEMT device will be further elaborated in the next chapter 1.2 Scope and Purpose Having discussed the advantages of GaN semiconductor material as being a suitable candidate for high power and high temperature purposes, a GaN -based HEMT would thus be the choice candidate for electronic devices capable of withstanding... (W/cm K) Dielectric constant ε CFOM = (χ ε µ vsat EB) / ( χ ε µ vsat EB)Si CFOM: Combined figure of merit for high temperature /high power /high frequency applications GaN with a large bandgap (Eg = 3.40 eV), large critical breakdown field of 4.0 MV cm-1, coupled with good electron transport properties (theoretical electron mobility, µe, of up to 2000 cm2 V-1s-1 [9] and a peak saturation velocity, vsat, of. .. performance enhancement of GaN -based HEMTs for applications in highpower electronics Simulation work was performed to understand the effect of different parameters on the electrical performance of the device Effect of various parameters such as barrier layer thickness, concentration and energy level of interface traps as well as thermal effects were investigated The simulation of the effect of stress due to... Effect Transistor (MOSFET) and Metal- Semiconductor Field Effect Transistor (MESFET) However, due to the immaturity of the technology of material growth [8], it is still a challenge to make high quality epitaxial layer on various substrates Thus GaN layers often come with high density of defects, primarily due to the difference in lattice constant of GaN and the substrate it is grown on This makes surface... slight increase in electron density is observed outside the gate region 90 XIII Figure 5.9 A plot of the simulated electron mobility value along the x-axis of the MOSHEMT with and without stress, at a depth of 1 nm below the AlGaN/GaN interface 91 Figure 5.10 A plot of the simulated vertical electric field along the x-direction of the MOSHEMT with and without stress, at a depth of 1nm below the AlGaN/GaN... MOSHEMT at gate region extracted from the simulation 76 Figure 4.18 The ID-VGS plot of devices with different concentration of acceptor-like trap 78 Figure 4.19 The ID-VDS plot of devices with different concentration of acceptor-like traps 79 XII Figure 5.1 The schematic view of the AlGaN/GaN MOSHEMT with a compressive Diamond-Like Carbon (DLC) liner The 2-DEG density decreases with application of compressive... Matching Eliminate/Reduce need for High Voltage High Breakdown Field voltage conversion Operation Bandwidth, µ-wave/mmHigh Frequency High Electron Velocity wave High dynamic range Low Noise High Gain, High Velocity receivers High Temperature Wide Bandgap Rugged, Reliable Operations Direct Bandgap Technology Leverage Enabler for Lighting carrier transport or a high breakdown voltage Table II presents the... effect transistor (HFET) as a general class of devices Also known as the High Electron Mobility Transistor (HEMT), the ability to induce a conductive 2 DEG in intrinsic GaN heterostructure layers of the device has ignited interest of many people In the rest of this thesis, we will be working on the AlGaN/GaN HEMT structure that is currently the de facto norm for GaN -based HEMTs The High Electron Mobility ... Metal-Oxide-Semiconductor High Electron Mobility Transistor 20 Figure 3.1 a) A typical transistor design for the purpose of DC characterisation W, L and LD-G referred to the gate width, gate length and drain -gate. .. suitable candidate for high power and high temperature purposes, a GaN-based HEMT would thus be the choice candidate for electronic devices capable of withstanding high power and high temperature However,... purpose of DC characterisation W, L and LD-G referred to the gate width, gate length and drain -gate separation respectively b) The width of a mesa island would dictate the gate width of a transistor