Analysis and design of power electronic cell for modular power electronic systems DC AC converter configurations

... “Plug-n-Play” using standard cells 1.2.2 Conceptual Design of A Universal Power Electronic Cell Power electronic converters can be broadly classified as DC/ DC, DC/ AC, AC /DC and AC/ AC converters We can... applications: a )DC to AC inverter, b )AC to DC converter, c )DC to AC motor controller, d )AC to DC 18 boost converter and e )DC to DC boost converter PEBB-2, the second phase focuses on developing and defining... concerns for 33 Motor Filter AC /DC DC /AC Load Rec & Filter AC Power Supply DC/ DC Filter DC/ AC Motor DC Power Distribution Bus Figure 2.9: A PEBB-based Distributed Power System [5] the DPS, because each

Analysis and Design of Power Electronic Cell for Modular Power Electronic Systems: DC-AC Converter Configurations YONGHONG JIANG A THESIS SUBMITTED FOR THE DEGREE OF MASTER OF ENGINEERING DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2003 i To my dearest Yijun ii Acknowledgment The author would like to thank many people who have contributed to this work. Foremost among them is my research supervisor, Dr.Ashwin M Khambadkone and Prof. Oruganti, Ramesh, to whom I would like to record my sincere appreciation and gratitude for his valuable guidance and helpful suggestion. And also for his patience and helpfulness, which was most certainly valuable an deeply appreciated throughout the course of the work. Thanks to Mr Teo Thiam Teck, the lab technician of the Power Electronics Laboratory. Mr Teo had offered the author plenty of technical support and in many ways accelerated. And also thanks to Mr Woo and Mr Chandra of Electrical Machines Laboratory for their help with laboratory equipments. Thanks to my friends Tripathi Anshuman, Kanakasabai Viswanathan, Zhang Tao, Deng Heng, Kong xin, Low Jim Meng for their concerned support and help me without reservation iii With a deep sense of love and gratitude I thank my dearest husband Yijun. As my life partner, he gave me the most care, understanding and support during those hard moments. Last, but not least, the author would like to thank all those who have helped her directly or indirectly in this project. iv Contents List of Figures x 1 Introduction 1.1 General Statement . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 The Concept of Basic Universal Power Electronic Cell . . . . . . 1.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2 Conceptual Design of A Universal Power Electronic Cell . 1.3 The Concept Of Building Distributed Power Systems Using UPEC 1.3.1 Parallel input parallel output operation . . . . . . . . . . . 1.3.2 Parallel input serial output full bridge operation . . . . . . 1.3.3 Parallel input serial output three phase operation . . . . . 1.4 Thesis Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Literature Review 2.1 Distributed Power Systems . . . . . . . . . . . . . . . . . . 2.2 Overview Of Power Electronics Building Blocks (PEBB) . 2.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 The PEBB Concept . . . . . . . . . . . . . . . . . 2.2.3 Three Design phases of PEBB . . . . . . . . . . . . 2.3 The Investments in PEBB Program . . . . . . . . . . . . 2.3.1 Plug and Play Power . . . . . . . . . . . . . . . . . 2.3.2 Cellular Design, PEBB Partition . . . . . . . . . . 2.3.3 Hierarchical Design . . . . . . . . . . . . . . . . . . 2.4 Design Issues in PEBB System Integration . . . . . . . . . 2.4.1 Hard Switching PEBB . . . . . . . . . . . . . . . . 2.4.2 Soft Switching Techniques for PEBB . . . . . . . . 2.4.3 Power Electronics Packaging Technology for PEBB 2.4.4 EMI Issues in PEBB System Integration . . . . . . 2.4.5 Power Integration Issues of PEBB . . . . . . . . . . 2.5 Distributed Software Architectures of PEBB-based DPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 . . 1 . . 3 . . 3 . . 4 Cells 6 . . 6 . . 7 . . 8 . . 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 12 12 14 16 18 19 20 21 22 22 24 28 31 32 33 v 2.6 2.5.1 Centralized Architecture . . . . . . . . . . . . . . . . . . . . . 2.5.2 Distributed Architecture . . . . . . . . . . . . . . . . . . . . . Motivation and Objective . . . . . . . . . . . . . . . . . . . . . . . . 3 The Basic UPEC Cell 3.1 Circuit Structure . . . . . . . . . . . . . . . . . . . . . 3.1.1 The Specifications . . . . . . . . . . . . . . . . . 3.1.2 Design Consideration . . . . . . . . . . . . . . . 3.1.3 Sine Triangle PWM Scheme . . . . . . . . . . . 3.2 Control Analysis and Design for The Single UPEC Cell 3.3 Close Loop Control Design . . . . . . . . . . . . . . . . 3.3.1 Inner Current Control Loop . . . . . . . . . . . 3.3.2 Outer Voltage Controller . . . . . . . . . . . . . 3.3.3 Controller Implementation . . . . . . . . . . . . 3.4 Circuit Implementation . . . . . . . . . . . . . . . . . . 3.4.1 Power Circuit Components . . . . . . . . . . . . 3.4.2 Driver Auxiliary Circuit . . . . . . . . . . . . . 3.4.3 Layout Consideration . . . . . . . . . . . . . . . 3.5 Discussion of Simulation and Experimental Results . . 3.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 35 40 43 43 44 44 52 55 57 58 61 64 66 67 67 70 73 74 4 Distribution Power Systems - Parallel-Parallel Operation Using UPEC Cells 80 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.2 Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.3 Synchronization Scheme For Parallel Parallel Configuration of UPEC Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.3.1 Phase-Lock-Loop . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.3.2 Internal Generated Sine Reference . . . . . . . . . . . . . . . . 87 4.3.3 A New Synchronization Scheme . . . . . . . . . . . . . . . . . 90 4.4 Imbalance Problem In Power Distribution System . . . . . . . . . . . 97 4.5 Load Current Sharing Problem . . . . . . . . . . . . . . . . . . . . . 103 4.5.1 The Analysis for Load Current Sharing . . . . . . . . . . . . . 103 4.5.2 Different Scheme For Load Sharing Distribution . . . . . . . . 108 4.5.3 The Load Current Sharing Scheme Analysis Using In Parallel Parallel Configuration . . . . . . . . . . . . . . . . . . . . . . 110 4.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 5 Distribution Power Systems - Full Bridge Operation and Three Phase Operation Using UPEC Cells 121 5.1 Full Bridge Operation Using UPEC Cells . . . . . . . . . . . . . . . . 121 5.2 Full Bridge Configuration Using UPEC Cells . . . . . . . . . . . . . . 122 vi 5.3 5.4 5.2.1 Synchronization Problems . . . . . . . . . 5.2.2 The Simulation and Experimental Results Parallel Input Three Phase Output Operation . . 5.3.1 Three Phase Inverter Investigation . . . . 5.3.2 Configuration Using UPEC Cells . . . . . 5.3.3 Synchronization Problems . . . . . . . . . 5.3.4 The Simulation and Experimental Results 5.3.5 Multi-phase systems . . . . . . . . . . . . Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Network Communication Investigation 6.1 Survey of Local Area Network Architecture . . . . . . . . . . 6.1.1 Star Topology . . . . . . . . . . . . . . . . . . . . . . 6.1.2 CSMA/CD Topology . . . . . . . . . . . . . . . . . . 6.1.3 Token-Ring Topology . . . . . . . . . . . . . . . . . . 6.1.4 Token-Bus Topology . . . . . . . . . . . . . . . . . . 6.2 Deterministic Ethernet Real-Time Control . . . . . . . . . . 6.2.1 Network Requirement of Hard Real-Time Systems . . 6.2.2 Non-Determinism in Ethernet CSMA/CD . . . . . . 6.2.3 Investigation of CSMA/DCR Deterministic Collision tion Algorithm . . . . . . . . . . . . . . . . . . . . . 6.3 The Investigation Of UPEC Communication Protocol . . . . 6.3.1 Structure Of Communication Topology . . . . . . . . 6.3.2 System Overview . . . . . . . . . . . . . . . . . . . . 6.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resolu. . . . . . . . . . . . . . . . . . . . . . . . . 128 129 130 130 132 136 137 139 140 147 148 148 149 150 151 152 152 153 153 154 154 156 161 7 Conclusions 162 Bibliography 166 A Components Data Sheet List 182 B Circuit and Layout Scheme 189 vii Summary To meet the requirement of high degree of integration and standardization of modern electronic power supply systems, the easy to use power processing configuration is becoming increasingly important. The widespread use of the electronic distributed power system (DPS) has given the electronic power supply industry the opportunity to develop a standardized modular approach to power processing. One of such approach is the use of Power Electronic Building Blocks (PEBB). Power electronic building blocks (PEBB) is a new paradigm in designing power electronic systems. The main objective of the Universal Power Electronic Cell - UPEC research is to investigate and develop a standard cell concept that can be configured into AC/DC, DC/DC, DC/AC converter. Such configurations can be used in DPS to enhance power handling capability by paralleling. Redundancy and reliability can be increased if such cells are used to obtain multi-phase systems. In this thesis, the focus is on the DC/AC systems using the basic cell. The report first introduces the basic concept of the UPEC cell. The basic cell is based on the most common half-bridge leg structure because it is the commonly used switching topologies that can be found viii in AC/DC, DC/DC, and DC/AC conversion. In this report, only hard switched DC/AC converters structures are used. This kind of structure can also be easily extended to the other two converter configuration by changing the reference wave. The cell includes power semiconductors devices, the required passive components, the driver electronic circuits and the controller to get a standard, self-contained units. After introducing the basic structure and operating concept of the UPEC cell, the cell is designed to meet certain performance criteria such as the output power rating, carrier frequency and harmonic content etc. A digital closed loop controller is designed and implemented on the DSP TMS320F243 to control the function of the cell. Experimental results of the close-loop controlled P.E system are provided. Based on the analysis of the basic UPEC cell structure and development, parallel input parallel output, full bridge and three phase configurations can be implemented by using it. In the parallel-parallel configuration, the main problem is of synchronization and circulating current. The output voltage and phase angle of the respective inverters must have the same value for the parallel operation at every instant, otherwise, the circulating current will occur between the power cells. To solve the synchronization problem, we normally use the phase lock loop (PLL) method [1]. However, a simple and practical way is used to solve the synchronization problem. Using the simple serial data communication to transfer synchronization information, a good synchronization is achieved. Furthermore, it is very easy to extend the synchronization method to more cells. Parallel connection can also be realized because this ix synchronization method does not depend on the cell number and configuration. Thus full bridge and three phase connection can be realized. In the parallel-parallel configuration, the average current sharing scheme is used to solve the circulating current problem. This method can also reduce the effect of difference in circuit parameters of parallel cells. Finally, a study of communication delays and errors is carried out to bench mark the requirements of a future communication network. x List of Figures 1.1 Basic UPEC Cell Topology . . . . . . . . . . . . . . . . . . . . . . . . 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 Basic DPS Structures [2] . . . . . . . . . . . . . . . . The View of A PEBB Module [3] . . . . . . . . . . . Some of The Common Switching Topologies . . . . . A Power Electronics Building Block (Hard-switching) Power Electronic Building Block [4] . . . . . . . . . . Hard Switching PEBB With Parasitics . . . . . . . . Topology of ARCP Soft Switching PEBB . . . . . . . Topology of Improved ZCT Soft Switching PEBB . . A PEBB-based Distributed Power System [5] . . . . . Plug and Play Power Electronics System Architecture Block Diagram of Designed Application Manager [6] . Block Diagram of Designed Hardware Manager [7] . . Data Formats In Distributed Controller Network [7] . . . . . . . . . . . . . . 12 14 16 17 17 22 26 27 33 36 37 38 40 3.1 3.2 3.3 3.4 The Single UPEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Capacitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . Output L-C Filter Circuit . . . . . . . . . . . . . . . . . . . . . . . . Cut-off Frequency Simulation of The Output Voltage Total THD Vs. Carrier Frequency For 10KHz . . . . . . . . . . . . . . . . . . . . . . Pulse-Width Modulation . . . . . . . . . . . . . . . . . . . . . . . . . One-leg switch-mode inverter . . . . . . . . . . . . . . . . . . . . . . Equivalent Circuit of The Basic UPEC . . . . . . . . . . . . . . . . . Current Controller Block Diagram . . . . . . . . . . . . . . . . . . . . Unit Step Response of The Close-loop Current Control . . . . . . . . Different PI Gain Values . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Controller Block Diagram . . . . . . . . . . . . . . . . . . . . Unit Step Response of The Close-loop Voltage Control . . . . . . . . Different PI Gain Values . . . . . . . . . . . . . . . . . . . . . . . . . 43 45 46 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 . . . . . . . . . . . . . . . . . . [6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 49 53 54 57 59 60 60 62 63 64 xi 3.14 3.15 3.16 3.17 3.18 3.19 3.20 3.21 3.22 3.23 3.24 3.25 3.26 3.27 3.28 3.29 3.30 3.31 4.1 4.2 4.3 4.4 4.5 4.6 Proposed Control System Block Diagram . . . . . . . . . . . . . . . . 64 Current and Sensing Interface Block Diagram . . . . . . . . . . . . . 65 Driver Auxiliary Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 68 Driver Output Signals(experimental). (1)The top driver signal(20V/Div), (3)The bottom driver signal(20V/Div) . . . . . . . . . . . . . . . . . 69 Current and Voltage Sensing and Scaling Block Diagram . . . . . . . 70 Current and Sensing Interface Block Diagram . . . . . . . . . . . . . 71 Junction Between Two Wide Copper Tracks Is Less Inductive When Several Spaced Links Are Used Rather Than A Single Link . . . . . . 71 Configuration of Decoupling Capacitors . . . . . . . . . . . . . . . . . 72 Linear Power Path-Minimize Noise Coupling From Switching Circuits Into Input And Outputs . . . . . . . . . . . . . . . . . . . . . . . . . 72 IGBT switches output waveform (experimental).(2)IGBT switches output voltage waveform (500V/Div), (M)the spectrum analysis . . . . . 73 IGBT switch over shot voltage when turn off (experimental). (4)the bottom IGBT (500V/Div) . . . . . . . . . . . . . . . . . . . . . . . . 74 The basic UPEC output current and voltage waveforms (simulated).(i)output current(5A/Div), (ii)output voltage(200V/Div) . . . . . . . . . . . . 75 The basic UPEC output current and voltage waveforms (experimental).(3)output current(10A/Div), (4)output voltage(200V/Div) . . . . 76 The dynamic response when load changes(simulated).(i)output current(5A/Div), (ii)output voltage(200V/Div) . . . . . . . . . . . . . . 76 The dynamic response when load changes(experimental).(3)output current(5A/Div), (4)output voltage(200V/Div) . . . . . . . . . . . . . . 77 The detail of the dynamic response when load changes(experimental).(3)output current(5A/Div), (4)output voltage(200V/Div) . . . . . . . . . . . . . 77 Main Program Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . 78 ISR Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Parallel Parallel Configuration Using Two UPEC Cells . . . . . . . . 82 Two Parallel Connected UPEC Cells . . . . . . . . . . . . . . . . . . 82 The Demonstration of Counter . . . . . . . . . . . . . . . . . . . . . 89 The Flow Chart of Using GPIO Pins . . . . . . . . . . . . . . . . . . 91 The Demonstration Using Switch . . . . . . . . . . . . . . . . . . . . 92 The error voltage between two parallel parallel configuration UPEC cells’ voltages(experimental). (1)UPEC cell1 output voltage(50V/Div), (4)UPEC cell2 output voltage(50V/Div), (3)Error (V1 −V4 ) voltage(100V/Div) 93 4.7 Parallel Parallel Voltage Error VS. Time Delay of Vcarrier . . . . . . . 94 4.8 Parallel Parallel Voltage Error VS. Time Delay of Vref . . . . . . . . 95 4.9 The Flow Chart of Synchronization Using SPI Module . . . . . . . . 96 xii 4.10 The error voltage every 5 fundamental cycles’ synchronization rate(experimental). (1)UPEC cell1 output voltage(50V/Div), (4)UPEC cell2 output voltage(50V/Div), (3)Error (V1 − V4 ) voltage(20V/Div) . . . . . . . . . . 97 4.11 The error voltage every 1 fundamental cycles’ synchronization rate(experimental). (1)UPEC cell1 output voltage(50V/Div), (4)UPEC cell2 output voltage(50V/Div), (3)Error (V1 − V4 ) voltage(10V/Div) . . . . . . . . . . 98 4.12 The error voltage every 14 fundamental cycles’ synchronization rate(experimental). (1)UPEC cell1 output voltage(50V/Div), (4)UPEC cell2 output voltage(50V/Div), (3)Error (V1 − V4 ) voltage(10V/Div) . . . . . . . . . . 99 4.13 The error voltage after different L-C filter(experimental). (1)UPEC cell1 output voltage(50V/Div), (4)UPEC cell2 output voltage(50V/Div), (3)Error (V1 − V4 ) voltage(10V/Div) . . . . . . . . . . . . . . . . . . 100 4.14 The error voltage after different L-C filter(simulated). (1)UPEC cell1 output voltage(50V/Div), (4)UPEC cell2 output voltage(50V/Div), (3)Error (V1 − V4 ) voltage(5V/Div) . . . . . . . . . . . . . . . . . . . 101 4.15 Error Voltage Between Two UPEC Cells . . . . . . . . . . . . . . . . 102 4.16 The Analysis for The Variation of L-C Filter Parameters. X = ZL1 /ZL2 , C1 C2 Y = ZC1 /ZC2 , Z = ZC1Z+Z − ZC2Z+Z . . . . . . . . . . . . . . . . . . 103 L1 L2 4.17 Block Diagram of Two UPEC cells Under Single-Loop Control . . . . 104 4.18 Equivalent Circuit of Two Parallel Connected UPEC Cells Under SingleLoop Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.19 Current Sharing Block Diagram Of The Parallel Parallel UPEC Cells 111 4.20 Control Loop Diagram Using Average Current Sharing . . . . . . . . 112 4.21 Block Diagram of Two Parallel-Connected UPEC Cells Using Automatic Current Sharing Average Current Method . . . . . . . . . . . . 113 4.22 The error voltage using load current sharing control(simulated). (i)UPEC cell1 output voltage(100V/Div), (ii)UPEC cell2 output voltage(100V/Div), (iii)Error (Vi − Vii ) voltage(10V/Div) . . . . . . . . . . . . . . . . . . 114 4.23 The error voltage using load current sharing control(experimental). (1)UPEC cell1 output voltage(200V/Div), (4)UPEC cell2 output voltage(200V/Div), (3)Error (V1 − V4 ) voltage(50V/Div) . . . . . . . . . 115 4.24 The output current and voltage waveforms in parallel parallel connection (simulated). (i)Output voltage(100V/Div), (ii)Output current(2A/Div) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 4.25 The output current and voltage waveforms in parallel parallel connection (experimental). (1)Output current(5A/Div), (2)Output voltage(100V/Div) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.26 The output current waveforms in parallel parallel connection(simulated). (i)Output current(2.5A/Div), (ii)UPEC cell1 output current(1A/Div), (iii)UPEC cell2 output current(1A/Div) . . . . . . . . . . . . . . . . 117 xiii 4.27 The output current waveforms in parallel parallel connection(experimental). (3)Output current(2A/Div), (1)UPEC cell1 output current(2A/Div), (2)UPEC cell2 output current(2A/Div) . . . . . . . . . . . . . . . . . 118 4.28 The output current dynamic response when load changes(simulated). (i)Output current(5A/Div), (ii)UPEC cell1 output current(2.5A/Div), (iii)UPEC cell2 output current(2.5A/Div) . . . . . . . . . . . . . . . 118 4.29 The output current dynamic response when load changes(simulated). (1)UPEC cell1 output current(2A/Div), (2)UPEC cell2 output current(2A/Div) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 4.30 The output current and voltage dynamic response when load changes(simulated). (i)Output voltage(100V/Div), (ii)Output current(5A/Div) . . . . . . 119 4.31 The output current and voltage dynamic response when load changes(experimental). (1)Output current(5A/Div), (2)Output voltage(100V/Div) . . . . . . 120 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.15 Single-phase full-bridge inverter . . . . . . . . . . . . . . . . . . . . . Full-Bridge Single Phase Configuration Using Two UPEC Cells . . . Full Bridge Output Voltage Between Two UPEC Cells . . . . . . . . The Control Block Diagram in Full Bridge Operation . . . . . . . . . The output voltage waveforms of full bridge connection UPEC (simulated). (i)full bridge output voltage(200V/Div),(ii)Cell1 output voltage(100V/Div), (iii)Cell2 output voltage(100V/Div) . . . . . . . . . . The output voltage waveforms of full bridge connection UPEC (experimental). (4)full bridge output voltage(200V/Div),(2)Cell1 output voltage(100V/Div), (3)Cell2 output voltage(100V/Div) . . . . . . . . The output current and voltage waveforms of full bridge connection UPEC (simulated). (i)full bridge output current(5A/Div),(ii)full bridge output voltage(200V/Div) . . . . . . . . . . . . . . . . . . . . . . . . The output current and voltage waveforms of full bridge connection UPEC (experimental). (1)full bridge output current(5A/Div),(4)full bridge output voltage(200V/Div) . . . . . . . . . . . . . . . . . . . . The dynamic response of output current and voltage waveforms of full bridge connection UPEC (simulated). (i)full bridge output current(10A/Div),(ii)full bridge output voltage(200V/Div) . . . . . . . . The dynamic response of output current and voltage waveforms of full bridge connection UPEC (experimental). (1)full bridge output current(5A/Div),(4)full bridge output voltage(200V/Div) . . . . . . . Three phase inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . Three Phase Configuration Using Three UPEC Cells With Delta Load Three Phase Configuration Using Three UPEC Cells With Star Load Three Phase Vector Relation Diagram . . . . . . . . . . . . . . . . . The Control Block Diagram in Three Phase Operation . . . . . . . . 122 123 125 129 130 131 132 133 134 135 136 137 138 139 141 xiv 5.16 The phase(line-to-line) voltage waveforms of three phase connection UPEC with Delta Load Connection (50V/Div)(simulated) . . . . . . 5.17 The phase(line-to-line) voltage waveforms of three phase connection UPEC with Delta Load Connection 100V/Div(experimental) . . . . . 5.18 The phase and line-to-line current waveforms of three phase connection UPEC with Delta Load Connection (simulated). (i)Line-to-line current wavefomrs(10A/Div),(ii)Phase current waveforms(5A/Div), . . . . . . 5.19 Output Phase Current with Delta Load Connection 5A/Div (experimental) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.20 Output Line-to-Line Current with Delta Load Connection 5A/Div (experimental) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.21 The output voltage waveforms of three phase connection UPEC (simulated). (i)Output line-to-line voltage(200V/Div). (ii)Output phase voltage(100V/Div) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.22 The line-to-line voltage waveforms of three phase connection UPEC with Star Load Conncection 100V/Div(experimental) . . . . . . . . . 5.23 The phase current waveforms of three phase connection UPEC with Star Load Conncection 1A/Div(experimental) . . . . . . . . . . . . . 5.24 The line-to-line voltage waveforms of three phase connection UPEC with Star Load Connection 100V/Div(Simulated) . . . . . . . . . . . 5.25 The phase voltage waveforms of three phase connection UPEC with Star Load Connection 20V/Div(experimental) . . . . . . . . . . . . . 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 Star Topology . . . . . . . . . . . . . . . . . . . . . . . . CSMA/CD Topology . . . . . . . . . . . . . . . . . . . . Token-Ring Topology . . . . . . . . . . . . . . . . . . . . Token-Bus Topology . . . . . . . . . . . . . . . . . . . . UPEC Bus Topology . . . . . . . . . . . . . . . . . . . . Communication Hierarchy . . . . . . . . . . . . . . . . . State Transition Diagram for Communication Controller Data Format of Start-Up Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 142 143 143 144 144 145 145 146 146 149 150 150 151 155 155 157 159 xv Abbreviation and Symbols PEBB Power Electronic Building Block UPEC Universal Power Electronic Cell DPS Distributed Power Systems VLSI Very-Large-Scale-Integrated PnP Plug and Play ZVS Zero-Voltage Switching ZCS Zero-Current Switching IGBT Insulated Gate Bipolar transistor GTO Gate Turn-off Thyristor PCB Printed Circuit Board EMI Electro Magnetic Interference PFC Power Factor Correction AM Application Manager HM Hardware Manager PEOS Power Electronics Operating System ZCS Zero-Current Switching THD Total Harmonic Distortion VSI Voltage Source Inverter CSI Current Source Inverter ISR Interrupt Service Routine SPI Serial Peripheral Interface DSP Digital Signal Processor GPIO General Purpose Input and Output PLL Phase Lock Loop LAN Local area networks CSMA/CD Carrier Sense with Multiple Access/Collision detection xvi η ζ ω fs f1 ma mf kp Ti Efficiency of Power Supply Damping Ratio Natural Frequency Carrier Frequency Modulating Frequency Amplitude Modulation Ratio Frequency Modulation Ratio Proportional Gain Integral Gain 1 Chapter 1 Introduction 1.1 General Statement Throughout the world, electric power is used at an average rate of 12 billion kilowatts every hour of every day of every year [8]. With few exceptions, the majority of this electrical power is not used in the form in which it was initially produced. Rather, it is reprocessed to provide the type of power needed in the technology that is being employed. Power electronics system converts electrical power from one to another. According to an EPRI survey [9], more than 40% of the electric power being processed is passed through some forms of power electronic equipment. By the year 2010, it is expected that up to 80% of electrical power will be processed by power electronics equipment and systems. With the widespread use of cost-effective power electronics technologies, the total energy consumption can be reduced by more than 2 35%. To process such a huge amount of electric energy, power electronics and related power processing technologies have become an enabling infrastructure technology with a significant potential impact on the economy. This is manifested through the increased energy efficiency of equipment and processes using electrical power, and through higher industrial productivity and higher product quality, which results from the ability to control precisely the electrical power for manufacturing operations. Sales of power electronics equipment exceeded $60 billion each year, and another $1 trillion in hardware electronics sales [3]. Power electronics plays a major part in most industrial and commercial systems. For efficient use of power in these systems, switched mode power converters are necessary. Requirements of many of these system are unique, hence, power converters have to be specifically designed for each of them. The design includes, not only the power semiconductors devices, but energy storage elements such as inductors and capacitors. In addition, protection, signal processing and control systems have to be integrated. The whole converter system needs to be packaged for high thermal efficiency and EMC compliance. All these factors make the design of power electronic system very complex. Furthermore, the design process is compounded by strong influences of parasitic effects of different subsystems. For example, the design of magnetic components such as inductors and transformers is fairly involved process. Parameters such as operating frequency, VA rating greatly influence the design and choice of ma- 3 terial. Therefore engineering cost of power electronic systems tend to be substantial. Can these cost be reduced? Can we design a universal power electronic cell that can be programmed to perform as any of the several converter topologies? One of such approach is the use of Power electronic building blocks. Power electronic building blocks is a new paradigm in designing power electronic systems. Various concepts have been proposed under this broad umbrella. We would like to extend this idea further. 1.2 The Concept of Basic Universal Power Electronic Cell 1.2.1 Introduction In this section, a improvement concept of a versatile power electronic cell that falls along the natural boundary of technical expertise is proposed. The philosophy is to design standard cells so that a combination of such cells should be able to implement any of the widely used converter modes such as AC/DC, DC/AC, DC/DC in single phase and three phase operations. In this context, a power electronic cell is defined to consist of power semiconductors devices, the required passive components like inductors and capacitors, the driver electronics and the control. The cells are basic self-contained units. Standardization of cells and their connectivity will lead to reduction of engineering costs in power electronic systems. Once standardized 4 and produced in large numbers, the cost of this cells will be lower. Engineering implementation of power electronic systems would then be reduced to “Plug-n-Play” using standard cells. 1.2.2 Conceptual Design of A Universal Power Electronic Cell Power electronic converters can be broadly classified as DC/DC, DC/AC, AC/DC and AC/AC converters. We can further classify them as hard-switched or soft switched converters. Each of these converters consists of power electronic switches and energy storage elements. They form the power electronic circuit. The control of the switch will depend on the mode of power conversion required. Of the four topologies described above, DC/DC and DC/AC are realized using controllable switches. AC/DC and AC/AC converters have been traditionally realized using line commutated devices such as thyristors and diodes. However, these configurations lead to a poor power quality on the line side. Switched mode rectifiers and boost-type rectifiers can improve the power quality on the line side; but on the other hand, switched mode configurations for AC/AC converters have not gained much ground. However, AC/AC conversion can be carried out using an intermediate DC link. Substantial body of research exists for converters with a DC link. Therefore, we can safely say that, all converter modes described above can be realized using a basic configuration with a DC link. Using the above facts, we can conceptualize the basic cell. 5 Converter topologies with DC link can be used to realize most of the power conversion modes. Hence, we will choose a cell to have a DC link. A basic half bridge configuration with controllable switches and diodes can be used to produce DC/DC, DC/AC and AC/DC power converter modes. In addition, we add filter components such as an inductor and a capacitor; this would form the basic cell. I use a hardswitched basic cell topology to explain the concept of cells and their use in various configurations. The basic cell topology is shown in Fig.1.1. It has 6 power terminals P H L M U W P M H U W V UPEC N C N V Cbus Cbus Figure 1.1: Basic UPEC Cell Topology and a control bus. By connecting the terminal V to terminal M, and connecting the load between U and V, we can implement a basic half bridge topology. This cell can be operated either in DC/DC, DC/AC or AC/DC mode. In my research work , I concentrate on the DC/AC operation using the cell. U and W will be shorted for this configuration. The building of the basic UPEC cell will be discussed in detail in Chapter 3. 6 1.3 The Concept Of Building Distributed Power Systems Using UPEC Cells Modern electronic systems need more complex power electronic systems to meet the requirements for reliability, high density and voltage regulation. As a result, a conventional centralized power system with a single high power converter may not be optimal for the systems of the future. New trends in the field of high and medium power systems use Distributed Power Systems instead of large and lumped power converters [2]. These allow standardized designs. For these reasons, we can find that the UPEC cell’s structure is very simple. It is the basic element for many other power converter topologies which are relatively complicated compared to the cell. These standard cells can be connected to form different circuit topologies and to implement different power conversion functions. In our works, the DPS is configured with a common DC bus and produces a constant AC voltage output. This system can be built by using the basic cells in various configurations that will be described further. 1.3.1 Parallel input parallel output operation One approach to build a large power inverter system is the use of a cellular structure, in which many quasi-autonomous inverters, called cells, are paralleled to create a single inverter system [10], [11]. The use of quasi-autonomous cells means that the 7 whole system performance will not be compromised by the failure of one cell. The proposed UPEC cell exactly has the quasi-autonomous characteristics. In the parallel parallel configuration, the UPEC cells share the same input and output busses, but each cell process only to a fraction of the total system power. The frequency and phase of the paralleled cells sine output voltage should have the same values. This method is believed to be an appropriated solution to supply more reliable and flexible power. However, we also need to solve problems such as the synchronization of all paralleled cells in frequency, phase and amplitude to guarantee equalization of parallel connection without circulating current; the output current sharing of the parallel inverter to avoid internal dissipation between parallel cells more over the output voltage regulation which will cause the inverter switching interference and the output voltage oscillations [12], [13], [14]. This problem is described in detail in Chapter4. 1.3.2 Parallel input serial output full bridge operation The other approach to build a large power inverter system is to use a full bridge inverter. With the same dc input voltage, the maximum output voltage of the full bridge inverter is twice that of the half bridge inverter. This implies that for the same power, the output current and the switch currents are one-half of those for a half bridge inverter. At a high power level, this is a distinct advantage, since it requires less paralleling of devices [15]. In this configuration, the UPEC cells share the same DC input and the output is serially connected. If we let the phase difference 8 of two cells output voltage 180o degree, we can realize the full bridge operation using two standard UPEC cells. 1.3.3 Parallel input serial output three phase operation In applications such as un-interruptible ac power supplies and ac motor drives, three phase inverters are commonly used to supply three phase loads. It is possible to supply a three phase load by means of three separate single-phase inverters, where each inverter produces an output displaced by 120o (of the fundamental frequency) with respect to each other [15]. In this configuration, three UPEC cells share the same DC input and the output is connected serially in star or delta style. The details of the full bridge and three phase configurations will be discussed in Chapter 6. 1.4 Thesis Layout Chapter 1 gives a brief introduction to the concept of the universal power electronics cell (UPEC) and the concept of building the distributed systems. It also introduces the structure of this thesis. Chapter 2 reviews the distributed power system development state of the research results related with PEBB such as the concepts, development, investment and the distribution structures of the PEBB. It also gives the difference between the PEBB 9 and UPEC and the aims of this research work. Chapter 3 is mainly about the analysis, simulation and building of the basic UPEC module in detail. The contents include mathematic model analysis, control parameter derivation, circuit implementation, controller programming flow chart and the comparison of simulated and experimental results of the cell. Chapter 4 and Chapter 5 form control part of the thesis. These two chapters analyze the possibilities of building the distributed power systems using UPEC cells from the power electronics (hardware) level. In Chapter 4, we connect the UPEC cells in parallel parallel mode. In this mode, the synchronization and the output load current sharing between paralleled cells are the most important problems we need to solve. After solving the synchronization problem, In Chapter 5, we can realize the full bridge and three phase operations according to the same principle. Chapter 6 investigates and discusses the possible communication protocols between the UPEC cells from the viewpoint of power electronics. 10 Chapter 2 Literature Review 2.1 Distributed Power Systems Unlike modern digital technology, which utilizes an array of developed components or cells to build a system, modern power systems lack a high degree of integration and standardization [16]. Power electronics products are essentially custom-designed, with a long design cycle time. The equipment is designed and manufactured largely using non-standard parts [3]. As a result, designers are often forced to build entire systems from scratch each time, which is costly in engineering time as well as system reliability [16]. Manufacturing processes are labor-intensive, resulting in high cost and poor reliability. The need for low-cost, high-reliability, easy to use power processing system is becoming more and more pronounced. Industrial firms are under constant pressure to produce power electronics products that are more power density, dependable and 11 durable, smaller in size, lighter in weight, and less costly to the consumer. Without a significant paradigm shift in power electronics technology, those objectives cannot be achieved [3]. The widespread use of the DPSs has given the power supply industry the opportunity to develop a standardized modular approach to power processing. This approach will enable significant improvements in the design and manufacturing process and enhance system performance and reliability. DPSs offer many advantages to power system designers: high power capability, high efficiency, reliability, modularity, redundancy, reduced development cost and tightly regulated output voltage as needed by today’s sophisticated electronic loads. For these reasons, DPS are becoming more and more common in many industries. According to ref.[2], the basic DPS structures may be classified as follows: cascading, paralleling, source splitting, load splitting and stacking. These structures are shown in Fig.2.1. These structures are based on a set of Power Processing Units(PPU). Traditionally, most PPUs are DC/DC PWM switching converters. With the introduction of the DPS, why not develop an integrated systems approach to standardize power electronics components and packaging techniques in the form of highly integrated PPUs in order to provide significant improvements in quality, reliability and cost of power electronics systems? The PEBB concept is the one to meet this challenge. 12 Vi PPU1 Vb Vo PPU2 Vi1 PPU1 Vs RL Vs1 Vb Vo PPU3 a) Cascading RL Vi2 PPU2 PPU1 Vs2 Vi Vo PPU2 Vs d) Source Splitting RL PPU3 b) Paralleling Vi Vo1 Vi PPU1 PPU2 Vi PPU3 R1 R4 PPU2 Vi PPU1 RL1 Vb Vs1 Vs2 Vs3 R2 Vs Vo2 R3 PPU3 R5 RL2 c) Load Splitting E) Stacking Structure Figure 2.1: Basic DPS Structures [2] 2.2 Overview Of Power Electronics Building Blocks (PEBB) 2.2.1 Overview The Office of Naval Research (ONR) is developing power processors – Power Electronic Building Blocks (PEBBs) to achieve: increased power density, “user friendly” design (“plug and play” power modules), and multi-functionality. Digital controls, integrated with higher frequency and more robust power circuits, enable modular power systems with lower size, weight, and cost – while increasing performance [17]. 13 It is expected that the impact of improvements in power electronics technology and system integration via the PEBB approach can be compared to the impact realized by improvements in very-large-scale-integrated (VLSI) circuit technology. Applications of VLSI circuit technology enabled rapid advances in computer and telecommunications equipment, accompanied by a steady increase of the levels of standardization, volume and manufacturing ability and a decrease in manufacturing cost. The PEBB approach will follow suit. It makes possible to increase levels of integration in the components that comprise a power electronics system-devices, circuits, controls, sensors and actuators-integrated into standardized manufacturable subassemblies and modules that, in turn, are customized for a particular application [3]. While the need to develop PEBB and power processing using an integrated system approach is clear, the task of developing PEBB components and processes suitable for standard use in customized power electronics applications is significantly more complex than for low-power VLSI circuits. Issues unique to power electronics include the use of high-current injection devices, the monolithic integration of high-voltage power devices and low-voltage devices for controls and sensors, the interconnection of high-power devices and control devices on a common substrate, thermal management, inductance and capacitance minimization in three-dimensional device packaging, and the integration of passive high-power components. Successfully addressing these wide-ranging, multi-disciplinary issues is a prerequisite for realizing the full potential impact of power electronics [3]. 14 2.2.2 The PEBB Concept Power electronics building blocks, or PEBBs, are integrated subassemblies or modules capable of processing electric power. A PEBB is not a specific semiconductor device, a passive component, or a circuit topology. A typical PEBB may look like the one shown in Fig.2.2 [3]. Although it looks similar to a typical commercially available Power Port (Output) Communication Port, System Control Communication Port, System Control Power Port (Source) Figure 2.2: The View of A PEBB Module [3] power semiconductor module, the inside of a PEBB contains much more. It includes gate drive, level shifting, sensing, protection, power supply and passive components, in addition to power semiconductor devices [3]. It integrates all these technologies of electrical, mechanical and thermal denominators [17]. The goal of the PEBB development is to create a power processing component that moves most of the design, away from specific circuit topology and power electronic switch and associated inductors, capacitors , and other ancillary component selection to a systems level [18]. As a building block, a PEBB has two types of interface ports for interconnections: 15 power ports and communication ports [3]. Depending on the instructions given to the communication ports, the PEBB can function as a DC/DC converter, an AC inverter, a synchronous rectifier, or a motor controller. Several PEBBs can connect together through these ports to form power electronics systems as simple as small DC/DC converters or as complicated as large distributed power systems. Multiple PEBB modules working together would perform system-level functions, such as voltage scaling, energy storage and conversion, and impedance matching [18]. Like a set of children’s interlocking blocks, PEBBs will be a rational and simple set of blocks and procedures that most any designer or architect can use to build electrical systems [17]. The essential design feature for PEBB is its commonality. The ultimate design goal would be to design as few as possible common PEBBs for most of the applications. In widespread applications of power electronics, a minimal group of power semiconductor switch configurations could satisfy most application requirements in a wide power range. Even though it is impossible to find one or a few switching topologies that can cover all applications, these minimum-complexity PEBBs could be combined with other components to assemble most of the common power converters. Fig.2.3 shows some of the commonly used switching topologies that can be found in AC/DC, DC/DC and DC/AC conversion. All converters in Fig.2.3 consist of the half-bridge leg structure as the building block. In this case the voltage can be applied bi-directionally, and the current flows only in one direction. 16 Vo a b c AC/DC Boost Rectifier Vg a b c Vg Vo DC/DC Converter DC/AC VSI (Inverter) (a) Voltage source converters a b c Vo Vg AC/DC Boost Rectifier a b c DC/AC CSI (Inverter) (b) Current source converters Figure 2.3: Some of The Common Switching Topologies Therefore, the half bridge inverter is defined as a PEBB and will be integrated as one three-terminal component as shown in Fig.2.4 [19]. 2.2.3 Three Design phases of PEBB According to refs.[17], [20] and [21], there are three design phases of the PEBB program. 1. PEBB-1, the first phase demonstrated that multiple application could be sat- 17 Figure 2.4: A Power Electronics Building Block (Hard-switching) isfied using the same set of hardware. Each application had its own set of software instructions. PEBB-1 proved that a single set of hardware could perform many functions. There are five power port in the first PEBB device - 2 DC and 3 AC/DC ports as shown in Fig.2.5, also see reference [22]. This device + - PEBB A B C Comm [0..x] A [0..x] D [0..x] N Figure 2.5: Power Electronic Building Block [4] corresponds to a three phase bridge. In addition to the power ports, there is a communication bus, an analog bus and a digital bus. Making only external connection changes, PEBB-1 demonstrated the following applications: a)DC to AC inverter, b)AC to DC converter, c)DC to AC motor controller, d)AC to DC 18 boost converter and e)DC to DC boost converter. 2. PEBB-2, the second phase focuses on developing and defining PEBB form. PEBB form is defined primarily by packaging considerations such as thermal, EMI, interconnections, interfaces, communications, sensors, control, manufacturing economics, reliability, passive devices, etc. PEBB-2 will demonstrate higher-power, faster-switching devices and micro electronic integration. 3. PEBB-3, will demonstrate a fully optimized PEBB prototype in form, fit, and function. The critical technological improvements manifested in PEBB-3 are the use of two-sided cooling, ultra-fast turn-off thyristors, distributed/integrated control architecture with software configuration and control. A system designer, with minimal power background, will be able to construct an power electronic system by using these standard-building blocks, quickly, simply, reliably. 2.3 The Investments in PEBB Program Over the past five years, the U.S.Navy has invested in an array of power electronic technology via the PEBB program. This investment is crucial to existing and future Navy ships and is also crucial to the power electronics industry. Like the Internet, the PEBB program focuses on core issues and attempts to assure that future US Navy requirements can be fulfilled from commercial-off-theshelf technology. Ideally, this is a win-win situation. The Navy wins by getting 19 affordable power electronics. The power electronic industry wins by getting support for core science and technology, which would be otherwise unaffordable. According to ref.[4], many modern paradigms have been studied for adaptation to power electronics throughout the PEBB program. They are open plug and play architecture, cellular design, hierarchical design, integration, and concurrent engineering. 2.3.1 Plug and Play Power The idea of an open plug and play architecture is to build power electronics systems in much the same way as personal computers. Power modules would be plugged into their applications and operational setting made automatically. The application knows what is plugged into it, who made it, and how to operate with it. Each power module maintains its own safe operating limits. Realization of this vision will require a community to develop standard interfaces and protocols. The benefit of it is to allow each section of the power equipment to be independent of the others. There are two motivations for plug and play architecture. One is for lower cost and increased application. The demand for new power electronics products exceeds the resources to supply them. The next generation engineer want to design systems on their computers and want power parts to come together like their PC components do. Open architecture multiplies the designer efforts and makes his expertise available for many more applications. Furthermore, the partitioning allows a focusing of efforts within the partitions and the development of high volume processes for partitioned 20 technologies. Both the increased utilization of resources and high volume processes lead to lower cost. “Return-on-investment” is another motivation. Open plug and play architecture allows upgrades within each partition. “Time-to-market” can be shortened by focusing on a partition rather than the whole system. A new partition is inserted with other parts to make a new product. This is just like upgrading a PC with a new video board based on a new “sub-micron” IC manufacturing process. 2.3.2 Cellular Design, PEBB Partition There would be three different levels of PEBBs according to the power range: switch cell and passive device-level PEBBs for high-power levels greater than 1MW; phase-leg PEBBs for medium power levels greater than 100KW and less than 1MW; converter-level PEBBs for low power levels less than 100KW. Each of these primary blocks are made of other basic blocks, such as: filter, power switching, and control. The power levels that define the low, medium, and high power boundaries will change as technology changes. However, these primary blocks have electrical relationships, which transcend power ratings. These simple relations lead to a cellular description or organization of power electronics. The bridge, phase leg, and switching cell are and will be primary power electronic building blocks and thus “well posed” candidates for primary units of integration. Finally, these blocks would be snapped together to form equipment and 21 systems. 2.3.3 Hierarchical Design Integration and snapping elements together require intelligence and hierarchical control. Control partitions need to be defined that compliment the spatial partitions or blocks. There needs to be enough intelligence and control embedded into a switch cell or two-terminal PEBB to enable them to be snapped together to form higher order PEBBs. The task is to define the functions and interface requirements for each of these partitions. Protocols for information transmitted across each interface need to be defined. BIOS and operating systems that apply to power equipment need to be developed. I/O and operating systems for power electronics must be highly reliable and capable of real time performance. At this point, a generalized control hierarchy boils down to four controllers as follows: • Power switch controller • Topology of circuit controller • Application controller • System controller Each of these controllers is programmable and multi-functional. 22 2.4 Design Issues in PEBB System Integration The PEBB approach is not just a process of standardization; it is also a process of integration. The resulting PEBBs should have small size, light weight, high reliability, and easy system-level configuration. To achieve these basic requirements, the following sections address the issues related to increasing the switching frequency, reducing package parasitics, improving the thermal management and reliability, and providing flexible and intelligent system configuration [3]. 2.4.1 Hard Switching PEBB The equivalent circuit of Fig.2.4 is shown as Fig.2.6. The parasitic inductance is Lstray + + Ipebb Is Vs - Vdc Cdclink Lstray - Figure 2.6: Hard Switching PEBB With Parasitics mainly the stray inductance between the DC link and PEBB since the small internal PEBB parasitic inductance can be ignored. Based on the Eq.2.1 VL(t) = Lstray di dt (2.1) 23 principle, the parasitic indectance will cause a huge voltage overshoot because of the rapidly changing current at IGBT turn off. The voltage spike could kill the device at high power. There are two ways to alleviate this problem: (1) slow down the current changing or force it to zero before switch turn off, (2) add a clamping capacitor to absorb the rapidly changing current of the device and thereby reduce the rate of change of current in the parasitic inductance [19]. For hard-switching PEBB, a large, high frequency clamping capacitor is closely added to the PEBB module. Moreover, the capacitor will cause some problems: high frequency ringing at the PEBB terminal and some high frequency loops with the parasitic inductance and the clamping capacitors of others. Additionally, the high switching loss problem is more concern for high power applications, since it will limit the switching frequency and prevent reduction in the size and cost of passive components and limit the bandwidth of control loops. For IGBTs, the turn-off loss is dominant because the turn-off current switching has a delay with respect to the junction voltage and the turn-off current is always larger than the turn-on current. To reduce hard switching voltage overshoot, a clamping capacitor is used. To reduce hard switching loss, a snubber directly in parallel with the device is sometimes used. However, the snubber makes the turn-on reverse recovery worse and then the total switching loss may be higher. 24 2.4.2 Soft Switching Techniques for PEBB As is well known, soft switching techniques can be used to alleviate switching losses/stresses and increase the switching frequency of converters. To meet the stringent requirements, soft switching techniques will have to be integrated into the PEBB. But PEBB soft switching is quite different from conventional soft switching. Conventional soft switching techniques always concern the device itself. For PEBB, it should be able to reduce not only the loss and stresses of the main devices, but also the loss and stresses of PEBB. Soft Switching Techniques Investigation There are many soft switching topologies from which to choose. Soft switching techniques have evolved from resonant converters (RC), quasi-resonant converters (QRC), multi-resonant converters (MRC), soft switching PWM converters and softtransition PWM converters, including zero-voltage switching (ZVS) and zero-current switching (ZCS). ZVS reduces the switch turn-on loss by forcing the switch voltage to zero prior to its current flowing, while ZCS reduces the turn-off loss by forcing the switch current to zero before its collector-emitter votage increases from zero to turn-off static value. For medium to high power applications, ZVT and ZCT are more suitable than other soft switching techniques, since they combine the advantages of PWM control (i.e. minimum switch static voltage/current dynamic and minimum circulating energy), and the advantages of soft switching techniques (i.e. low switch- 25 ing loss and low dynamic transition). For PEBB application, conversion systems is usually from medium to very high power level, preferably with the insulated gate bipolar transistor (IGBT) and the gate turn-off thyristor (GTO). The major turn-off loss although the turn-on loss cannot be ignored in high power application. Hua’s ZVT topology in [23] eliminates the main switch turn-on loss and diode reverse recovery. But its auxiliary switch is hard switched at high current. The coupled inductor ZVT proposed in [24] reduces the auxiliary switch turn-off loss as an improvement of [23]. However, the design of the coupled inductor is complicated. The auxiliary resonant commutated pole (ARCP) converter [25] can achieve zerovoltage for all main switches without significant modification to the hard-switching modulation scheme. The advantages of ARCP is that the auxiliary switches block only half the dc link voltage and are turned off under zero current conditions and therefore have a low power loss. The ARCP is one of the best ZVT topologies and a preferred soft switching technique for some specific applications. Zero-current transition techniques can significantly reduce turn-off loss and di . dt The ZCT scheme in [26] eliminates the main switch turn-off loss. However it cannot help the switches reduce the diode reverse recovery and turn-on loss. Moreover, the auxiliary switch is hard turned off. To get rid of these problems, a newly proposed ZCT in [27] is very attractive for medium to high power application. This ZCT topology can not only eliminate the main switch turn-off loss but also reduce the turn-on loss and diode reverse recovery problem significantly. 26 ARCP soft switching PEBB The ARCP ZVT topology is shown in Fig.2.7. The turn-on losses of ARCP are I S1 Vi/2 Lr + Cr Vs - sx1 Vi/2 Cr Figure 2.7: Topology of ARCP Soft Switching PEBB very small compared to the hard switching and the turn-off losses are also reduced, but not by much. The switching frequency limitation of the device under ZVT is about 16KHz under the same operation conditions as hard switching. One additional advantage of ARCP is that the resonant tank loss is small due to zero-current switching of the auxiliary switches. However, ARCP ZVT has the following shortcomings: (1)turn-off loss is still high and so total switching loss reduction is not satisfactory; and (2)To eliminate the hard turn-off problem, large snubber or additional clamping capacitors are needed. The larger the snubber capacitance, the longer the auxiliary commutated period, and the higher the resonant loss. Besides, both snubbers and clamping capacitors have additional losses. The snubber and clamping capacitors have a similar effect on the PEBB 27 terminals and DC link as in hard switching due to the high frequency loops formed by the capacitors and the parasitic inductance in DC buses and PEBBs. Therefore, the interaction phenomena of ARCP PEBB are similar to the hard switching PEBB. In summary, ARCP is good for switch turn-on and reduces the turn-on switching loss significantly, but for PEBB application, the terminal high frequency noise and high turn-off loss are potential drawbacks. Improved ZCT soft switching PEBB The ARCP ZVT topology is shown in Fig.2.8. The related switching frequency I D + Lx Vi Cx S Sx Vo Dc Figure 2.8: Topology of Improved ZCT Soft Switching PEBB limitation is about 40KHz. With the help of a low power auxiliary zero-current switching circuit, the main switches are turned off under zero-current conditions, practically eliminating turnoff switching losses. The turn-on current of the main switches is also reduced to approximately zero so that turn-on loss and reverse recovery of the main switches 28 are significantly reduced. Therefore, the proposed ZCT converter has a much lower switching loss than in a conventional converter and can operate at a much higher switching frequency and achieve much higher density because of smaller passive components. Moreover, because the auxiliary switches are turned on and off with zero currnt, the auxiliary loss is lower and the efficiency of the ZCT converter can be imporved. However, the parasitics will not be able to affect the terminal performance of the ZCT PEBB, since it does not have a capacitor in parallel with dc link or devices in the PEBB module. Due to the zero-current turn-off, the snubbers and clamping capacitors is eliminated in ZCT PEBBs, thus completely eliminating the high frequency noise. In summary, the ZCT PEBB has the following advantages compared with ZVT PEBB: switching losses are significantly reduces; high frequency operation is capable; PEBB high frequency terminal noise is eliminated; and there is no possibility of interaction between ZCT PEBBs and system because there are no high frequency loops without the clamping capacitors. 2.4.3 Power Electronics Packaging Technology for PEBB The size and design of a packaging layout, and the kind of packaging technique used are determined by a lot of factors. Some important factors include, but are not limited to: Materials: The thermal capacity of the materials, the mismatch in Coefficient 29 of Thermal Expansion (CTE) among different layers, their insulation properties, the dependence of the properties of the material on temperature, humidity are some factors that effect the layout. Devices: The losses in the device like the switching losses, conduction losses, the reverse recovery of the diode effect the ratio of the size of the footprint of the die to the footprint of the module. Application: The kind of application that the device has been manufactured for plays a crucial rule in determining the layout. Some applications involve constraints on space, size, and the kind of ambient temperature that the module would work under. Constraints may also come in the form of type of cooling that is used. All these factors go a long way in determining the layout design and the kind of packaging technique that can be used. For a typical power electronics system, individual power devices are mounted on the heat sink, and the driver, sensor and protection circuit are implemented on a printed circuit board (PCB) and mounted on top of the power devices. In addition, a control circuitry and a microprocessor board are mounted on top of the driver board. The manufacturing process for such equipment is labor-intensive, the cost is high, and the reliability is low. Some companies have developed a high level of integration in which power semiconductors in die form are mounted on a common substrate with wire bond. The associated drivers, protection and sensors are still realized in the form of a high-density 30 PCB, using surface-mounted components and then packaged inside the plastic enclosure with the power devices. But there are fundamental limitations to the existing packaging approaches. References pointed out that the lifetime of wire-bonded plastic power modules is limited only to a few years [28]. First of all, the interconnection wire bond is known to be unreliable. One of the frequent failure modes is the detachment of the wire bond from the semiconductor die due to electrical and thermal fatigue. The thermal management in this type of packaging is poor. The heat generated in a semiconductor die is transferred through its substrate onto the heat sink. Therefore, this form of packaging is primarily limited to low-power applications. In addition, the parasitic inductance and resistance associated with bonding wires and terminations are excessive, which severely limits the electrical performance of the modules. To resolve these issues, bond-wireless technologies has to be developed and deployed. Currently, there are several interconnection technologies under development. One is the metal posts interconnected parallel plate structure (MPIPPS) that uses metal (copper) posts for interconnecting devices as well as joining the different circuit planes together [29], [30], [31], a technology similar to the flip-chip technology used in today’s IC packaging that utilizes low-profile solder bumps as current-carrying interconnects to achieve negligible parasitic inductance and capacitance [32], a 3-D thin-film power overlay technology that claims to have significant performance, reliability and cost advantages over conventional wire-bond modules [33], [34], [35]. 31 2.4.4 EMI Issues in PEBB System Integration Because of high dv/dt, di/dt and currents, EMI is one of the most important system integration issues. One topic under investigation is how should the PEBB switching cell be implemented in order to reduce or eliminate the high frequency ringing associated with parasitic parameters in the circuit and the high dv dt and di dt caused during switching. One method to reduce the ringing on the PEBB input is to use torpedo-shaped waveforms rather than square wave pulses with high frequency edges. This can be implemented using soft-switching techniques mentioned in 2.4.2. Another concern of the distributed power system is the interaction between PEBBs. Many of these interactions are the primary source of system instability. For example, the interaction between input filter and closed-loop converter is a well known phenomenon which is caused by negative impedance of a regulated converter [36]. With the proliferation of power electronic systems, radio frequency EMI generated by power converter is also a serious concern. The chief cause of increased EMI is higher device switching speed. Audio frequency EMI is produced by modulation strategies and when conducted through parasitic paths can cause damage to motor windings and machine bearing [37]. The EMI problem is exacerbated by the recent trend towards higher efficiency machines with lower leakage inductances. It is possible to reduce the common mode voltage (a major source of EMI) produced by any inverter modulation scheme in a hard switched topology by a new scheme proposed in [38] which involves a modification of the three phase VSI topology. 32 During the design process of a PEBB, detailed device and integrated gate drive module models can be used to predict and prevent EMI generation. One coupling path for conducted EMI is the capacitive path formed by the heat sinks between the devices and chassis. With integrated gated drives and sensors EMI problems are likely to worsen. Opto-coupling of all interface signals is a likely solution for some of the EMI problems. 2.4.5 Power Integration Issues of PEBB Using these various design techniques, the resulting PEBBs can be very compact and flexible. They can be easily used to build various types of power converters. For an individual converter, the control design is very straightforward and there are not many system-level issues. But when a number of converters are put together into one system – such as the dc distributed power system (DPS) shown in Fig.2.9. – the compatibility of converters becomes a major issue. There are many converters on the DC bus of DPS. For a high-power application, the DC bus is fed through a bus regulator, which regulated the dc bus and performs power factor correction (PFC) [39] to the ac source. The downstream converters may include single or multiple-phase inverters, DC/DC converters, energy storage components and various loads [40], [41]. Even the subsystems may be well designed for stand-alone operation [42], [43]. Unlike the commercial off-line utility ac power supply, dc bus stability and system interaction are among the greatest concerns for 33 Motor Filter AC/DC DC/AC Load Rec & Filter AC Power Supply DC/DC Filter DC/AC Motor DC Power Distribution Bus Figure 2.9: A PEBB-based Distributed Power System [5] the DPS, because each converter subsystem is designed only at its individual box level. 2.5 Distributed Software Architectures of PEBBbased DPS Power electronics has reached the point where further advancement, in terms of wider application of converters can hardly be achieved unless the community is presented with easy to use of the shelf, reliable and flexible power electronics modules [17], [44], [45]. In order to fulfill these requirements, future power electronics converters should have several predominant features, such as: • A high level of integration, to improve reliability and lower costs 34 • Flexibility, to provide the necessary level of system adaptability and multifunctionality • In-circuit programmability, to allow for simple software and hardware reconfiguration and use of one standardized module in different applications and • User-friendless, to enable the wider engineering community to create their own applications, thus focusing engineering efforts towards system-oriented design 2.5.1 Centralized Architecture What is needed to bring the whole concept to its full potential is a general solution for the controller that will be able to support all necessary functions. The standard method of controlling a power converter is with a centralized controller, as explained in [46]. This board typically handles the outer and inner-loop control of the power converter. This approach has several drawbacks with perhaps the biggest one being the large number of point-to-point signal links that connect power stage and sensors on one side with the centralized controller on the other. A fault in the controller will cause a complete system shut-down and the controller must be replaced or repaired. This makes maintenance of the converter and controller more expensive. Upgrading the system, for example the power rating of the converter, sometimes require a redesign of the interface to the modules, as well as the measurement unit. Fault detection is less reliable, due to the feedback paths of the current, voltage and status 35 feedback signals. Furthermore, the signals in typical power electronics systems come in variety of different formats and are transmitted through a variety of physical media. This makes the standardization and modularization of power electronics systems and subsystems very difficult, if not impossible. The trend is therefore shifting towards integrated control [47], [48]. 2.5.2 Distributed Architecture The concept of a distributed controller is widely accepted in motion control and factory automation system [49]. In computer research, there have been many mature technologies addressing similar issues. For example, an operating system [50] manages system resources, and handles the interfaces to all kinds of peripherals. The object-oriented technology [51] provides a successful way to both reduce software design complexity and modularize software. Plug and play (PnP) [52] technology gives a computer system the capability of automatic configuration, so that the system construction becomes much user-friendly. In addition, parallel or distributed computing cluster can be used to build up super computing facilities. The concept of PEBB provides a way to hardware standardization of power electronics systems. Based on PEBB concept, some work has already been done regarding the control and communication issues where a distributed controller has been implemented at the converter level. Malapelle et al. [53] proposed a distributed digital controller for high-power drives. They partitioned the system controller into a reg- 36 ulator and a bridge controller, which were connected via a relatively slow parallel bus. Toit et al. [54] have proposed a control structure where phase-leg controllers are connected to a higher-level controller through a (2.5 Mbits/sec) daisy-chained fiber optic link. In their structure the current control is implemented locally in a phase-leg controller, while the voltage control is implemented in a higher-level controller. Hierarchical Structure All together, in the network topology, the control software will be functionally divided into hierarchical levels. Fig.2.10 shows a way to functionally divide the control User High level Control Application Manager (AM) Hierarchical Power Electronics System Control Software Hardware Manager (HM) PEBB Hardware Manager (HM) PEBB Hardware Manager (HM) PEBB Figure 2.10: Plug and Play Power Electronics System Architecture [6] in power electronics systems. In this hierarchical architecture, the control software is divided into 3 hierarchies high-level control, application manager (AM) and hardware manager (HM) [6]. The division is based on functionality. The high-level control performs tasks at the system level, such as responding to user’s commands, coordinating 37 performances between PEBBs, and monitoring system execution, etc. Application Manager Fig.2.11 shows the block diagram of application manager (AM). An AM is designed Converter real-time control subsystem Device Detector Device Registry Driver Installer Configuration Manager P E O S Information Dispatcher Driver 1 Driver 2 ....... Driver n Figure 2.11: Block Diagram of Designed Application Manager [6] to provide system flexibility and software re-configurability, specifically to perform higher-level control algorithms and supervisory tasks. An embedded operating system dedicated for power electronics systems, named power electronics operating system (PEOS) [6] is introduced. The whole control software systems at AM are composed of two subsystems: converter real-time control subsystem and PEOS. The converter real-time control subsystem can be seen as an object, and is appli- 38 cation specific. A converter real-time control object is invoked once every switching period. It may have many sub-objects, such as sensor reading, filters, regulators, etc. Different software object combinations implement different applications. While the embedded real-time PEOS provides basic system services, such as system configuration, system resource allocation and maintenance, communication with software objects at other hierarchies, etc. The PEOS can be optimized for different applications. It is the embedded PEOS that makes the converter control algorithm truly independent of the infrastructure of the HM level. Hardware Manager Fig.2.12 shows the block diagram of hardware manager (HM). An HM is responsi- GATE DRIVER& FAULT SENSING ALTERA 10K EPLD TAXI RECEIVER TAXI TRANSMITTER ADC ISOLATED POWER SUPPLY CURRENT, VOLTAGE &TEMP SENSORS GATE DRIVER& FAULT SENSING GATE DRIVER& FAULT SENSING Figure 2.12: Block Diagram of Designed Hardware Manager [7] ble for hardware related tasks such as: PWM generation, low level module protection, 39 communication and sensing of all key analog variables. Depending on the power level and system requirements the hardware manager can be designed for different power converter topologies or even sub-topologies. Once the communications interface is defined, this method of control partitioning allows the selection of the application controller based upon the application requirements and the hardware manger complexity based upon the topology and performance criteria. Both of which are programmable and reusable. Communication Link One of the gears that make the distributed controller system flexible, open, and modular is the communication protocol [55]. The more information we communicate the more flexible a system we get, but since the bandwidth of the communication channel is limited, a trade-off has to be established [7]. Two basic types of information are being communicated through network: realtime data, exchanged on switching cycle level, and initialization data exchanged during the system power up. Data that is being communicated from the application manager to the hardware manager is desired phase leg duty cycle and switching period. Feedback data is provide from the hardware manager to the application manager in the form of current, voltage, temperature and status information. The format of the data packets that is being transmitted through the network is shown in Fig.2.13. The specific number of bytes always follows a command that 40 3 0 7 command 0 40 address field 0 7 data field 0 error code a) data frame 3 0 7 command 7 0 7 address field n address field n-1 7 ............ 0 address field 0 b) synchronization frame 3 0 command c) command frame Figure 2.13: Data Formats In Distributed Controller Network [7] allows a receiver to identify the type of incoming data. 2.6 Motivation and Objective As seen in this chapter, the research activities in the PEBB based distributed power system have been presented. Within this area itself, the scope is wide including topics such as: • The concept of the PEBB including three design phases to perfect the concept. • The development and investment of PEBB program including Plug and Play, Cellular Design and Hierarchical Design. • The different design issues of PEBB system including hard-switching, soft- 41 switching, packaging, EMI and integration issues. • The spirit of the PEBB system: the distributed software structure of the PEBB including the hierarchical structure, application manager and hardware manager. However, in order to limit the scope of the research to a reasonable extent, the main objectives of the present research are to • Propose standard cell concept to meet the requirement of distributed power system • Develop designs and control process in order to achieve various DC/AC converter configuration. The objective in proposing new standard cell concept is to • The design starting point for the new paradigm, UPEC, is the same as PEBB module. They all include power devices, gate drive, sensing, protection, power supply, passive components and the micro controller. But in the new concept, we will try to find the common points of DC/DC, DC/AC, AC/DC converter circuits and build a standard cell which can realize the three operations with minimum components. • In the software architecture aspect, make the control methods and communication protocols more simple and practical. The distributed controller discussed 42 in PEBB proposes a new control partitioning that falls along the natural boundary of technical expertise. Network system engineers focus on the higher level communication protocols, control engineers focus on the application and system issues, while power electronic engineers focus on the power conversion hardware [7]. As more information is communicated the system becomes more flexible. However, the probabilities of the errors and collisions would also increase. We need a close cooperation of different fields of engineering to perfect the whole PEBB systems. But if we just want to use it in industry such as motor and drive control, why not design a new sub-system which is more simple and more suitable for the industry use. In this new system, we can download the whole functions and programs into each cell and to operate it using simple command. The communication protocols will become more simple and it will reduce the data collision problems. The new system will reduce the design cycle, human sources and will be more efficient. In order to achieve the desired objectives a new approach to modular systems based on a unit power electronic cell will be presented. Such an approach can lead to a new paradigm in design of industrial and commercial distributed electronic power supply systems. 43 Chapter 3 The Basic UPEC Cell 3.1 Circuit Structure The single UPEC model is shown as Fig.3.1. In this configuration, U and W P H current measure + Vin - L M C N U W V + Vo - voltage Cbus Communication Bus Figure 3.1: The Single UPEC should be connected together. The cell works as a DC/AC inverter. measure 44 3.1.1 The Specifications The full technical data for the proposed inverter is specified below: • DC input voltage: 600V • AC output power rating: 1KW • AC output voltage: 240V /50Hz • Carrier frequency: 10kHz • Harmonic content: less than 5% • Load: linear resistive load 3.1.2 Design Consideration Input Capacitor Design In the basic UPEC cell structure, two equal capacitors are connected in series across the dc input and their junction at a mid-potential, with a voltage 21 Vd across each capacitor. Sufficiently large capacitance should be used such that it is reasonable to assume that the potential at point M remains essentially constant with respect to the negative dc bus N . The input capacitor circuit is shown as Fig.3.2(a). Fig.3.2(b) illustrates the relationship between the capacitor voltage and the voltage holding time. ∆Vin means the input voltage dropping value. ∆t(t0 − t1 ) means the hold-up time when the input voltage drops to a selected value. 45 P Vin + Vin C1 Vin RL M C2 N (a) (b) to t1 Figure 3.2: Input Capacitor Circuit The output load RL can be calculated using the following equation: RL = Vin2 P/η η– efficiency of power supply. In the ideal situation, we will define the value 1.0. The energy in the load RL can be calculated as the following equation: ∆Q = C ∗ ∆Vin = I0 ∗ ∆t = I0 ∗ (t1 − t0 ) = I0 ∗ Tk    1   = C11 + C12  C          Tk = hold − up time     Io = the load current           Vin = V1 + V2 = Q1 + Q2 C C 1 We Assume δ = 2 ∆Vin Vin C= Tk ∗ I0 ∆Vin ∗ Vin Vin = If we chose δ = 10% and Tk = 1/f = 20ms: C ≈ 555uF Tk δ ∗ RL 46 The explanation above is not for control design, but for explanting the choice of DC link capacitor using hold-up time. Output Filter Design In order to get a sinusoidal voltage output, it is desirable to add a L-C filter between intermediate bus (output of the inverter module) and the output of the system. An L-C filter can be used to provide good reduction of the switching ripple, while maintaining adequate stability margins under a wide range of loads. • Output filter analysis The output L-C filter circuit is shown as Fig.3.3. The low-pass L-C filter is used at the inverter output side to eliminate the harmonics caused by the pulse L RL i Vin i2 i1 C R Vo Figure 3.3: Output L-C Filter Circuit modulation of the voltage waveform. For the design of L-C low-pass filter, the cut-off frequency is used to eliminate most of the low order harmonics. Higher the cut-off frequency, smaller and lighter the L-C filter size and weight. On the other hand, higher cut-off frequency will cause higher total harmonic distortion. 47 We need to find a trade-off point of these factors. According to KCL and KVL principles, from Fig.3.3 we can get:      Vc (s) = I1 (s) C∗S ⇒ I2 (s) =     Vo (s) = I2 (s) ∗ R I1 (s) C ∗R∗S Vin (s) = VRL (s) + VL (s) + Vo (s) = I(s) ∗ RL + L ∗ S ∗ I(s) + I2 (s) ∗ R = (I1 (s) + I2 (s))(RL + L ∗ S) + I2 (s) ∗ R 1 1 )(RL + L ∗ s) + ] C ∗R∗s C ∗s C ∗ R ∗ RL ∗ s + RL + C ∗ R ∗ L ∗ s2 + L ∗ S + R = I1 (s) C ∗R∗s Vo (s) R = Vin (s) C ∗ R ∗ L ∗ s2 + (C ∗ R ∗ RL + L) ∗ s + R + RL = I1 (s)[(1 + = = C∗R∗L∗s2 R+RL + R R+RL C∗R∗RL +L R+RL ∗s+1 R s2 ω2 + 2ξ s ω +1 where      R =      ω=          2ξ = ω R R+RL R+RL C∗R∗L C∗R∗RL +L R+RL ⇓ ξ= 2∗ √ C ∗ R ∗ RL + L √ R ∗ L ∗ C ∗ R + RL (3.1) 48 In order to get a desirable transient response for a second-order system, the damping ratio ξ may be chosen between 0.4 and 0.8. Small value of ξ(ξ < 0.4) yield excessive overshoot in the transient response, and system with a large value of ξ(ξ > 0.8) responds sluggishly. For this second order system, we will choose optimum damping coefficient ξ = 0.707. Substitute the following equation L= 4∗ π2 1 ∗ f2 ∗ C to Eq.3.1, we can get:      C =     L= √ R+R √ L − R−RL 2 2∗R∗π∗RL ∗f √ √ √ √RL ∗ R √ 2∗π∗f ∗( R+RL − R−RL ) From this equation, we can get the L and C value after deciding the cut-off frequency. In order to decide the trade-off cut-off frequency, we analyzed the relation of L-C filter cut-off frequency and output voltage THD value using simulink. In the simulink, we built the complete UPEC cell using power electronics models in power system blockset. We change the L and C value to achieve different cut-off frequencies. Thus iterating the cut-off frequencies for a given switching frequency, we can get the different output voltage THD value. The simulation result is shown as Fig.3.4. The X-axis is the L-C filter cut-off frequency and the Y-axis is the output voltage THD value. From this simulation we found that with the increase of the cut-off frequency, the output voltage THD value 49 Output Voltage THD (%) 30 27.79 25 20 18.56 15 11.01 10 5.64 5 1.156 1.768 250 500 2.65 0 1000 2000 3000 4000 5000 L-C Filter Cut-off Frequency (Hz) Figure 3.4: Cut-off Frequency Simulation of The Output Voltage Total THD Vs. Carrier Frequency For 10KHz also will increase. According to the specification, the THD value should be less than 5%, we will choose the low-pass filter cut-off frequency as 1kHz. Now we can get the theoretical values of the L-C filter:      L = 6.74mH     C = 3.76uF • Output inductor design 1. Assemble design inputs: – Inductance value L = 10mH (practical value) – Rated peak current Iˆ = 10A – Rated Rms current Irms = 7.07A – Operating frequency f = 10KHz 50 – Maximum surface temp: Ts = 100o C – Maximum ambient temp: Ta = 40o C ˆ rms : 2. Compute stored energy value LII ˆ rms = 10 ∗ 10−3 ∗ 10 ∗ 7.07 = 0.7H − A2 LII 3. Choose core material, shape and size: Core material: powder Core shape:EE cores Core part NO.:Mircometals E220 − 26 The parameters of the core E220 − 26 are as follows: Bac =1750gauss a=1.73cm Core area Acore = 1.5 ∗ a2 = 448.9mm2 Winding area Aw = 1.4 ∗ a2 = 419mm2 Area Product AP = 2.1a4 = 1881mm2 ˆ : 4. Calculation of the peak core flux density Bcore ˆ = Bac ∗ Bcore Iˆ ˆ dc I−I Because no DC current in the inductor, ˆ =Bac =1750gauss Bcore 5. Spec of winding parameters: L= ˆcore N ∗Acore B Iˆ N= L∗Iˆ ˆcore Acore ∗B = 10∗10−3 ∗10 448.9∗10−6 ∗1.75 ≈ 127(turns) 51 6. Air-gap Length: g = Acore ˆ core (a+d) Acore B − N g µ0 N Iˆ =0.957mm From the L-C filter design process we found that this system has a high requirement for the fundamental frequency variation. Hence, we need to choose the right control scheme to meet this standard. Since we have chosen a VSI type of cell, there are two types of control schemes which can be used to control the VSI in DC/AC mode. One is the hysteresis control scheme, the other is the sine triangle PWM scheme. The hysteresis control is used to impose a dead band or hysteresis around the reference current. This control scheme provides excellent dynamic performance because it acts quickly and it is relatively simple with respect to the PWM based ones which require a complete knowledge of the converter mathematical model. However, this only provides the current control and hence an outer voltage loop is also mandatory. The hysteresis control has two main disadvantages compared to the PWM scheme: • The switching frequency is very high and varies with fundamental frequency. • The method is essentially for a continuous time analogue implementation. When implemented digitally, it requires a high sampling rate in order to maintain the current error within the hysteresis limit. Hence at a given sampling rate, the PWM control technique offers better performances than the hysteresis PWM especially in the line current ripple and switching 52 frequency aspects. The harmonic content of the PWM control is also lower than the one corresponding to the hysteresis control [56], [57]. Moreover, the switching frequency in PWM scheme is constant and hence the design of output filter becomes simple. Based on these characteristics, we will use sine triangle PWM method. 3.1.3 Sine Triangle PWM Scheme We would like the DC/AC UPEC output to be sinusoidal with its magnitude and frequency controllable. In order to produce a sinusoidal output voltage waveform at a design frequency, a sinusoidal control signal at the desired frequency is compared with a triangular waveform as shown in Fig.3.5. The triangular waveform Vtri is at a switching frequency fs (carrier frequency) and the control signal Vcontrol is used to modulate the switch duty ratio and has a frequency f1 (modulating frequency). The amplitude modulation ratio ma is defined as ma = Vˆcontrol Vˆtri where Vˆcontrol is the peak amplitude of the control signal. The amplitude Vtri of the triangular signal is generally kept constant. The frequency modulation ratio mf is defined as mf = fs f1 In the inverter of Fig.3.6, the switches TA+ and TA− are controlled based on the comparison of Vcontrol and Vtri , and the following output voltage results, independent 53 vcontrol vtri t 0 1/fs (a) vAo vAo , fundamental = (v Ao)1 Vd/2 0 t -Vd/2 {vcontrol < vtri (VAo)h Vd/2 {vcontrol > vtri TA-: on, T A+: off} TA+: on, T A-: off } (b) 1.2 1.0 ma=0.8, m f=15 0.8 0.6 0.4 0.2 0.0 mf 1 2mf (mf+2) 3mf (2mf+1) (3mf+2) Harmonics h of f 1 (c) Figure 3.5: Pulse-Width Modulation of the direction of io : Vcontrol > Vtri , TA+ is on, 1 vAo = Vd 2 or Vcontrol < Vtri , TA− is on, 1 vAo = − Vd 2 The harmonic spectrum of VAo under the conditions indicated in Fig.3.5a and Fig.3.5b 54 + Vd + Vd/2 - A o + i0 + TA- Vd/2 - DA+ TA+ - DA- vAN - Figure 3.6: One-leg switch-mode inverter is shown in Fig.3.5c. This plot (for ma ≤ 1.0) shows three items of importance: • The fundamental-frequency component (vAo )1 varies sinusoidally and in phase with vcontrol as a function of time: Vˆcontrol Vd sin ω1 t 2 Vˆtri Vd = ma sin ω1 t for ma ≤ 1.0 2 (vAo )1 = Therefore, (VˆAo )1 = ma Vd 2 ma ≤ 1.0 the range of ma from 0 to 1 is referred to as the linear range. • The harmonics in the inverter output voltage waveform appear as sidebands, centered around the switching frequency and its multiples, that is, around harmonics mf , 2mf , 3mf , and so on. The analysis above is only true for synchronous PWM. That means mf value should be an integer. In section 3.1.2, we designed the L-C filter in a fixed carrier frequency. 55 If we let the system work in synchronous PWM mode, we have to change the carrier frequency according to the change of the fundamental frequency. That means we have to re-design the L-C filter. The system is also required to work in asynchronous PWM mode. According to the paper [58], in the regularly sampled asymmetrical sine triangle PWM technique, the lowest harmonics are almost around the switching frequency. We can use L-C filter to filter it out. Among the conventional switch-mode DC/AC inverters, the single-phase half bridge inverter operating in continuous conduction mode is by far the simplest choice for low to medium power (400W to a few kilowatts) applications. In this chapter, a half bridge DC/AC topology operating as a DC/AC inverter as a basic UPEC cell is studied in detail. The research focuses on the use of the half-bridge topology for basic UPEC cell because it is the simplest topology which can implement the DC/AC function. More simple the basic cell, more flexible and controllable of the combination functions of the UPEC cells. 3.2 Control Analysis and Design for The Single UPEC Cell In the past, sine wave inverters relied on open loop feed-forward control to produce the shape of the waveform, while a relatively slow output voltage rms feedback loop regulated the magnitude. While these types of controllers could maintain a desired 56 steady-state rms output voltage, their response to step changes in load were noticeably slow (several cycles of the output waveform), and nonlinear loads could greatly distort their output voltage waveform. Today, various modern feedback control techniques are available to control the output voltage waveform continuously, rather than on an rms basis. There so-called “instantaneous” controllers offer many performance advantages including faster transient response, better THD, and improved disturbance rejection via lower output impedance. Our control scheme is based on voltage feedback loop control. In order to get the fast response, high accuracy and high-level performance from the system, a current loop can be implemented inside the voltage loop. As a result, for the single UPEC, the overall control loop incorporates an inner current loop, an outer output voltage loop, a fixed switching frequency, and variable duty cycle approach to produce sinusoidal output voltage with minimum harmonic distortion. The fixed switching frequency approach produces a defined frequency spectrum at the inverter output, which makes it easier to design an electromagnetic interference filter to prevent interference with communication circuits. There are many control methods we can use to realize the close loop control. In our project, we will limit ourselves to the framework of the PI controller. This control method has the advantage in its simplicity since it is the most common industrial controller. It is satisfactory for a large number of applications, particularly for drives of low and medium performance. It is simple, robust and its performance improves as the switching frequency increases. By the fast PI 57 compensation for the load disturbance, we can also solve the problems such as: 1. variation in controller performance due to change in load 2. and parallel operation of converters. The transfer function of the ideal PI controller is T (s) = kp (1 + 1 ) Ti s (3.2) where kp is the proportional gain and Ti is the integral gain. 3.3 Close Loop Control Design Fig.3.7 shows the equivalent circuit diagram of the basic UPEC cell. Now we will + S1 io RL L Vd + + - RC iL vi + - ic C + vc - Z vo - Vd S'1 - Figure 3.7: Equivalent Circuit of The Basic UPEC analyze the inner current control loop and outer voltage control loop separately. 58 3.3.1 Inner Current Control Loop In the inner current control loop, according to the KCL and KVL principles, we can get the relationship as follows: L diL + RL iL = Vi − Vo dt We will express it in discrete time system as: iL [(k + 1)Ts ] − iL (kTs ) RL iL (kTs ) Vi (kTs ) − Vo (kTs ) + = Ts L L Ts RL iL (kTs ) Ts [Vi (kTs ) − Vo (kTs )] = iL [(k + 1)Ts ] − iL (kTs ) + L L Then we can convert it to z domain as: Ts RL iL (z) Ts = [Vi (z) − Vo (z)] L L L ∗ (z − 1) + Ts RL Ts iL (z) = [Vi (z) − Vo (z)] L L ziL (z) − iL (z) + So we can get: iL (z) = Ts [Vi (z) − Vo (z)] L ∗ (z − 1) + Ts RL Ts = 100µs is the sampling period. Then we can get the inner loop close PI control system block diagram as Fig.3.8 From this diagram we can see that Vo appears as a disturbance in the current loop. We can not express this disturbance with inductor current because of the unknown load. In our system, the output voltage is measurable. As a result, we can use decoupling to eliminate this disturbance as shown in the dashed block in Fig.3.8. After elimination of the disturbance, we can get the inner current 59 measured v o iL* PI + vi iL TS/[L(z-1)+R LTS] vo iL Figure 3.8: Current Controller Block Diagram close loop transfer function as follows: Ts s kI (kp + Tz−1 ) × L∗(z−1)+R iL L Ts = Ts kI ∗ Ts iL 1 + (kp + z−1 ) × L∗(z−1)+RL Ts = (kp + Ts kI )Ts z−1 Ts kI )Ts z−1 + kI Ts2 L ∗ (z − 1) + RL Ts + (kp + kp Ts (z − 1) L ∗ (z − 1)2 + RL Ts (z − 1) + kp Ts (z − 1) + kI T 2 kp Ts z − kp Ts + kI Ts2 = Lz 2 + (kp Ts + RL Ts − 2L)z + L − RL Ts − kp Ts + kI Ts2 = After applying the parameter values into this close loop transfer function, we can get the equation expressed with PI controller parameters kp and kI as: iL 10−4 kp z − 10−4 kp + 10−8 ki = i∗L 6.74 × 10−3 z 2 + (10−4 kp − 13.18 × 10−3 )z + 6.44 × 10−3 − 10−4 kp + 10−8 kI According to this equation, we can get the unit step response applying different kp and kI value as Fig.3.9 using matlab tool. The different PI gains and their performance is shown in Fig.3.10. The simulated sampling frequency is the same as the one we used in the actual circuit. Considering the overall requirements of settling time and overshoot magnitude for the unit step response curve P I1 gives the best performance. 60 Figure 3.9: Unit Step Response of The Close-loop Current Control PI 1 PI 2 PI 3 PI 4 kp 50 55 45 45 ki 100 100 100 80 f(s) 10kHz 10kHz 10kHz 10kHz Figure 3.10: Different PI Gain Values Hence we can chose the PI controller parameter kp = 50 and kI = 100. 61 3.3.2 Outer Voltage Controller In the outer voltage control loop, we also can get the relationship according to the KCL and KVL principles:      Vo = Vc + VRC      c ic = C dV  dt         i c = iL − i o We analyze the equation in discrete time system:      Vo (kTs ) = Vc (kTs ) + ic (kTs )RC      ic (kTs ) = TCs [Vc (k + 1)Ts − Vc (kTs )]          ic (kTs ) = iL (kTs ) − io (kTs ) Ts is the same sampling time as the inner current control loop. Then we can convert it to z domain as:      Vo (z) = Vc (z) + ic (z)RC      Ts Vc (z) = C(z−1) ic (z)          ic (z) = iL (z) − io (z) As the result, we can get: Vo (z) = Ts + Rc C(z − 1) [iL (z) − io (z)] C(z − 1) After solving the inner current close control loop, we can look the inner loop as a Gain K which is the resultant gain of the close loop. In the inner current close loop design, when we apply a unit step signal at the input, the system response is also a unit 62 output. Based on this result, we can look the K value equal to be 1 when we design the outer voltage loop. It makes the outer voltage close loop design more easy. In order to reduce the steady-state error between the capacitor voltage and its reference waveform, a PI controller also be used in the outer capacitor voltage feedback loop. We can get the outer loop close PI control system block diagram as Fig.3.11. It shows that the output current io acts as a disturbance in the loop. We cannot express this measured io Vo * PI 1/Z iL* + K iL + io ic Vo [CRC(z-1)+Ts]/C(z-1) Vo Figure 3.11: Voltage Controller Block Diagram disturbance with output voltage because of the unknown load. In our system, the output current is also measurable. As a result, we can use decoupling to eliminate this disturbance as shown in the dashed block in Fig.3.11. After elimination of the disturbance, we can get the outer voltage close loop transfer function as follows: (z−1)+Ts s kI (kp + Tz−1 ) × CRCC(z−1) Vo = (z−1)+Ts s kI Vo∗ 1 + (kp + Tz−1 ) × CRCC(z−1) = (kp + Ts kI )[CRC (z − 1) + Ts ] z−1 s kI (kp + Tz−1 )[CRC (z − 1) C(z − 1) + + Ts ] [kp (z − 1) + Ts kI ][CRC (z − 1) + Ts ] = C(z − 1)2 + [kp (z − 1) + Ts kI ][CRC (z − 1) + Ts ] kp CRC (z − 1)2 + kp Ts (z − 1) + Ts kI CRC (z − 1) + Ts2 kI = C(z − 1)2 + kp CRC (z − 1)2 + kp Ts (z − 1) + Ts kI CRC (z − 1) + Ts2 kI 63 Because the parasitic resistor of the capacitor is very small (about 0.07Ω), we can omit this value. After applying the parameter values into this close loop transfer function, we can get the equation expressed with PI controller parameters kp and kI as: Vo 10−4 kp z − 10−4 kp + 10−8 ki ≈ Vo∗ 3.76 × 10−6 z 2 + (10−4 kp − 7.52 × 10−6 )z + 3.76 × 10−6 − 10−4 kp + 10−8 kI According to this equation, we can get the unit step response applying different kp and kI value as Fig.3.12 using matlab tool. The different PI gains is shown as Fig.3.13. Figure 3.12: Unit Step Response of The Close-loop Voltage Control The simulated sampling frequency is the same as the one we used in the actual circuit. Considering the overall weighting of setting time and overshoot magnitude, the unit step response curve P I2 performs the best weighting. Hence, we will chose the PI controller parameter kp = 0.045 and kI = 170. 64 kp 0.04 0.045 0.055 0.045 0.045 PI 1 PI 2 PI 3 PI 4 PI 5 ki 170 170 170 130 200 f(s) 10kHz 10kHz 10kHz 10kHz 10kHz Figure 3.13: Different PI Gain Values The overall proposed control system block diagram is shown as the Fig.3.14. The output capacitor voltage, the inductor current and the load current are measured. measured Vo 1/Z measured io vo* + PI vo iL * + iL PI vi + vo - 1/(Ls+RL) iL + io ic (1/Cs)+RC vo Figure 3.14: Proposed Control System Block Diagram 3.3.3 Controller Implementation We use Texas Instrument (TI) company’s TMS320F243 DSP (Digital Signal Processor) as the main controller. There are many functions and modules in the DSP. We will use Even Manager (EV2), ADC, SPI, Internal and External Interrupt Modules to realize the single UPEC feedback control and combination functions. Fig.3.15 shows the internal structure of the DSP. (General Purpose)GP 65 + Verr PI1 Vref PWM1 + PI2 GATE DRIVE PWM2 Iout Vout ADCIN1 TMS320F243 ADCIN2 Voltage and Current Sense Amplifier Figure 3.15: Current and Sensing Interface Block Diagram Timer1 provides the time base for PWM generation, ADC sampling, current and voltage control loops. The timer operates in continuous up/down counting mode. For this design, the sampling frequency is 10kHz. The sampling time is 100µs. Interrupt mask registers IMR, EVIMRA are configured to allow Timer1 to generate an interrupt on period match. Once the DSP core receives the INT2 Timer1 interrupt, it takes a finite amount of time for interrupt source identification and context saving. Following that, in the T1 timer match interrupt service routine (ISR), ADC conversion starts and the results are saved. Then the voltage and current control loop are calculated. The sensed voltage and current signals are then fed back to the DSP core by the two ADC channels ADCIN1 and ADCIN2, respectively. Once this is done, the digitized feedback output voltage, Vout , is compared to an internally generated sine wave reference Vref . The difference between these two voltages, Verr , is fed into the PI 66 regulator, PI1. The output of this compensator is the reference current command for the inner current loop. This reference is compared with the digitized inductor current feedback Iout and then the difference is passed to the second PI regulator, PI2. The output of this current regulator is the command voltage, which is used to determine the duty cycle of the PWM gating signals. This current regulator output is passed onto the PWM module through the full compare register CMPR1. The PWM module compares this value with a 10kHz triangle waveform generated internally by Timer1. The results of the comparison are the required PWM signals PWM1 and PWM2, which control the IGBT switches. Programmable precise dead times are provided between this pair of complementary PWM signals. This dead time is defined by the dead-time control register DBTCON. The main programming flow chart is shown in Fig.3.30. The interrupt program flow chat is shown in Fig.3.31 (please refer to the rear part of this chapter). 3.4 Circuit Implementation The whole UPEC hardware circuit schematics please see Appendix.B. The datasheet of the components please refer to Appendix.A. 67 3.4.1 Power Circuit Components An Insulated Gate Bipolar Transistor (IGBT) has a fast recovery diode externally paralleled across it. Also, the IGBT on-voltage drop is low. Hence we will use SEMIKRON N channel IGBT-SK20GB123. It is a compact design and it integrates a half bridge switches into a small module. The maximum ratings of the IGBT is:Vces = 1200 ± 20V , Ic = 23/15A. Rubycon Aluminium Electrolytic Capacitors MX Series-105o C(PCB Mounting-Snap-In– 330uF/400V d.c. were used for the two input capacitors. Revox Rifa Class X2 Metallised Polyester Capacitors PHE830– 2.2uF/275V a.c was used for the output capacitor. The serial resistor is 0.07ohm 3.4.2 Driver Auxiliary Circuit Driver Circuit The driver auxiliary circuit is shown as Fig.3.16. SEMIKRON SKHI22 Hybrid Dual IGBT Driver SKHI22 fed by an isolated +15V supply was used for the gate drive. This driver module has many advantages including short circuit protection, driver interlock top/bottom and isolation by transformer. The interlock circuit prevents the IGBT to turn on before the gate change of the other IGBT is completely discharged. The locking time is typically 2.7µs. It may be prolonged by external resistors. Fig.3.17 shows the driver’s output signals to the top and bottom IGBTs. The IGBTs are turned on by applying a positive gate-emitter voltage of 15V , and turned off by 68 +5V +15V NDY0515 +5V +15V DSP +15V +15V CMP1 IGBT Driver SKHI22 CMP2 SFH6325 To IGBT CD4049 Figure 3.16: Driver Auxiliary Circuit connecting the gate with the emitter with −15V against the emitter to assure the complete turn on and turn off. The dead time between two IGBTs is 4µs. Isolated DC/DC converter NDY0515 was used to isolate the digital ground and analogue ground. The high-speed dual optocoupler SFH6325 from Infineon Technologies and a inverter CD4049 from FAIRCHILD Semiconductor were used to match the electrical level between the DSP and IGBT driver and isolate the ground. Sensing and Scaling Circuit The output voltage and capacitor current feedback signals are obtained through current and voltage transducer LA 25-NP and LV 25-P. The current and voltage sensor outputs need to be rearranged and scaled. The complete process of acquiring the current and voltage is depicted in the Fig.3.18 The LEM output signal can be 69 Figure 3.17: Driver Output Signals(experimental). nal(20V/Div), (3)The bottom driver signal(20V/Div) (1)The top driver sig- either positive or negative. This signal must therefore be translated by the analogue interface into a range of 0V-5V in order to allow the single voltage ADC module to read both positive and negative values. The Fig.3.19 below shows the different steps of the implemented current and voltage sensing: Note that Imax represents the maximum measurable current, which is not necessarily equal to the maximum phase current. This information is useful at the point where current scaling becomes necessary. The ADC input voltage is now converted into a ten bits digital value. The 2.5V analogue offset is digitally subtracted from the conversion result, thereby giving a signed integer value of the sensed current. 70 I 511 : -512 ix Kcurrent 1023 : 0 range adjustement 10-bit A/D interface LEM x=a,b TMS320F243 Figure 3.18: Current and Voltage Sensing and Scaling Block Diagram 3.4.3 Layout Consideration The layout design for high speed and high power switching circuit is very important. The bad layout design will cause EMI problem which even can damage the whole hardware circuit. Normally, the design rules used for the switching power inverter layout are summarized: • Use of double layer PCB where each high current path is immediately above its returns path on the other side of the board. • The current density has been reduced by enlarging the copper tracks in order to decrease the local dl /dt and consequently the resulting induced voltage. • Use of several links instead of one, between two large copper tracks, avoids high current concentrations and reduces the inductance (Fig.3.20). • Decoupling capacitors have been configured in the same direction as the direction of current flow. This prevents the formation of an inductive loop (Fig.3.21). 71 2.5V analog offset LEM ADC Input Volts OA Output Voltage Imax 5.0 2.5 LEM Output Voltage Volts Volts Imax 2.5 0 0 -2.5 -Imax Figure 3.19: Current and Sensing Interface Block Diagram I, dI/dt L I, dI/dt e e' e=L x dI/dt e'=1/3e Figure 3.20: Junction Between Two Wide Copper Tracks Is Less Inductive When Several Spaced Links Are Used Rather Than A Single Link • The use of several smaller capacitors in parallel permits reduction of the equivalent internal parasitic inductance (Fig.3.21). • Choose components specified with a low internal inductance. Prefer the capacitor packages which minimize the inductive connection length. • In general, the power, drive, and logic physical layout should resemble a neat schematic. See Fig.3.22. 72 Input filter Aux Switching & rectification Output filter Driver Sensing Control Iso. Output Input Figure 3.21: Configuration of Decoupling Capacitors Aux Figure 3.22: Linear Power Path-Minimize Noise Coupling From Switching Circuits Into Input And Outputs • Keep isolated circuits physical separated • Keep noisy power circuits away from logic and low-voltage control circuity • Keep power switching circuits away from filtered inputs and outputs • Place drivers close to switches and away from logic • Keep snubber and clamp loops as small as close to snubbed devices as possible Please refer to the layout diagram at Appendix.B. 73 3.5 Discussion of Simulation and Experimental Results Before building the experimental prototype, the operation of the circuit and results of the analysis were verified using SIMULINK simulation software. The simulation was done using switched models. The IGBT switch output voltage waveform is shown as Fig.3.23. The waveform is Figure 3.23: IGBT switches output waveform (experimental).(2)IGBT switches output voltage waveform (500V/Div), (M)the spectrum analysis the voltage waveform before L-C low-pass filter. According to the spectrum analysis, the harmonics are the switching frequency 10kHz and its multiples. Fig.3.24 shows the detail of the bottom IGBT switch output voltage. From this figure we can see that the maxim over-voltage is about 40V. It is about 6.6% of the output voltage. This value is measured at 10kHz switching frequency. The over-voltage is acceptable. 74 Figure 3.24: IGBT switch over shot voltage when turn off (experimental). (4)the bottom IGBT (500V/Div) Fig.3.25 and Fig.3.26 shows the simulation and experimental results of the basic UPEC close-loop output current and voltage waveforms at the steady state. Fig.3.27, Fig.3.28 and Fig.3.29 show the dynamic response when the load changes. Comparing these waveforms between simulated and experimental, it is seen that the waveforms shape and nature agree quite well. From these figures we can see that the system’s response for the disturbance caused by load changing is quick. 3.6 Summary In this chapter the design of basic UPEC cell is presented. The components of the cell are designed to meet the performance requirements of THD. A closed loop control method is proposed that uses both internal current and outer voltage loop. 75 Figure 3.25: The basic UPEC output current and voltage waveforms (simulated).(i)output current(5A/Div), (ii)output voltage(200V/Div) An output current feedback is added in order to facilitate current sharing as well as robustness to the load change. Experimental results of the cell using a DSP controller implementation is demonstrated. 76 Figure 3.26: The basic UPEC output current and voltage waveforms (experimental).(3)output current(10A/Div), (4)output voltage(200V/Div) Figure 3.27: The dynamic response when load changes(simulated).(i)output current(5A/Div), (ii)output voltage(200V/Div) 77 Figure 3.28: The dynamic response when load changes(experimental).(3)output current(5A/Div), (4)output voltage(200V/Div) Figure 3.29: The detail of the dynamic response when load changes(experimental).(3)output current(5A/Div), (4)output voltage(200V/Div) 78 start initialize _stop variable disable timer 1 feature to automatically start ADC conversion (in GPTCON) set GPIO output PWM pin function (in OCRA) load and initialize timer1 registers: - load _timer_period variable and store it to T1PER register - reset timer counter register (T1CNT) - set timer cofiguration register (T1CON) - configure timer 1 in continuous-up-down mode, DSP internal clock, prescaler X1 program ADC module: - set ADC configuration register (ADCCRTL2) - load _adcctrl_value variable to the ADC control & status register (ADCCTRL1) - clear ADC stacks (ADCFIFO1 and ADCFIFO2) program PWM module: - set PWM deadbeat parameters (DBTCON) - define active state of the 6 PWM outputs (ACTR) - load initial varaible and store it to CMPR1 register - set Compare Units control register (COMCON) load the address of timer 1 interrupt service routine into the corresponding interrupt vector: - load _t1per_ISR value and store it to tpint1vec vector initilize the variables Kp and Ki for current and voltage PI regulator calculation umask INT2 and T1PINT to enable timer 1 period interrupts generation (IMR, IMRA and IFRA) start PWM generation: - enable compare operation in Compare Units (in COMCON register) - enable output pins of Comapre Units (in COMCON register) - start timer 1 (in T1CON register) loop: call monitor NO stop ? YES end Figure 3.30: Main Program Flow Chart 79 _t1per_ISR: Timer 1 Interrupt Serivce sampling feedback current and voltage : - start ADC conversion immediately (ADCTRL1 register) - keep checking ADCEOC bit to wait for the end of conversion (ADCTRL1 register ) - save ADC result execute the sine wave generation program to generate the reference sine wave for the voltage control loop execute the voltage control algorithms to generate the current commands for the current control loop - execute the current control algorithms - calculate the PWM duty cycles and save the values in the specified full compare shadow registers (CMPR1) - the compare registers are updated after the next period match return from ISR Figure 3.31: ISR Flow Chart 80 Chapter 4 Distribution Power Systems Parallel-Parallel Operation Using UPEC Cells 4.1 Introduction In this chapter, the parallel-parallel configuration of the UPEC cells is analyzed. In high power applications, the stress on power switches increases, this requires a redesign of converters increasing the engineering cost. On the other hand, parallel redundant operation of power modules is believed to be an appropriate solution to supply more reliable and flexible power. It allows high current to be delivered to loads without the need to employ devices of high power rating and has advantages in 81 the cost and maintenance as compared with the single unit operation of a high power inverter [59]. Even though it has so many advantages, it also has some disadvantages such as: • Non-synchronization will cause the collapse of whole system. • Imbalance in power distribution among non identical modules leads to an unequal distribution of output current. • The circulation current excursing in the parallel inverter modules results in damage of power semiconductor in the parallel inverter [60], [61]. One of the aims of using cell based systems is to achieve a simple way of combining cells to form parallel redundant distributed power systems. In order to achieve a equal current distribution among all the parallel modules, it is necessary to use some kinds of feedback control scheme. The synchronization and load current sharing problems will be analyzed in the following sections. 4.2 Circuit Implementation First of all, we will analyze the parallel parallel configuration using the basic UPEC cells. We can obtain a higher kVA rating converter by connecting two cells in parallel. All P, N, U and W will be connected together, while V and M are shorted. The connections are shown in Fig.4.1. Now let us derive a system equation under 82 P + M N Cell 1 H U W V + Cbus Vin Vout P M - Cell 2 N H U W V - Cbus Communication Bus Figure 4.1: Parallel Parallel Configuration Using Two UPEC Cells ideal situation. We can model the parallel parallel connection as an AC circuit of first order approximation, which is shown as Fig.4.2. In the ideal situation, the inductor and capacitor are all ideal components and their values are the same. The two control waveform are sinusoidal: I1 A I2 + L1 V1 C B L2 Vo V2 O Figure 4.2: Two Parallel Connected UPEC Cells V1 = Vˆ1 sin(ωt + θ1 ) 83 V2 = Vˆ2 sin(ωt + θ2 ) According to the analysis of the basic module, we can get two waveforms at point A and B. The fundamental waveforms of the A, B output waveforms are as following: V1 = A1 sin(ωt + θ1 ), A1 = ma1 Vd , 2 ma1 = Vˆcontrol1 Vˆtri V2 = A2 sin(ωt + θ2 ), A2 = ma2 Vd , 2 ma2 = Vˆcontrol2 Vˆtri and In order to get the Vo : 1. according to the KVL, we get the equations:      V1 − Vo = L1 didt1         2   V2 − Vo = L2 di d (1) (2) t    o  C dV = i1 + i2   dt         L1 = L2 = L (3) 2. differential equation (3) and (1)+(2), we can get:   2    C ddtV2o =     C CL V1 +V2 −2Vo L d(i1 +i2 ) dt = d(i1 +i2 ) dt d2 Vo V1 + V2 − 2Vo = 2 dt L d2 Vo + 2Vo = V1 + V2 dt2 (4) 84 3. substitute the following equation Vo = A sin(ωt + Φ) to equation (4), we have: A(2 − CLω 2 ) sin(ωt + Φ) = A1 sin(ωt + θ1 ) + A2 sin(ωt + θ2 ) To solve the right side of the equation, we have: A1 sin(ωt + θ1 ) + A2 sin(ωt + θ2 ) = A1 sin(ωt + θ1 ) + A2 sin[(ωt + θ1 ) + (θ2 − θ1 )] = A1 sin(ωt + θ1 ) + A2 sin(ωt + θ1 ) cos(θ2 − θ1 ) + + A2 cos(ωt + θ1 ) sin(θ2 − θ1 ) = [A1 + A2 cos(θ2 − θ1 )] sin(ωt + θ1 ) + A2 sin(θ2 − θ1 ) cos(ωt + θ1 ) = [A1 + A2 cos(θ2 − θ1 )]2 + [A2 sin(θ2 − θ1 )]2 × × [cos Ψ sin(ωt + θ1 ) + sin Ψ cos(ωt + θ1 )] = [A1 + A2 cos(θ2 − θ1 )]2 + [A2 sin(θ2 − θ1 )]2 × × sin(ωt + θ1 + Ψ) cos Ψ = sin Ψ = A1 + A2 cos(θ2 − θ1 ) [A1 + A2 cos(θ2 − θ1 )]2 + [A2 sin(θ2 − θ1 )]2 A2 sin(θ2 − θ1 ) [A1 + A2 cos(θ2 − θ1 )]2 + [A2 sin(θ2 − θ1 )]2 Ψ = arctan A2 sin(θ2 − θ1 ) A1 + A2 cos(θ2 − θ1) 85 After solving the right side of the equation, we have: A(2 − CLω 2 ) sin(ωt + Φ) = [A1 + A2 cos(θ2 − θ1 )]2 + [A2 sin(θ2 − θ1 )]2 × × sin(ωt + θ1 + Ψ) Ψ = arctan A2 sin(θ2 − θ1 ) A1 + A2 cos(θ2 − θ1) and A sin(ωt + Φ) = [A1 + A2 cos(θ2 − θ1 )]2 + [A2 sin(θ2 − θ1 )]2 2 − CLω 2 × × sin(ωt + θ1 + Ψ) Then, we can get the result of parallel-parallel output voltage equation as follows: V0 = A sin(ωt + Φ) (4.1)  √  [A1 +A2 cos(θ2 −θ1 )]2 +[A2 sin(θ2 −θ1 )]2    A=  2−CLω 2     Φ = θ1 + Ψ          Ψ = arctan A2 sin(θ2 −θ1 ) A +A cos(θ −θ 1 2 2 1) Now we got the ideal general output voltage equation for UPEC cells when connected in parallel input and parallel output format. Using this equation, we can analyze the output voltage even when the two inputs are different in amplitude and phase. For example, the output voltage of cell 1 and cell 2 is given as      V1 = 240 sin(314t + 180o )     V2 = 210 sin(314t − 30o ) 86 When they are connected in parallel input parallel output mode, the output voltage can be obtained using Eq.5.2: V0 = A sin(ωt + Φ) ≈ 60 sin(314t + 240.95o ) Under ideal conditions, the two parallel cells will be operating at the same amplitude and the same phase shift. We will simply let the A1 = A2 = A and θ1 = θ2 = 0o :      V1 = A sin 314t     V2 = A sin 314t The output voltage under ideal situation should be: Vo ≈ A sin 314t 4.3 Synchronization Scheme For Parallel Parallel Configuration of UPEC Cells Two or more inverters operating in parallel must satisfy the following conditions: • frequency and phase synchronism between the output voltages of the various inverters • output voltage should be equal and current balance The output voltage and phase angle of the respective inverters must have the same value for the parallel operation at every instant, otherwise, the circulating current 87 will occur between the UPEC Cells. So, the precise control for the phase angle and output voltage is necessary. 4.3.1 Phase-Lock-Loop In general synchronization scheme, the function of synchronization is performed by a PLL circuit [1]. A PLL is a device which causes one signal to track another. It keeps the output signal synchronized with a reference input signal in frequency as well as in phase. More precisely, the PLL is simply a servo system, which controls the phase of its output signal in such a way that the phase error between output phase and reference phase reduces to a minimum [62]. So, the PLL circuit is adopted to control the phase angle among the inverters and AC power source. But this technique also has many disadvantages. It is difficult to obtain a fast response of control because of the inherently slow response of the PLL circuit. Also, during transients the parallel units have a difference in output voltage causing circulating current. This is especially so if the load is light [63]. Thus, the above scheme of parallel operation is difficult to implement and to provide for expansion of system [12]. 4.3.2 Internal Generated Sine Reference In some circumstances, it is possible and advantageous to simplify the synchronization scheme. According to the characteristics of the basic UPEC cell and the concrete circumstances, we will introduce a more simple but effective method to realize the 88 synchronization between the parallel parallel configuration UPEC cells. Before introducing this scheme, we will briefly explain the generation of the sine reference wave. In Section 3.3.3, we have mentioned that the reference sine wave Vref is internally generated in the controller DSP TMS320F243. It is obtained using a look up table which includes 256 values. To be able to control the frequency of the modulation with some accuracy, a method based on the modulo mathematical operation is used (i.e. any overflow is disregarded and only the remainder is kept) [64]. A 16-bit “counter” is used to determine the location of the next value and only the upper byte of the counter determines the location of the next sine value. A step value is added to the counter every time a new value from the sine table is to be loaded. By changing the value of the step, one can accurately control the frequency of the sine wave. The frequency of the step value can be calculated from the following formula: f (step) = step Ts × 2n (4.2) where: f (step)=desired frequency Ts =the PWM time period n=the number of bits in the counter register step=the step size used The frequency that the PWM signal will be modulated is proportional to the step size 89 and inversely proportional to the size of the counter register and the period. Since the upper byte is used as the pointer, the look up table has 256 values, which is equivalent to the number of possibilities for an 8-bit number: 0 to 255. Additionally, since the upper word of the accumulator is disregarded, the pointer for the sine look up table does not need to be reset. The principle is shown as Fig.4.3. In our system, Counter (Step Value=147h) 0000h 0147h 028Eh 03D5h 051Ch …. …. …. FF78h 0000h 0147h Pointer 00h 01h 02h 03h 05h …. …. …. FFh 00h 01h Sine Reference Value 1st value of sine table 2nd value of sine table 3rd value of sine table 4th value of sine table 5th value of sine table …. …. …. 256th value of sine table 1st value of sine table 2nd value of sine table Figure 4.3: The Demonstration of Counter the desired frequency f (step) is 50Hz, the PWM time period is 100µs and the number of bits for the counter is 16. Then we can get the step according to the equation 4.2: step = f (step) ∗ 0.0001 ∗ 65536 = 327(Dec) = 0147h(Hex) 90 4.3.3 A New Synchronization Scheme General Purpose Input Output (GPIO) Functions In Chapter 3, we have mentioned that every basic UPEC cell has its own feedback close loop current and voltage control system and a internal sine wave reference look up table. Our goal is to configure the distributed power system without changing the basic UPEC cell internal structure and control loop and simply connect the cell input and output ports together. In order to get the results, the first problem we need to solve is: how can we synchronize the PWM clocks of the two independent UPEC cells? From the close loop control program flow chart of the basic UPEC cell (Fig.3.30), we can find that GP Timer 1 provides the time base for PWM generation, ADC sampling and the whole close loop control programs. We can let the two GP timers of the two UPEC cells start to count at the same time, in other words, the PWM clocks are synchronized. How to let the two timers start at almost the same time in a simple way? We can use the GPIO pins to realize the function. In the DSP controller, there are some digital input/output (GPIO) pins. The GPIO pins are controlled through datamemory mapped registers. The pin status can be monitored by reading the I/O data register. That means if the pins electrical level changes either from high to low or from low to high, there is a flag bit in the corresponding register which will be set. Fig.4.4 shows the flow chart of how to let the two UPEC cells start the timer at the same time. We can configure one of the I/O pins as input and use a simple circuit to 91 UPEC 2 UPEC 1 - enable compare operation - enable output pins of Comapre Unit - enable compare operation - enable output pins of Comapre Unit configure the corresponding GPIO pin as input configure the corresponding GPIO pin as input test the status of the pin test the status of the pin NO Does the pin is read as high ? NO YES start PWM generation: - start timer 1 (in T1CON register) Does the pin is read as high ? YES start PWM generation: - start timer 1 (in T1CON register) Figure 4.4: The Flow Chart of Using GPIO Pins connect two I/O pins of the two UPEC cells together as shown in Fig.4.5. Before we turn on the switch, the program will continue to check the pin status. When we turn on the switch, the state of the I/O pin will change from low to high. The two DSPs will detect it and run out of this loop and begin to run the main program “almost” at the same time. Drawback of Using The GPIO Functions In the former section, we used the word “almost” because if we use the GPIO method, there are some factors we have to consider. • First, we cannot ensure that the cables connected between the two GPIO pins 92 S I/O pin UPEC1 R1 +5V R2 I/O pin UPEC2 Figure 4.5: The Demonstration Using Switch and the switch have exactly the same length. • Second, we may not get the two GPIO pins detect the statue change at exactly the same time, • Third, even if we can let the two DSP detect the change at exactly the same time and start to run the main program at exactly the same time, we cannot make sure the timer of the two DSP are running at exactly the same speed (due to propagation delays). At this stage, we will leave the output ports of two cells unconnected before we can get a equal output voltage. Fig.4.6 shows the error between two parallel parallel configuration UPEC cell output voltages using the GPIO method. All of these factors that cause the phase shift of the two DSP’s PWM timer result in the phase shift of the two UPECs internal references. Fig.4.7 shows the simulation results of the percent 93 Figure 4.6: The error voltage between two parallel parallel configuration UPEC cells’ voltages(experimental). (1)UPEC cell1 output voltage(50V/Div), (4)UPEC cell2 output voltage(50V/Div), (3)Error (V1 − V4 ) voltage(100V/Div) of the output voltage distortion (= Vref −Vout ) V ref when there is a time delay between two carrier waveforms caused by the network communication. Fig.4.8 shows the simulation results of the percent of output voltage distortion (= Vref −Vout ) V ref when there is a time delay between two reference waveforms caused by the network communication. Fig.4.7 and Fig.4.8 show us that the phase shift of the PWM timer does not cause a major problem because of its high frequency. Phase shift between two internal reference sine wave will cause a large error that can damage when connected in parallel parallel configuration. Continuous Synchronization Using Serial Interface From Section 4.3.2, we can find that the variable “counter” can decide the next reference value in the inner look up table. If at every PWM period this variable is 94 1.3 1.2 delta V (%) 1.1 1 0.9 0.8 0.7 0.6 0.5 0.2 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 0.4 (ms) Figure 4.7: Parallel Parallel Voltage Error VS. Time Delay of Vcarrier the same, we can get the same amplitude and phase angle of the two UPEC cell sine reference value. We can assume that one of the UPEC cell is the master and the other one is the slave. To be sure the “counter” variables of two UPEC cells are the same at every PWM period, we only need the master cell “tell” the slave its own “counter” value periodically. The slave cell then will track the master’s changing automatically. The master and slave cells will use the SPI (serial peripheral interface) module to communicate as shown in Fig.4.9. The SPI is a high-speed synchronous serial input/output (I/O) port that allows a serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. If we use 5Mbps SPI baud rate, the slave just needs 3.2µs to finish receiving 16-bit information ideally. It is normally used for communication between the DSP controller and external peripherals or another controller. The SPI can operate in 95 7 6 deltaV (%) 5 4 3 2 1 1.95 1.75 1.55 1.35 1.15 0.95 0.75 0.55 0.35 0.15 0 0 (ms) Figure 4.8: Parallel Parallel Voltage Error VS. Time Delay of Vref master or slave mode. • In the master mode, the SPI provides the serial clock on the SPICLK pin for the entire serial communications network. The master will send out the next possible counter value to the slave periodically. • In the slave mode, it receives the information only when the master sends it. There is a flag bit which will be set each time after receiving the information from the master. The slave will check the flag bit every PWM period. Only when it detects the status change of the flag bit, that means the master has sent a data to the slave, it will read the received data and update its own counter value to the new value. Using the simple method, we can implement the synchronization between parallel UPEC cells. The “counter” points to the relative position to the start point of sine 96 Master slave _t1per_ISR: Timer 1 Interrupt Serivce _t1per_ISR: Timer 1 Interrupt Serivce fetching the sine reference value fetching the sine reference value time to synchronize? NO YES send the reference value to salve using SPI module return from ISR YES SPI flag bit set to 1? receive the reference value sending from master using SPI NO return from ISR Figure 4.9: The Flow Chart of Synchronization Using SPI Module reference look up table, not a concrete reference value, we also can use it in the other configurations such as full bridge single phase and three phase connection. Now the problem we need to solve is: how often the master needs to send a synchronized value? What is the optimal synchronization rate? The following figures show the different results of open-loop UPECs using different synchronization rate. Before we actually connect cells in parallel parallel configuration, we will measure the individual cells output voltages so as to measure the error voltage between the two cells. Only when the error voltage is zero two cells will be connected in parallel. Fig.4.10 is the result with synchronization every 5 fundamental cycles. Fig.4.11 is the result with synchronization every 1 fundamental cycles. Fig.4.12 is the result with every 1 4 fundamental cycle synchronization rate. From these figures, we find that the 97 Figure 4.10: The error voltage every 5 fundamental cycles’ synchronization rate(experimental). (1)UPEC cell1 output voltage(50V/Div), (4)UPEC cell2 output voltage(50V/Div), (3)Error (V1 − V4 ) voltage(20V/Div) error was reduced from 20% to 10% when synchronizing from every 5 cycles to 1 cycles. But any increase in rate beyond 1 cycle synchronization, the error is almost the same. We can not reduce it using just synchronization. We would have expected that the more synchronization frequency, the less the error. Then why does error still exist at high synchronization rate? Is it caused by the circuit parameter difference? We will investigate this further. 4.4 Imbalance Problem In Power Distribution System In order to analyze the problem, we simulated the output voltage error using the same L-C filter parameters including the inductor internal serial resistor and capacitor 98 Figure 4.11: The error voltage every 1 fundamental cycles’ synchronization rate(experimental). (1)UPEC cell1 output voltage(50V/Div), (4)UPEC cell2 output voltage(50V/Div), (3)Error (V1 − V4 ) voltage(10V/Div) internal parallel resistor. We also gave the two UPEC cells the same input before the output L-C filter. The simulated and experimental results are shown in Fig.4.13 and Fig.4.14. The two results match exactly. When different parameters were used for two different UPEC L-C filters, an error exists between the two UEPCs and it almost equals the error we get when we synchronized every 1 cycle. This shows that the error is not caused by non-synchronization, but caused by the L-C filter parameter. Because the inner serial resistor of the inductor and the parallel resistor of capacitor of the two UPEC L-C filter are not exactly the same, they cause the error between the two UPEC output voltage. The error voltage is shown in Fig.4.15. The derivation of the error voltage is shown as follows: Verror = ZC1 ZC2 V1 − V2 ZC1 + ZL1 ZC2 + ZL2 99 Figure 4.12: The error voltage every 14 fundamental cycles’ synchronization rate(experimental). (1)UPEC cell1 output voltage(50V/Div), (4)UPEC cell2 output voltage(50V/Div), (3)Error (V1 − V4 ) voltage(10V/Div) At this demonstration circuit, we have V1 = V2 = V sin ωt Synchronization makes this possible. Then we can get Verror = ( ZC1 ZC2 − )V sin ωt ZC1 + ZL1 ZC2 + ZL2 • In the ideal situation:     RL1 = RL2 = 0           RC1 = RC2 = 0  L1 = L 2 C1 = C2 ⇒ Verror = 0               • In the actually situation, the inductor and capacitor have a inner serial resistor. There is a little difference between the values for the resistor and even the 100 Figure 4.13: The error voltage after different L-C filter(experimental). (1)UPEC cell1 output voltage(50V/Div), (4)UPEC cell2 output voltage(50V/Div), (3)Error (V1 −V4 ) voltage(10V/Div) inductor and capacitor. All these factors will cause the error voltage. From Fig.4.15, we can get:      ZL = RL + jXL (XL = ωL)     ZC = RC − jXC (XC = 1 ) ωC ZC RC − jXC = ZC + ZL RC − jXC + RL + jXL RC − jXC = RC + RL + j(XL − XC ) The difference of parameters is derived as follows: ZC1 ZC2 RC1 − jXC1 RC2 − jXC2 − = − ZC1 + ZL1 ZC2 + ZL2 RC1 + RL1 + j(XL1 − XC1 ) RC2 + RL2 + j(XL2 − XC2 ) 2 2 C1 RC1 + XC1 arctan −X RC1 = L1 −XC1 (RC1 + RL1 )2 + (XL1 − XC1 )2 arctan X RC1 +RL1 − 2 2 C2 RC2 + XC2 arctan −X RC2 L2 −XC2 (RC2 + RL2 )2 + (XL2 − XC2 )2 arctan X RC2 +RL2 101 Figure 4.14: The error voltage after different L-C filter(simulated). (1)UPEC cell1 output voltage(50V/Div), (4)UPEC cell2 output voltage(50V/Div), (3)Error (V1 −V4 ) voltage(5V/Div) (4.3) For example, the actually inductors and capacitors and their inner serial resistors values can be measured from two different UPEC cells hardware circuits. These values is listed below:      RL1 = 4.05Ω           RL2 = 3.35Ω           L1 = 10.52mH     L2 = 10.26mH           C1 = C2 = 2.05uF           RC1 = RC2 = 0.07Ω After substituting these parameters into Eq.5.4, we can get: ZC1 ZC2 1553.5 − 89.99o 1553.5 − 89.99o − = − ZC1 + ZL1 ZC2 + ZL2 1550.2 − 89.85o 1550.28 − 89.87o 102 ZL1 ZL2 Verr L1 Rl1 V1 ZC1 Rl2 Rc1 Rc2 C1 C2 L2 V2 ZC2 O Figure 4.15: Error Voltage Between Two UPEC Cells o = ej(−0.14 ) − ej(−0.12) o = cos(−0.14)o + j sin(−0.14)o − cos(−0.12)o − j sin(−0.12)o = [cos(−0.14)o − cos(−0.12)o ] + j[sin(−0.14)o − sin(−0.12)o ] = −7.92 × 10−7 + j(−3.49 × 10−4 ) = 3.49 × 10−4 89.87o Verror = 3.49 × 10−4 (cos 89.87o + j sin 89.87o )V sin ωt ≈ 3.49 × 10−4 V j sin ωt From this equation, we found that the error voltage is about 90o out of phase with the fundamental signal and changing at the same frequency as the fundamental. The analysis diagram of the L-C filter parameter variation is shown in the Fig.4.16. The X-axis is a ratio of ZL1 /ZL2 , Y-axis is a ratio of ZC1 /ZC2 and Z-axis is ZC2 . ZC2 +ZL2 ZC1 ZC1 +ZL1 − From the 3 − D analysis we can see the trend in error when two L-C filter 103 parameters change. The change of the capacitor parameter would have a much more effect than the change of the inductor parameter. We can reduce the difference of Figure 4.16: The Analysis for The Variation of L-C Filter Parameters. X = ZL1 /ZL2 , C1 C2 − ZC2Z+Z Y = ZC1 /ZC2 , Z = ZC1Z+Z L1 L2 the two L-C filter parameters, but we still cannot make the parameters exactly the same. In practice, mandatory control is needed to reduce the error caused due to the components. 4.5 4.5.1 Load Current Sharing Problem The Analysis for Load Current Sharing To show the importance of current sharing, we will consider the conventional approach in which only the output voltage is fed back for output voltage regulation, with no control of the current distribution. The principle theory refers to [65]. The 104 overall control block diagram is shown in Fig.4.17. The transfer function indicated in cell1 Ve Vref + iL1 d G(s) H G1(s) - + Q(s) Vref + Ve cell2 G(s) H - d VO + G2(s) iL2 Figure 4.17: Block Diagram of Two UPEC cells Under Single-Loop Control the block diagram is defined as follows: H=PWM gain of the inverter Gi (s)=Transfer function of the duty ratio to inductor current G(s)=Transfer function of the compensation circuit Z(s)=Output impendence function Q(s)=Load impedance The equivalent circuit for this system is shown in Fig.4.18. Because of the small value of the ESR of the output capacitor (0.07Ω), we can neglect it. Also we will consider L1 = L2 = L, C1 = C2 = C because we need to analyze the effect of the inductor ESR. Vg is the DC link voltage and d is the duty ratio. We can only consider the duty ratio because we only need to find the current distribution error between 105 iL1 ZL1 L1 Vgd ZL2 iL2 + RL1 C1 Zc RL2 C2 vo - L2 Vgd RL O Figure 4.18: Equivalent Circuit of Two Parallel Connected UPEC Cells Under SingleLoop Control the two cells in a simple way. According to the KVL and KCL principles, the duty ratio-to-inductor current transfer functions are derived as follows:      iL1 ZL1 = iL2 ZL2     (iL1 + iL2 )Zc = (1) Zc V d Zc +ZL g (2) In this equation:      ZL1 = sL + RL1           ZL2 = sL + RL2   ZL2   ZL = ZZL1L1+Z   L2       1   Zc = 2sC+ 1 RL From (2), we can get iL2 = = Vg d ZL2 − iL1 Zc + ZZL1L1+Z L2 Vg d(ZL1 + ZL2 ) − iL1 Zc ZL1 + Zc ZL2 + ZL1 ZL2 106 substitute this equation to (1), we can get Vg d(ZL1 + ZL2 )ZL2 − iL1 ZL2 Zc ZL1 + Zc ZL2 + ZL1 ZL2 Vg d(ZL1 + ZL2 )ZL2 iL1 (ZL1 + ZL2 ) = Zc ZL1 + Zc ZL2 + ZL1 ZL2 Vg dZL2 iL1 = Zc ZL1 + Zc ZL2 + ZL1 ZL2 (sL + RL2 ) = Vg d 1 (sL + RL1 + sL + RL2 ) + (sL + RL1 )(sL + RL2 ) 2sC+ 1 iL1 ZL1 = RL = = (2sC + (2sC + 1 )(sL RL 1 )(sL RL + RL2 ) + RL1 )(sL + RL2 ) + (sL + RL1 ) + (sL + RL2 ) (2sC + (sL + RL1 )[(2sC + 1 )(sL RL 1 )(sL RL + RL2 ) + RL2 ) + 1] + sL + RL2 Vg d Vg d As a result, we can get the duty ratio-to-current transfer function G1 (s) = = G2 (s) = = iL1 (s) d(s) (2sC + (sL + RL1 )[(2sC + 1 )(sL RL 1 )(sL RL + RL2 ) + RL2 ) + 1] + sL + RL2 Vg iL2 (s) d(s) (2sC + (sL + RL2 )[(2sC + 1 )(sL RL 1 )(sL RL + RL1 ) + RL1 ) + 1] + sL + RL1 Vg and the load impedance is given by Q(s) = vo (s) RL = iL1 (s) + iL2 (s) 2sCRL + 1 Applying Mason’s gain formula [66] to the block diagram shown in Fig.4.18, we can obtain the current distribution error which is derived as follows: According to the 107 flowchart, we have      iL1 (s) = Ve G(s)H(s)G1 (s) (4.4)     iL2 (s) = Ve G(s)H(s)G2 (s) We also can get the relation      Ve = Vref − Vo     Vo = HQ(s)G(s)[G1 (s) + G2 (s)]Ve From this equation, we will have Ve = Vref − HG(s)Q(s)[G1 (s) + G2 (s)]Ve = Vref 1 + HG(s)Q(s)[G1 (s) + G2 (s)] Now we can substitute the value of Ve into Eq.4.4, we can get      iL1 (s) = G(s)H(s)G1 (s) V 1+HG(s)Q(s)[G1 (s)+G2 (s)] ref     iL2 (s) = G(s)H(s)G2 (s) V 1+HG(s)Q(s)[G1 (s)+G2 (s)] ref Now we can get the equation for the circulating current as iL1 (s) − iL2 (s) = Let Vref (s) be the step function HG(s)(G1 (s) − G2 (s)) Vref (s) 1 + HG(s)Q(s)(G1 (s) + G2 (s)) Vref . s By using the final value theorem as: IL1 (0) − IL2 (0) = lim s[iL1 (S) − iL2 (S)] s→0 where IL1 (0) and IL2 (0) are the steady state values of iL1 (s) and iL2 (s). The current distribution error is given by |iL1 (0) − iL2 (0)| = HG(0)[G1 (0) − G2 (0)] Vref (s) 1 + HG(0)Q(0)[G1 (0) + G2 (0)] 108 In this equation:      Q(0) = RL      G1 (0) =          G2 (0) = RL2 Vg RL1 RL2 +RL (RL1 +RL2 ) RL1 Vg RL1 RL2 +RL (RL1 +RL2 ) If both cells are identical, the current distribution error should be zero. However, this is not always the case. For example, if H = 70, G(0) = 0.04, Vref = 240V , Vg = 600V , RL1 = 4.05Ω, RL2 = 3.35Ω, and RL = 30Ω, we obtain: IL1 (0) − IL2 (0) = 759mA From this result we can clearly see that the load imbalance becomes worst at large load outputs. 4.5.2 Different Scheme For Load Sharing Distribution Before we discuss the load current sharing problem, we will briefly introduce the different methods used to achieve load sharing control [67]. The Droop Control Technique The simplest and oldest method to achieve current sharing is based on the voltage droop characteristics [68]. The voltage droop is produced by using the output current to adjust the reference voltages, which is used to program the output impedance of each power supply. This technique exhibits very poor load sharing capability at light load and when the parallel modules are of different power densities. 109 The Automatic Current Sharing Average Current Method The second method is the automatic current sharing average current method [69]. This method achieves load sharing by adjusting the reference voltages and does not use any external controller. A single shared bus interconnects all the supplies, then a single signal from the shared bus is feed back and adjusts the reference voltage until load sharing is achieved. This scheme performs good load sharing if used for paralleling similar modules, it performs poorly if the power density of the connected modules are different. Master-Slave Load Distribution Technique The master slave technique [65] uses a master converter to achieve the output voltage regulation through the voltage feedback loops to program the load sharing. This scheme can offer very good load sharing ability even if the modules paralleled are not identical. However, because the master controller has no current feedback loop on its own, there is high output current overshoot during startup transient. Central Limit Control Method This method [70] uses an extra controller to achieve the load distribution. All the modules are programmed to track a central limit reference, so the necessary for an extra controller. This scheme is the most accurate technique. However, we have to add an extra controller except for the main circuits. 110 4.5.3 The Load Current Sharing Scheme Analysis Using In Parallel Parallel Configuration The inverters connected to the same output bus is the most simple and versatile solution for the parallel operation [71],[72]. It does not require the use of common power elements such as the multi-primary transformer. In our project, the UPEC cell is a standard basic cell. We just need to connect the basic cells simply at the input and output ports to configure the parallel parallel functions. We can consider the paralleled cell modules with the same capacity and having similar dynamic characteristics. In this case, the instantaneous load to be shared in each half cycle is determined by the internal impedance of each inverter, which depends on the output filter and on the DC filter. Similarly, the sharing of the harmonic currents depends on the output filter. The parallel operation regulation is a function of the control circuit. Thus, the inverter with the smallest impedance and/or the fastest dynamic response tends to be overloaded. Nevertheless, for inverters of the same power and from the same manufacturer these differences are quite small reducing the mentioned problems [73]. Depending on these characteristics, we will use the automatic current sharing average current method as our basic principle. The approach we use is to employ an active current control scheme. It forces the current in each inverter to follow an average current which is obtained by taking the average value of all individual output currents. In essence, the controller needs to calculate the average current value continuously. Following which, each cell compares 111 its output current with the average current value and incorporates the error into the voltage feedback loop. An additional current loop is used in each cell to incorporate the error current, which is the difference between the output current and the average current. The error is fed to the voltage control loop and the current control loop to achieve active current sharing. Such a scheme is commonly known as the democratic current-sharing scheme [74], [75], [76], [77]. Suppose N modules in parallel, when the switches are all ‘on’, obtained (I1 − Iave )R + (I2 − Iave )R + ..... + (IN − Iave )R = 0 So Iave = 1 N N Ik k=1 If one or more switches are “off”, the Iave will be the average of the rest ones automatically. This makes redundant operation possible. Fig.4.19 shows the parallel IL1 output current of UPEC #1 + U1 - + IL2 + - output current of UPEC #2 Iave + U2 Figure 4.19: Current Sharing Block Diagram Of The Parallel Parallel UPEC Cells combination of cells with current sharing control method. Iave is an average current defined by Iave = µ1 I1 + µ2 I2 where µ1 and µ2 are constants equal to 1 (n=number n 112 of inverters). The overall control loops diagram is shown as Fig.4.20 After applying + P - measured V o master measured I o + vo* + PI iL* + vi + PI 1/(Ls+R L) iL vo vo 1/Z io - iL + u1 (1/Cs)+R C ic - + Iave + u2 + P measured V o - slave measured I o 1/Z + vo* + PI vo iL* + vi + PI iL 1/(Ls+R L) vo - io - iL + Vo (1/Cs)+R C ic Figure 4.20: Control Loop Diagram Using Average Current Sharing the average current control, we can analyze the current distribution error as shown in Fig.4.21. In this figure, P1 (s) and P2 (s) are the compensation amplifier gains for the current error signals. IL1 (s) + IL2 (s) − IL1 (s) 2 and IL1 (s) + IL2 (s) − IL2 (s) 2 And the other parameters have been defined at Section 4.5.1. We assume P1 = P2 = P . Now we will apply Mason’s gain formula the as the same as the analysis in Section 4.5.1, we can get the current distribution error function as follows according to the 113 + cell 1 P1(s) - Vref + Ve d + G(s) H iL1 G1(s) - + 1/2 Ve Vref + G(s) - H d + + G2(s) VO iL2 - cell 2 P2(s) Q(s) + Figure 4.21: Block Diagram of Two Parallel-Connected UPEC Cells Using Automatic Current Sharing Average Current Method result of [70]: iL1 (s) − iL1 (s) = G1 (s) − G2 (s) Vref ∆(s) where ∆(s) = 1 0.5P (s) +Q(s)[G1 (s)+G2 (s)+ ×(G1 (s)+G2 (s))+2HP (s)G1 (s)G2 (s)] G(s)H G(s)Q(s) then we can get the steady state current distribution error following the same procedures in Section 4.5.1 as follows: (RL2 − RL1 )Vref ∆(0) M 0.5P (0) ∆(0) = + Q(0)[RL2 + RL1 + (RL1 + RL2 + 2RL ) + G(0)H G(0)Q(0) 2HP (0)Vg + (RL1 + RL2 )RL ] M |iL1 (0) − iL2 (0)| = Where M = RL (RL1 + RL2 ) + RL1 RL2 . By choosing the same device values used in Section 4.5.1: Vg = 600, Vref = 240, RL1 = 4.05Ω, RL2 = 3.35Ω, and RL = 30Ω, 114 P = 1, Q(0) = 30, H = 70, G(0) = 0.04, the current distribution error can be: |iL1 (0) − iL2 (0)| = 1.16mA The result means that this method could be used to reduce the error caused by the components value variation. Fig.4.22 and Fig.4.23 show the simulated and experimental result using load current sharing control scheme. The mean error is decreased from 10% to 0.8% of the nominal voltage. Figure 4.22: The error voltage using load current sharing control(simulated). (i)UPEC cell1 output voltage(100V/Div), (ii)UPEC cell2 output voltage(100V/Div), (iii)Error (Vi − Vii ) voltage(10V/Div) Simulation and Experiment Results After getting these results, we connect two UPEC cells outputs together. Fig.4.24 and Fig.4.25 show the simulated and experimental results of the steady state output current and voltage waveforms. Fig.4.26 and Fig.4.27 shows the steady state of the parallel cells output currents. Fig.4.28 and Fig.4.29 show the simulation and 115 Figure 4.23: The error voltage using load current sharing control(experimental). (1)UPEC cell1 output voltage(200V/Div), (4)UPEC cell2 output voltage(200V/Div), (3)Error (V1 − V4 ) voltage(50V/Div) experiment results of dynamic response cells current waveforms when load changing from full to half. Fig.4.30 and Fig.4.31 show the simulated and experimental results of the output current and voltage dynamic response. 4.6 Summary Parallel parallel operation of basic UPEC cells is presented. The problem of synchronization is solved using the general purpose I/O of the DSP. The synchronization is maintained using a high speed serial interface that passes on the address pointer of the reference sine wave in a master slave mode. However, this is not sufficient to reduce the error between two cells. Hence, the cell voltage difference is analyzed with respect to the parameter change between the cell. An average current sharing con- 116 Figure 4.24: The output current and voltage waveforms in parallel parallel connection (simulated). (i)Output voltage(100V/Div), (ii)Output current(2A/Div) trol is implemented that reduces the error voltage from 10% to 0.8% of the nominal output voltage 117 Figure 4.25: The output current and voltage waveforms in parallel parallel connection (experimental). (1)Output current(5A/Div), (2)Output voltage(100V/Div) Figure 4.26: The output current waveforms in parallel parallel connection(simulated). (i)Output current(2.5A/Div), (ii)UPEC cell1 output current(1A/Div), (iii)UPEC cell2 output current(1A/Div) 118 Figure 4.27: The output current waveforms in parallel parallel connection(experimental). (3)Output current(2A/Div), (1)UPEC cell1 output current(2A/Div), (2)UPEC cell2 output current(2A/Div) Figure 4.28: The output current dynamic response when load changes(simulated). (i)Output current(5A/Div), (ii)UPEC cell1 output current(2.5A/Div), (iii)UPEC cell2 output current(2.5A/Div) 119 Figure 4.29: The output current dynamic response when load changes(simulated). (1)UPEC cell1 output current(2A/Div), (2)UPEC cell2 output current(2A/Div) Figure 4.30: The output current and voltage dynamic response when load changes(simulated). (i)Output voltage(100V/Div), (ii)Output current(5A/Div) 120 Figure 4.31: The output current and voltage dynamic response when load changes(experimental). (1)Output current(5A/Div), (2)Output voltage(100V/Div) 121 Chapter 5 Distribution Power Systems - Full Bridge Operation and Three Phase Operation Using UPEC Cells 5.1 Full Bridge Operation Using UPEC Cells A full bridge inverter is shown in Fig.5.1. This inverter consists of two one-leg inverters. Here, the diagonally opposite switches (TA+ , TB− ) and (TA− , TB+ ) from the two legs in Fig.5.1 are switches as switch pair 1 and 2, respectively. With this type of PWM switching, the output voltage waveform of leg A is identical to the output of the basic one-leg inverter, which is determined in the same manner by comparison 122 id + + Vd + Vd/2 - DA+ TA+ Vd/2 TB+ A DB+ A O TA- DA- - TB- i0 + vo=vAo-vBo DB- Figure 5.1: Single-phase full-bridge inverter of Vcontrol and Vtri . The output of inverter leg B is negative of the leg A output; for example, when TA+ is on and VAo is equal to + 12 Vd , TB− is also on and VBo = − 12 Vd . Therefore vBo = −vAo (t) and vo (t) = vAo (t) − vBo (t) = 2vAo (t) Therefore, the peak of the fundamental-frequency component in the output voltage (Vˆo1 ) can be obtained as: vˆo1 = ma Vd 5.2 (ma ≤ 1.0) Full Bridge Configuration Using UPEC Cells In this configuration we will connect the DC links of the two basic cells in parallel, while the output is connected in series. The configuration is shown in Fig.5.2. Suppose 123 H U W V P + M N Cell Cbus Vin Vo H U W V P M - V1 N Cell V2 Cbus Communication Bus Figure 5.2: Full-Bridge Single Phase Configuration Using Two UPEC Cells the output waveforms for two cells are given as: V1 = A1 sin(ωt + θ1 ), A1 = ma1 Vin , 2 ma1 = Vˆcontrol1 Vˆtri V2 = A2 sin(ωt + θ2 ), A2 = ma2 Vin , 2 ma2 = Vˆcontrol2 Vˆtri where A1, A2 are peak value of the output fundamental, ω1 , ω2 their angular frequency, and θ1 , θ2 their phase angle. In order In order to get the Vo , we assume: Vo = A sin(ωt + Φ) then we get: Vo = V1 − V2 = A1 sin(ωt + θ1 ) − A2 sin(ωt + θ2 ) = A1 sin(ωt + θ1 ) + (−A2 ) sin(ωt + θ2 ) (5.1) 124 According to the conclusion we got in Section 4.2: A1 sin(ωt + θ1 ) + A2 sin(ωt + θ2 ) = [A1 + A2 cos(θ2 − θ1 )]2 + [A2 sin(θ2 − θ1 )]2 × × sin(ωt + θ1 + Ψ) Ψ = arctan A2 sin(θ2 − θ1 ) A1 + A2 cos(θ2 − θ1) We can get: A1 sin(ωt + θ1 ) − A2 sin(ωt + θ2 ) = [A1 − A2 cos(θ2 − θ1 )]2 + [A2 sin(θ2 − θ1 )]2 × × sin(ωt + θ1 + Ψ) −A2 sin(θ2 − θ1 ) A1 − A2 cos(θ2 − θ1) A2 sin(θ2 − θ1 ) = arctan A2 cos(θ2 − θ1) − A1 Ψ = arctan ⇓ V0 = A sin(ωt + Φ)      A=      (5.2) [A1 − A2 cos(θ2 − θ1 )]2 + [A2 sin(θ2 − θ1 )]2 Φ = θ1 + ψ          Ψ = arctan A2 sin(θ2 −θ1 ) A2 cos(θ2 −θ1 )−A1 According to the derivation, we can obtain a single phase full bridge operation 125 when the two UPEC cells output voltage are as follows:      V1 = A sin(ωt)     V2 = A sin(ωt + π) The full bridge operation output voltage function is: V0 = 2A sin(ωt) = 2ma Vin sin(ωt) 2 = ma Vin sin(ωt) (5.3) The calculation results match the principle of the full bridge single phase inverter. Now we will analyze the effect due to different L-C filter parameters. Fig.5.3 shows the actual voltage between two full bridge connected cells. ZL1 L1 ZL2 Vo Rl1 V1 ZC1 Rl2 Rc1 Rc2 C1 C2 L2 V2 ZC2 O Figure 5.3: Full Bridge Output Voltage Between Two UPEC Cells Vo = ZC1 ZC2 V1 − V2 ZC1 + ZL1 ZC2 + ZL2 126 In this demonstration circuit, we have V1 = V sin ωt V2 = V sin(ωt + 180o ) = −V1 then we can get Vo = ( ZC1 ZC2 + )V sin ωt ZC1 + ZL1 ZC2 + ZL2 In this equation:      ZL = RL + jXL (XL = ωL)     ZC = RC − jXC (XC = 1 ) ωC Then we have: ZC RC − jXC = ZC + ZL RC − jXC + RL + jXL RC − jXC = RC + RL + j(XL − XC ) • In the ideal situation:     RL1 = RL2 = 0           RC1 = RC2 = 0  L1 = L 2 = L C1 = C2 = C               We can derive the difference of the parameters as follows: ZC1 ZC2 −jXC −jXC + = + ZC1 + ZL1 ZC2 + ZL2 −jXC + jXL −jXC + jXL 2XC = XC − XL 127 = 2 ωC 1 ωC = 2 − ωL (ω = √ 1 ) LC We can get the output voltage: Vo = 2V sin ωt • In practice, the inductor and capacitor have a internal serial resistor ESR. There is always a small difference between the values for the resistor and even the inductor and capacitor. All these factors will cause the error voltage to appear at the output. From Fig.4.15, we can derive Vo as follows: ZC1 ZC2 RC1 − jXC1 RC2 − jXC2 + + = ZC1 + ZL1 ZC2 + ZL2 RC1 + RL1 + j(XL1 − XC1 ) RC2 + RL2 + j(XL2 − XC2 ) 2 2 C1 RC1 + XC1 arctan −X RC1 = L1 −XC1 (RC1 + RL1 )2 + (XL1 − XC1 )2 arctan X RC1 +RL1 + 2 2 C2 RC2 + XC2 arctan −X RC2 L2 −XC2 (RC2 + RL2 )2 + (XL2 − XC2 )2 arctan X RC2 +RL2 (5.4) After substituting the following parameters      RL1 = 4.05Ω           RL2 = 3.35Ω           L1 = 10.52mH     L2 = 10.26mH           C1 = C2 = 2.05uF           RC1 = RC2 = 0.07Ω 128 into Eq.5.4, we can get: ZC1 ZC2 1553.5 − 89.99o 1553.5 − 89.99o + = + ZC1 + ZL1 ZC2 + ZL2 1550.2 − 89.85o 1550.28 − 89.87o o o = ej(−0.14 ) + ej(−0.12) = cos(−0.14)o + j sin(−0.14)o + cos(−0.12)o + j sin(−0.12)o = [cos(−0.14)o + cos(−0.12)o ] + j[sin(−0.14)o + sin(−0.12)o ] ≈ 2 + j(−4.534 × 10−3 ) Vo ≈ 2V sin ωt + j(−4.534 × 10−3 )V sin ωt From the analysis, we can find that the difference L and C parameters will have a very small effect for the output voltage when connected in full bridge configuration. 5.2.1 Synchronization Problems In order to implement the full bridge function, we also need to synchronize the two cells inner reference address pointer update rate. According to the method we used in the parallel parallel operation, we found that the variable “counter” is an address pointer and relative to the start point of the reference look up table. If we set the two cell reference start point 180o phase shift, the “counter” value of the two cells would be the same. Then we can synchronize the cells with the same method as we did in parallel parallel operation. Fig.5.4 shows the proposed control scheme. The control parameters are the same as the ones used in single UPEC cell. We can look one of the cell as master and the other as slave. In the initial stage, we still need the 129 master measured V o 1/Z measured i o vo* + PI iL* vi + + PI 1/(Ls+R L) iL vo vo iL + io (1/Cs)+R C vo ic - 180o phase shift slave measured V o 1/Z measured i o vo* + PI vo vi + iL* + PI iL 1/(Ls+R L) vo - iL + io (1/Cs)+R C vo ic Figure 5.4: The Control Block Diagram in Full Bridge Operation GPIO pins to let the two cells start running program at the same time. In the steady stage, the master will send the counter value to the slave every one fundamental cycle to realize the synchronization. 5.2.2 The Simulation and Experimental Results Fig.5.5 and Fig.5.6 shows the simulated and experimental results of the steady state voltage waveforms. The phase difference between two UPEC cells is 180o . And the full bridge output voltage peak value is two times of single UPEC cell output voltage peak value. This results match the theory. Fig.5.7 and Fig.5.8 shows the simulated and experimental results of the steady state output current and voltage waveforms. Fig.5.9 and Fig.5.10 show the simulation and experiment results of the 130 Figure 5.5: The output voltage waveforms of full bridge connection UPEC (simulated). (i)full bridge output voltage(200V/Div),(ii)Cell1 output voltage(100V/Div), (iii)Cell2 output voltage(100V/Div) system dynamic response when load changing. 5.3 5.3.1 Parallel Input Three Phase Output Operation Three Phase Inverter Investigation The most frequently used three phase inverter circuit consists of three legs, one for each phase, as shown in Fig.5.11. The output of each leg, for example vAN (with respect to the negative dc bus), depends only on Vd and the switch status; the output voltage is independent of the output load current since one of the two switches in a leg is always on at any instant. In the linear region (ma ≤ 1.0), the fundamental-frequency component in the 131 Figure 5.6: The output voltage waveforms of full bridge connection UPEC (experimental). (4)full bridge output voltage(200V/Div),(2)Cell1 output voltage(100V/Div), (3)Cell2 output voltage(100V/Div) output voltage varies linearly with the amplitude modulation ratio ma . The peak value of the fundamental-frequency component in one of the inverter legs is (VˆAN )1 = ma Vd 2 Therefore, under star connected system, the line-to-line peak voltage as the fundamental frequency, due to 120o phase displacement between phase voltages, can be written as √ 3VˆAN √ 3 = ma Vd 2 VˆLL = 0.866ma Vd (ma ≤ 1.0) 132 Figure 5.7: The output current and voltage waveforms of full bridge connection UPEC (simulated). (i)full bridge output current(5A/Div),(ii)full bridge output voltage(200V/Div) 5.3.2 Configuration Using UPEC Cells With Delta Connected Load To produce a three phase DC/AC converter, three cells are required. The input terminals P and N of all cells are connected together, while the triangular connected load is connected between U terminals of the three cell. The configuration of this connection is shown in Fig.5.12. We give the three sinusoidal control reference voltages that are 120o out of phase and the same m value, the output voltage of each UPEC cells are:      V1 = A sin(ωt)      V2 = A sin(ωt − 120o )          V3 = A sin(ωt + 120o ) 133 Figure 5.8: The output current and voltage waveforms of full bridge connection UPEC (experimental). (1)full bridge output current(5A/Div),(4)full bridge output voltage(200V/Div) According to the Equation 5.2, the line-line voltages are calculated as follows:      Va = V1 − V2 =      Vb = V2 − V3 =          Vc = V3 − V1 = √ 3 mVd 2 √ 3 mVd 2 √ 3 mVd 2 sin(ωt + 30o ) sin(ωt − 90o ) sin(ωt + 150o ) The calculation results exactly match the principle of the three phase inverter. Because the load is delta connected, the output phase voltages are equal to the line-line voltages. The peak value of the line-to-line currents and the phase currents are shown as follows: IˆLL1 = √ 3Iˆa 134 Figure 5.9: The dynamic response of output current and voltage waveforms of full bridge connection UPEC (simulated). (i)full bridge output current(10A/Div),(ii)full bridge output voltage(200V/Div) With Star Connected Load The configuration of the star load connection is shown in Fig.5.13. We give the three sinusoidal control reference voltages that are 120o out of phase and the same m value, the output voltage of each UPEC cells are:      V1 = A sin(ωt)      V2 = A sin(ωt − 120o )          V3 = A sin(ωt + 120o ) 135 Figure 5.10: The dynamic response of output current and voltage waveforms of full bridge connection UPEC (experimental). (1)full bridge output current(5A/Div),(4)full bridge output voltage(200V/Div) The cell voltages are equal to the phase voltages. According to the Equation 5.2, the line-line voltages are calculated as follows:      Va = V1 − V2 =      Vb = V2 − V3 =          Vc = V3 − V1 = √ 3 mVd 2 √ 3 mVd 2 √ 3 mVd 2 sin(ωt + 30o ) sin(ωt − 90o ) sin(ωt + 150o ) The relations of the vector is shown as Fig.5.14. The calculation results exactly match the principle of the three phase inverter. Because the load is triangular connected, the output phase currents are equal to the line-line currents. The peak value of the line-to-line currents and the phase currents. 136 id + + Vd A - A DC+ A O + Vd/2 - DB+ TC+ DA+ TB+ TA+ Vd/2 TA- DA- - TB- DB- TC- DC- N A B C Figure 5.11: Three phase inverter 5.3.3 Synchronization Problems In order to implement the three phase function, we need to synchronize the three cells inner reference changing speed. The synchronization method is the same as the one we mentioned in Sec.5.2.1 except that we need to set the three cell’s reference start point 120o phase shift. The proposed control scheme is shown as Fig.5.15. The control parameters are the same as the ones used in single UPEC cell. We also can look one of the cell as master and the other two as slaves. In the initial stage, we still need the GPIO pins to let the three cells start running program at the same time. In the steady stage, the master will send the counter value to the slaves every one fundamental cycle to realize the synchronization. 137 H U W V P + M N Cell I1 V1 Ia Va Cbus H U W V P Vin M N Cell I2 Vc V2 Ib Cbus M - N Vb H U W V P Cell Ic I3 V3 Cbus Communication Bus Figure 5.12: Three Phase Configuration Using Three UPEC Cells With Delta Load 5.3.4 The Simulation and Experimental Results With Delta Connected Load Fig.5.16 and Fig.5.17 shows the simulated and experimental results of the three phase voltage and phase current waveforms. Because the load is connected as delta shape, the phase voltage and line-to-line voltage are the same. The phase difference of the phase current and voltage are all 30o , −90o , and +150o . Fig.5.18 shows the simulated results of the relations between the three phase line-to-line current and 138 H U W V P + M N Cell I1 V1 Ia Va Cbus H U W V P Vin M N Cell I2 Vc V2 Ib Cbus H U W V P M - N Vb Cell I3 V3 Ic Cbus Communication Bus Figure 5.13: Three Phase Configuration Using Three UPEC Cells With Star Load phase current waveforms. From these figure we can find that the phase difference is 0o , −120o , +120o for line-to-line current and 30o , −90o , +150o for phase current. The peak value of the line-to-line current is about √ 3 times of the phase current. Fig.5.19 and Fig.5.20 show the relevant experimental results of the phase and line-toline currents. With Star Connected Load Fig.5.21 shows the simulated results of the relations between the three phase lineto-line voltage and phase voltage waveforms. We can find that the phase difference is 139 Figure 5.14: Three Phase Vector Relation Diagram 0o , −120o , +120o for phase voltage and 30o , −90o , +150o for line-to-line voltage. The peak value of the line-to-line current is about √ 3 times of the phase voltage. Fig.5.22 and Fig.5.23 shows the experimental results of the three phase voltage and line-toline voltage waveforms. Fig.5.24 and Fig.5.25 shows the simulation and experiment results of the output current waveforms. Because the load is connected as star shape, the phase current and line-to-line current are the same. 5.3.5 Multi-phase systems Using the method described above more than 3 cells can be connected to produce multi-phase systems with 6,9,15 phases. Such systems can be used to feed multi-phase motors that give higher efficiencies and redundancies. In addition to the multi-phase operation, paralleling cells can be used to increase the power rating of the system. In principle, the experiment above demonstrates a multi-phase system with 3 phases and 140 can be extended further with more number of cells with appropriate phase difference between the phases. 5.4 Summary A distributed power supply system concept is presented using two cells to produce a full wave single phase operation. The idea is extended further to multi-phase systems. The synchronization method used for paralleling can also be extended to multi-phase operation. Thus the utility of the research to built distributed power supply systems is demonstrated. 141 master measured V o 1/Z measured i o vo* + PI iL* vi + 1/(Ls+R L) iL vo + PI vo iL + io (1/Cs)+R C vo ic - 120 o phase shift slave 1 measured V o 1/Z measured i o vo* + 120o phase shift PI iL* vi + 1/(Ls+R L) iL vo + PI vo iL + - io (1/Cs)+R C vo ic 120 o phase shift slave 2 measured V o 1/Z measured i o vo* + PI vo iL* vi + + PI iL 1/(Ls+R L) vo - iL + io (1/Cs)+R C ic Figure 5.15: The Control Block Diagram in Three Phase Operation vo 142 Figure 5.16: The phase(line-to-line) voltage waveforms of three phase connection UPEC with Delta Load Connection (50V/Div)(simulated) Figure 5.17: The phase(line-to-line) voltage waveforms of three phase connection UPEC with Delta Load Connection 100V/Div(experimental) 143 Figure 5.18: The phase and line-to-line current waveforms of three phase connection UPEC with Delta Load Connection (simulated). (i)Line-to-line current wavefomrs(10A/Div),(ii)Phase current waveforms(5A/Div), Figure 5.19: Output Phase Current with Delta Load Connection 5A/Div (experimental) 144 Figure 5.20: Output Line-to-Line Current with Delta Load Connection 5A/Div (experimental) Figure 5.21: The output voltage waveforms of three phase connection UPEC (simulated). (i)Output line-to-line voltage(200V/Div). (ii)Output phase voltage(100V/Div) 145 Figure 5.22: The line-to-line voltage waveforms of three phase connection UPEC with Star Load Conncection 100V/Div(experimental) Figure 5.23: The phase current waveforms of three phase connection UPEC with Star Load Conncection 1A/Div(experimental) 146 Figure 5.24: The line-to-line voltage waveforms of three phase connection UPEC with Star Load Connection 100V/Div(Simulated) Figure 5.25: The phase voltage waveforms of three phase connection UPEC with Star Load Connection 20V/Div(experimental) 147 Chapter 6 Network Communication Investigation Inter cell communication is the back bone of the proposed concept of system integration. A deterministic network is used for this purpose. In the foregoing several chapters, we have solved the basic synchronization problem and got some results in different configurations. These results show the probability to configure a distributed software architecture between the UPEC cells. The ultimate goal of the overall UPEC project is to build a flexible, reliable, inexpensive, fast and open control structure that would follow so-called “Plug and Play” (PnP) principles. This project investigated the problem of synchronization as applied to DC/AC configuration. However, in this section a survey of network based communication method will be carried out. 148 6.1 Survey of Local Area Network Architecture Network based communication is being increasingly used in industrial and process control applications. In order to provide the “Plug and Play” function we will look into a communication network based solution. In the communication network, two types of networks are generally used: • Local area networks (LANs) providing communications over a relatively small area • Wide area networks (WANs) providing communications over several kilometers, across the nation, or around the globe. In these different types, a LAN is a data communication system, usually owned by a single organization, that allows similar or dissimilar digital devices to talk to each other over a common transmission medium. We may regard a LAN as a resourcesharing data communication network [78], [79]. There are mainly 4 topologies of LAN: Star, CSMA/CD, Token-Ring, Token-Bus [80], [81]. We will give a brief description of their characteristic in the following section. 6.1.1 Star Topology Star topology is shown in Fig.6.1. A star LAN consists of a central controller and transmission lines connecting cells to the controller. The central controller establishes the connection, facilitates the communication, and terminates the connection 149 1 Central controller 4 2 3 Figure 6.1: Star Topology at the end of the communication among any pair of network cells. The point-to-point interconnection is suitable for optical fiber-based implementation. They allow the interconnection of more nodes, are less prone to catastrophic failure, and are relatively flexible. The central node is a complex one from the hardware standpoint. It is also a limiting element in the growth of this topology because it requires the central node to have a spare port to plug in a new link. The delay caused by the central node affects the performance of the network. The star network exhibits growth limitations, low reliability, poor expandability. 6.1.2 CSMA/CD Topology CSMA/CD (Carrier Sense with Multiple Access/Collision detection) topology is shown in Fig.6.2. Only a single cable is used for the connection. All cells are connected to this cable. Each cell has its own micro-controller to communicate with the central 150 6 5 4 1 2 3 Figure 6.2: CSMA/CD Topology node. Each cell has a unique physical address on the network, usually implemented by means of a hardwired address plug or a row of switches. Messages are broadcast to all nodes on the network. Probabilistic–Upper bound cannot be given on the access time for a given cell trying to access the bus for transmission 6.1.3 Token-Ring Topology Token-Ring topology is shown in Fig.6.3. A special 8-bit pattern called a token 1 2 6 3 5 4 Figure 6.3: Token-Ring Topology 151 which gives the right to use the medium circulates round the ring. In this topology, a break anywhere in the cable will usually cause the entire segment to be inoperable until the break is repaired. The ring consists of a number of nodes interconnected by segments of the communication medium which linking together the cell repeaters in a loop. These repeaters pass on serial data from one segment to the next, but also allow the attached cell to read the information as it passes deterministic–if a maximum packet size is decided upon, the maximum time interval between successive appearances of the token can always be calculated. 6.1.4 Token-Bus Topology Token-Bus topology is shown in Fig.6.4. The token bus is considered by many to logic ring A B E C F D G H Figure 6.4: Token-Bus Topology combine the good features of CSMA/CD(namely its passive, flexible medium) and the token ring(its deterministic token access protocol). The token is circulated among 152 those cells that have some information to transmit. Such cells form a logical ring. The sequence does not depend upon the physical location of the cells. Fig.6.4 shows a typical ordering of cells on a bus with the sequence AEFHCA. In order to avoid the possibility of two or more cells capturing the token at the same time, an explicit address of the next cell to receive the token is attached to the token. For this reason, the process of token-passing in bus LANs is referred to as explicit token-passing as opposed to the implicit token-passing used in ring LANs. There is an elaborate mechanism for adding cells to the logical ring and removing them from the logical ring. The size of the logical ring varies with the variations in the traffic load of the network 6.2 Deterministic Ethernet Real-Time Control 6.2.1 Network Requirement of Hard Real-Time Systems Power electronics systems are hard real-time systems. The support of real-time systems demands for the use of communication protocol with predictable timing characteristics, since real-time systems are defined as those systems whose operation depends not only on the logical result of computation, but also on the time at which the results are produced. The following are the requirements needed for the protocol to operate hard real-time systems: • Message collisions are not allowed. 153 • Timely execution of tasks within their associated deadlines. • 100% error-free guarantee of message. • Adaptive to network traffic by dynamic prioritization of messages. • Maximum upper bound on access delay. 6.2.2 Non-Determinism in Ethernet CSMA/CD Within the four topologies, CSMA/CD is the most popular LAN technology with 80% of the world’s network based on this protocol. It’s low price and wide acceptance, has created much eagerness to expand its scope of application to the factory field floor, where real-time requirements are to be fulfilled. However, it is difficult to build a real-time control network using Ethernet CSMA/CD protocol, because it’s MAC (Medium Access Control) protocol is based on a probabilistic algorithm. The BEB (Binary Exponential Backoff) algorithm in Ethernet CSMA/CD has a nondeterministic access delay, leading to an unpredictable timing behavior of the delivery of messages which have time-critical constraints. 6.2.3 Investigation of CSMA/DCR Deterministic Collision Resolution Algorithm CSMA/DCR (Deterministic Collision Resolution)was proposed and analyzed by the Department of Computer Science and Engineering, India Institute of Technology, 154 Madras at 1998. CSMA/DCR functions are similar to Ethernet CSMA/CD when there are no collisions. However, when a collision occurs during the first transmission attempt, all nodes enter collision resolution mode as in DCR. In the collision resolution mode, transmission rights are given to nodes in a pre-determined order depending on the position of the node in the binary tree map and according to their Laxity (Laxity is the amount of time messages can be delayed before delivery deadline expires). Messages with smaller laxity are given higher priority access to the medium. This methodical approach to collision resolution bounds the worst case channel access delay because the binary tree map is traverse in a pre-determined order and each node gets its turn to transmit, as determined by its position in the tree. However, there can still be collision and message loss. The following describes the protocol in greater detail. 6.3 The Investigation Of UPEC Communication Protocol 6.3.1 Structure Of Communication Topology A structure and communication protocol was investigated as a part of the projet along with a Final year project [82]. It has built the structure of UPEC cells communication topology. In his topology, all UPEC units are cascaded in a straight line bus topology. Each UPEC unit has an internal section of the bus, which when cascaded with multiple units, will form a complete bus structure topology. See Fig.6.5. There 155 Central Controller Cell 0 Cell 1 Cell 2 Cell 3 Figure 6.5: UPEC Bus Topology are three levels in the communication hierarchy shown in Fig.6.6. external inputs Central Controller UPEC system Master Slave Slave Slave Slave Figure 6.6: Communication Hierarchy • Central Controller: At the top of the hierarchy is the Central Controller (SuperMaster). It functions as an interface between external inputs and the UPEC system. It processes requirements as specified by external inputs, and then converts these requirements to useful information in the form of UPEC System Control Data. This System Control Data is handed over to the master to be 156 interpreted further. The Central Controller fetches information from the external inputs periodically. Hence, information flow between Central Controller and master is likewise periodic. • Master: acts as an interface between the central controller and the other slaves. Physically, the Master is similar to the slaves, but different in responsibilities. When the central controller passes system control Data to the master periodically, the master further interprets this data and converts it to tasks specific to individual slaves. • Slave: The slave forms the 3rd level in the communication hierarchy. It is the lowest level in the system with the responsibility of executing tasks as specified by the master. 6.3.2 System Overview According to his communication topology, we can divide the communications operation into 6 modes: initialization mode, idle mode, normal operation mode, passing mode, active mode, synchronization mode, see Fig.6.7. Initialization Mode: Initialize the whole system and dynamically assigns the cell address During this mode, the central controller is wired to a user interface such as a computer with interface software. Suppose we want to realize the three phase inverter 157 Local address end of packet ACTIVE end of packet PASSING Non-local address local address NORMAL SYNCHRO synchro. identifier end of start-up INITIALIZATION End of initialization IDLE Figure 6.7: State Transition Diagram for Communication Controller function and we have three cells in connection. Each cell has it’s own dynamic ID (identity) address. When powered up, the following functions will be carried out in steps: • Each cell reports its ID to the central controller. The central controller will know the number of cell in the system. • The central controller will transmit a data packet with new device ID and the concrete control variables to each cell one at a time. That means, the central controller will transmit the next data packet after receiving the acknowledgement from each cell. The control variables include switching frequency information, duty cycle information and phase information. 158 • The cells in the bus will receive the data packet according to the distance and adopt the ID as its ID. After receiving the data, each cell will transmit an acknowledgement to the central controller. • After assigning the ID and receiving the acknowledgement from each cell, the central controller can get a distance information between every cell and the central controller. It then can draw a transmission time delay map according to the data transmission rate (decided by the communication media), the distance and the cell numbers. Idle Mode: Waiting for the data packet to arrive After the initialization mode, the cells are in the idle state. The gate drive stages are disabled. The cells are all waiting for the start bit from the central controller to start the PWM GP timer, refer to Section.4.3.3. In the CSMA/DCR type of network, each cell introduces a delay in data propagation path. Meaning that if we send start command through the network, each cell is going to receive the command with as many time delay Td , as where are cells between that cell and the central controller. The error will generate time shifted PWM signals at the outputs, causing low frequency harmonics. The delay from start to end should be kept to a minimum. This problem is solved if we introduce the different time delay in the start-up command packet. Format of start or start-up frame is shown in Fig.6.8. The frame starts with start-up command and is followed by the cells’ 159 Command node (n) address concrete time delay1 node (n) address concrete time delay2 ...... node 0 address Figure 6.8: Data Format of Start-Up Frame addresses and time delay fields which are used for propagation compensation. In the initialization mode, the central controller has calculated the transmission time delay map for cell1, 2 and 3. The first address to be transmitted is of the cell that is last to receive the frame. The number of address data blocks sent equals to the number of cells on the bus. The first field is a start-up command that alerts the cells to start the PWM GP timer. Next are the address fields of the cells being start-up. After the start-up command is passed, the node awaits its address field. When the address is received, the cell will start the PWM GP timer. Because all the addresses are in reverse order and time delayed for the cell propagation delay all the addresses will arrive at the destination cells at almost the same time. This method will minimize the propagation delay. Normal Operation Mode Each UPEC cell is a comparatively independent individual. After the idle mode, the UPEC cell will do its own job according to the control variables the central controller sent to them in the initialization mode. In the normal operation mode, the use interface is disconnected. The system comes to “life”. The central controller will assign the nearest cell the role of master and will send the transmission time 160 delay map to the master cell in order to realize the synchronization mode. At the same time, the central controller will receive the output current variable from the cells. Using these received variables, the central controller can get the average and the different output current values and send them to the correspondent cells. Passing Mode: passing the information to the central controller In the passing mode, each cell will pass its own output current to the central controller. Active Mode: incoming data packet has the address of the cell In the active mode, the data is stored in corresponding buffers. Synchronization Mode: after receiving the synchronization command from the master In the synchronization mode, the master will send its’ own counter value according to the transmission delay time map to the other slave cells periodically. When receiving the counter value, the slave cells will reload to the corespondent double buffers and the buffers will refresh when period match. 161 6.4 Summary There are certain advantages of using a network based communication in order to implement “plug and play” functions. However due to the hard real-time constraints, reliability and ease of expansion, we cannot use existing network solutions for our purpose. A new deterministic network has been investigated. It was implemented as a part of a final year project, however the metrics of design have been derived and correlated to the this project. We have discussed the effect of delays in chapter 4.3.3 and have shown the constraints of design on a deterministic network. The transportation delays in CSMA/DCR protocol have to be compensated or minimized by using higher bandwidth fibre optic networks. In order to achieve a true “Plug and Play” function for the UPEC system further work has to be carried out on developing deterministic networks and protocols suitable for the application. 162 Chapter 7 Conclusions The main objective of the present research is to investigate and develop a standard cell concept that can be configured into DC/AC, AC/DC and DC/DC converter. Such configurations can be used in DPS to enhance power capability by paralleling. In addition, redundancy and reliability can be increased. Cells can be connected in different configurations to achieve multi-phase systems. Three phase converter is commonly used as a single unit, however, the use of cell based systems to generate multi-phase system can be very useful in development of multi-phase motor drives. A UPEC cell is used as PEBB. The basic cell is based on the most common halfbridge leg structure because it is the commonly used switching topology that can be found in AC/DC, DC/DC, and DC/AC conversion. In this report, we mainly use hard-switched DC/AC converter structure to achieve our objective. This kind of structure can also be easily extended to the other two converters configuration by 163 changing or synchronizing the reference wave. The cell includes power semiconductors, the required passive components, the driver electronics and the controller to get a standard, self-contained unit. After introducing the basic structure and operating concept of the UPEC cell, we design the cell to meet certain performance criteria. In the controller part, we used the PI control because it is simple, robust especially as the switching frequency of modern power devices increases. It is also easy to use in the parallel operation using the instantaneous voltage feedback loop control. In order to get the fast response, high accuracy and high-level performance from the system, a current loop is implemented inside the voltage loop. As a result, for the single UPEC, the overall control loop incorporates an inner current loop, an outer output voltage loop, and a fixed switching frequency approach. The fixed switching frequency approach produces a defined frequency spectrum at the inverter output, which makes it easier to design an output filter and an EMI filter to prevent interference with communication circuits. To implement a digital closed loop control, DSP TMS320F243 is used. It samples the output voltage and current value at 10kHz and compares it with the inner sine reference value after scaling. Using the control loops the PWM signal to the drive the top and bottom switch is generated. In the hardware part, IGBT SK20GB123 is used to implement the power switch function. Because the driver capacity of the signals from DSP is not large enough to drive the switch directly, we designed the driver circuit with driver SKHI22 to enhance the capacity. In order to protect the DSP, we also used the isolation chips 164 SFH6325 and isolated DC/DC converter to isolate the digital ground and analogue ground. The layout design is very important for this type of high speed and high power switch since it can cause EMI problems. An over voltage due to poor leakage inductance can damage the IGBT. We used the double layer PCB where each high current path is parallel above its returns path on the other side of the board. This produces a less than 5% overshoot voltage at turn-off. Based on the analysis of the basic UPEC cell structure and development, we can use it to implement the parallel input parallel output, full bridge and three phase configuration. In the parallel parallel configuration, the main problem is of the synchronization and circulating current elimination. To solve the synchronization problem, a phase lock loop or more complicated network communication method is used. However, we used a simple and practical way to solve the synchronization problem. Using the simple serial data communication and the characters of the inner reference sine wave look up table, we can get a good synchronization. In the parallel parallel configuration, we use the average current sharing scheme to solve the circulating current problem that is caused due to parameter variation between the two cells. We analyzed the difference before and after applying this method. The mean value of the error voltage is reduced from 10% to 0.8%. Furthermore, it is very easy to extend the synchronization method to more cells parallel connection because it is no relation with the cell number and configuration. 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(Accepted) [...]... cost of this cells will be lower Engineering implementation of power electronic systems would then be reduced to “Plug-n-Play” using standard cells 1.2.2 Conceptual Design of A Universal Power Electronic Cell Power electronic converters can be broadly classified as DC/ DC, DC/ AC, AC /DC and AC/ AC converters We can further classify them as hard-switched or soft switched converters Each of these converters... electrical power for manufacturing operations Sales of power electronics equipment exceeded $60 billion each year, and another $1 trillion in hardware electronics sales [3] Power electronics plays a major part in most industrial and commercial systems For efficient use of power in these systems, switched mode power converters are necessary Requirements of many of these system are unique, hence, power converters... converters consists of power electronic switches and energy storage elements They form the power electronic circuit The control of the switch will depend on the mode of power conversion required Of the four topologies described above, DC/ DC and DC/ AC are realized using controllable switches AC /DC and AC/ AC converters have been traditionally realized using line commutated devices such as thyristors and diodes... Universal Power Electronic Cell 1.2.1 Introduction In this section, a improvement concept of a versatile power electronic cell that falls along the natural boundary of technical expertise is proposed The philosophy is to design standard cells so that a combination of such cells should be able to implement any of the widely used converter modes such as AC /DC, DC/ AC, DC/ DC in single phase and three phase... power electronic cell is defined to consist of power semiconductors devices, the required passive components like inductors and capacitors, the driver electronics and the control The cells are basic self-contained units Standardization of cells and their connectivity will lead to reduction of engineering costs in power electronic systems Once standardized 4 and produced in large numbers, the cost of. .. Concept Of Building Distributed Power Systems Using UPEC Cells Modern electronic systems need more complex power electronic systems to meet the requirements for reliability, high density and voltage regulation As a result, a conventional centralized power system with a single high power converter may not be optimal for the systems of the future New trends in the field of high and medium power systems. .. switches and diodes can be used to produce DC/ DC, DC/ AC and AC /DC power converter modes In addition, we add filter components such as an inductor and a capacitor; this would form the basic cell I use a hardswitched basic cell topology to explain the concept of cells and their use in various configurations The basic cell topology is shown in Fig.1.1 It has 6 power terminals P H L M U W P M H U W V UPEC... common power converters Fig.2.3 shows some of the commonly used switching topologies that can be found in AC /DC, DC/ DC and DC/ AC conversion All converters in Fig.2.3 consist of the half-bridge leg structure as the building block In this case the voltage can be applied bi-directionally, and the current flows only in one direction 16 Vo a b c AC /DC Boost Rectifier Vg a b c Vg Vo DC/ DC Converter DC/ AC VSI... standard interfaces and protocols The benefit of it is to allow each section of the power equipment to be independent of the others There are two motivations for plug and play architecture One is for lower cost and increased application The demand for new power electronics products exceeds the resources to supply them The next generation engineer want to design systems on their computers and want power. .. Distributed Power Systems instead of large and lumped power converters [2] These allow standardized designs For these reasons, we can find that the UPEC cell s structure is very simple It is the basic element for many other power converter topologies which are relatively complicated compared to the cell These standard cells can be connected to form different circuit topologies and to implement different power