Novel devices for enhanced CMOS performance

NOVEL DEVICES FOR ENHANCED CMOS PERFORMANCE CHUI KING JIEN NATIONAL UNIVERSITY OF SINGAPORE 2006 NOVEL DEVICES FOR ENHANCED CMOS PERFORMANCE CHUI KING JIEN (B.Eng. (Hons.) NUS) A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2006 Novel Devices for Enhanced CMOS Performance ABSTRACT Complementary Metal Oxide Semiconductor (CMOS) transistors form the basis of many integrated circuit products, such as microprocessor, random access memory (RAM), and digital signal processor (DSP). Continual transistor miniaturization, including scaling down of the transistor gate length and gate dielectric thickness, has been the technology trend for the past few decades. Aggressive CMOS transistor scaling has driven CMOS transistors into the nanoscale regime, making it the most widespread nanotechnology in production today. Further transistor scaling becomes increasingly challenging and faces many difficulties related to physical limitations. A new and emerging trend is the exploration of alternative ways to enhance CMOS transistor performance besides size reduction. The proposed research will be on investigation of novel CMOS transistor structures to enhance performance. The main focus will be on different schemes to form strained silicon transistors for enhanced performance over conventional silicon CMOS transistors where the silicon is not strained. When the crystal lattice of silicon is strained, the electronic properties of silicon will be modified. By engineering the strain introduced, the strain-induced modification of electronic properties can be made to improve the mobility of carriers (i.e. electrons and holes) in silicon. This leads to a higher drive current for CMOS transistors and a corresponding increase in speed of integrated circuits formed using these transistors. Faster integrated circuit speed enables new products or applications with faster computational power or increased functionality. i ACKNOWLEDGEMENTS First and foremost, I would like to thank my main advisor, A/Prof Ganesh S Samudra for his immense guidance and support through these years of my PhD candidature. I have learnt a lot from him, especially in the field of device physics and TCAD simulation work. He has been extremely supportive and has given me the freedom to explore and try out new ideas. I still remember the time when I first ask him what the main focus of my work is about and his answer was “The sky’s the limit!”. I wish to also thank to my other advisor, Dr Yee-Chia Yeo, who has provided me with a lot of guidance and advice these years. I will miss all the long conversations which we always begin on-track but wandered out of scope when new ideas come to our minds. I have benefited a lot through the interactions with members of his research group, both during and after the weekly meetings. In my opinion, the collaborative and enjoyable atmosphere in our group is really unique and I’m proud to be part of it. Special thanks to my research buddy, Kah Wee, who has been a great partner in terms of research work as well as a great friend. I’ll never forget the times when we stayed overnight in the cleanroom, running processes and rushing the manuscript for conferences when it is only hours away from the submission dateline. I’ll also miss all the entertaining conversations and jokes we shared during lunch and while waiting for processes to complete in the cleanroom. ii I wish to express the genuinely enjoyable insights and exchange of perspectives between the official as well as unofficial mentors from Chartered Semiconductors. I would like to thank Dr. Francis Benistant who has given me the chance to learn TCAD simulation and for providing me with the resources to run my never-ending simulation jobs, and the aggressive optimism of Dr. Liu Jinping whose enthusiasm continues to propel endlessly. To the Special Project students, I am grateful for having a wonderful research atmosphere to work in. Some direct contributors which cannot go without mention, Vincent Leong for the TCAD calibration training and valuable comments on TCAD work. And I would also want to take this opportunity to dedicate a big thank you to a very special person - my wife who has been in many ways very supportive and considerate during my entire PhD candidature. Special mention also goes to my parents, siblings and friends whom knowingly or not giving me the most appreciative support. Thank you all! iii TABLE OF CONTENTS ABSTRACT . i ACKNOWLEDGEMENT ……………………………………… ………………………… . ii TABLE OF CONTENTS ………………………………………… …………………………. iv LIST OF FIGURES …………………………………………… …… ………………… . … viii LIST OF TABLES ……………………………………………………….…………………… xviii LIST OF SYMBOLS …………………………………………… …….……… . xix LIST OF ABBREVIATIONS ………………………………… …….……… . xx CHAPTER Literature Review ……….…………… …… 1.1 Motivation …………………………………………………………… ……………………. 1.2 Background ……………………………………………… . 1.2.1 Present Technology Trend : Novel Devices and Architecture for Enhanced Performance CMOS Performance …………… 1.2.2 Channel Strain Engineering …………………………………………………. 1.2.3 Silicon-On-Insulator (SOI) for reduced parasitic capacitance C … . 11 1.3 Objectives of the research …………………………………………………………… .…… 11 1.4 Outline of the report ……………………………………………………………….……… …. 12 CHAPTER Source Drain On DEpletion Layer (SDODEL) for Reduced Junction Capacitance ………………………………………………………………… …………….…….… 13 2.1 Background ……………………………… .…………………………………….……… ……. 13 2.2 Simulation Results …………………………………………………………………………… 15 2.2.1 Reduction in Junction Capacitance …………………………… .……….… 15 2.3 Experimental Results …………………………………………………………… .………… 20 2.3.1 Reduction in Junction Capacitance ……………………… ………………… 22 2.3.2 Subthreshold Characteristics ………………………………………………… 23 iv 2.3.3 Verification of restoration of Vt though simulation ……………… .……. 24 2.3.4 Circuit Speed Measurement ……………………………………………… … . 25 2.3.5 Breakdown Voltage …………………………………………………… ….……… 26 2.3.6 Junction Leakage. ………………………………….…. ……………… ……. 27 2.3.7 Simulation of SDODEL transistors at shorter gate lengths ……… 28 2.4 Summary ………………………………………………………………………………………… 30 CHAPTER Fabrication of Strained Si / relaxed SiGe CMOSFETs ………… … ….… …31 3.1 Background … .………………………………………………………… ………… …… … .31 3.2 Device Fabrication …………………………………………………………………….…33 3.3 Electrical Characterization …………………………………………………………….… 34 3.3.1 Drive Current Enhancement ……………………………………………… 34 3.3.2 Sub-threshold Characteristics ……………………………………… … 37 3.3.3 Circuitry Speed……………………………………………………………… . 42 3.4 Summary …………………………………………………… .………………………………… . 43 CHAPTER Characterization of Strained MOSFET structures with S/D Stressors . 45 4.1 Background ……… .………………………….………………………………………….45 4.2 MOSFET Structure Fabrication …………… ……………………………………… 47 4.2.1 Strained MOSFET Structure Fabrication ……………… …………………… 47 4.2.2 Strain Characterization ……………………………………… .…………………. 49 4.3 Electron Dispersion Spectroscopy (EDS) Analysis ……………………………… 54 CHAPTER Strained nMOSFETs using SiC S/D Regions ………………………… .…………. 57 5.1 Strained nMOSFETs with SiC S/D on Bulk substrate ………………….…….… 57 5.1.1 Background …………… …………………….……………………………… 57 5.1.2 Device Fabrication …………….……………………………… .………… 59 v 5.1.3 Electrical Characterization ……….………………………… …………… 62 A. I-V Characteristics …… .…………….…………………………….62 B. P-N Junction Characteristics ………………………………… 67 5.2 Strained nMOSFETs with SiC S/D on SOI substrate …………… …….…….… 69 5.2.1 Background………………………………………….………………………….69 5.2.2 Device Fabrication …………………………………………… ………… 70 5.2.3 Electrical Characterization ……………………….…………… ………… 74 A. IDsat Dependence on Gate Length LG and Device Width W … 74 B. IDsat Dependence on Channel Orientation …………………… 76 C. Dual Stressors Effect on IDsat and Dependence on Channel Orientation …………………… ………………………………………… 80 5.3 Summary ………………………………………………………………………….……………… 85 CHAPTER Strained pMOSFETs with Ge condensed S/D Regions ……………………… 87 6.1 Strained SOI pMOSFETs with Condensed SiGe S/D ………………… .….…….….87 6.1.1 Background … ………………………………….…………………… .…………….87 6.1.2 Device Fabrication ……………………………………………….… ………… 89 6.1.3 Electrical Characterization ……………………………………………………… 91 6.1.4 Material Characterization …………………….…………………………… …….96 6.2 Strained UTB pMOSFETs with Condensed SiGe S/D ……… ………………….… 99 6.2.1 Background …… .…………………………….………………… .………….99 6.2.2 Optimization of Device Structure and Process Conditions for Increased Strain Effects . 100 6.2.3 Fabrication of Strained UTB pMOSFETs with SiGe S/D ………………101 6.2.4 Electrical Characterization …………………………………… ………… 105 6.3 Summary …………………….……………………………… ………………………….109 CHAPTER Conclusion ……………… .………………………………… ……….……… ……….………… 110 7.1 Summary …………………………………………………… ………………………………… 110 7.1.1 Source / Drain On Depletion Layer (SDODEL) CMOSFET for Reduced Parasitic Capacitance …………………………………………………………………… 110 vi 7.1.2 Strained Si on Relaxed SiGe MOSFET ……………………………………… 110 7.1.3 Material Characterization of Strained Si MOSFET Structures ……… 111 7.1.4 Strained nMOSFETs with SiC S/D Regions …………………… ……… 111 7.1.5 Strained pMOSFETs with Condensed SiGe S/D Regions ……… .… . 112 7.2 Future work ………………………………………………………………………………… .….112 References ……………………………………………………………… .………… …………… 113 List of Conference / Publication ………………………………………………… .…… 121 List of Patents …………………….……………………………………………………………… 123 vii LIST OF FIGURES Figure 1.1 : Germanium has a larger lattice constant (5.658Å) than Silicon (5.431Å). By Vegard’s law. the lattice constant of Si1-xGex will have a larger lattice constant than Si. When silicon is epitaxially grown on Si1-xGex, the silicon layer will be stretched biaxially ………… .…… ……………….…………………………………… … Figure 1.2 : Different type of globally strained silicon substrate wafers. (a) Strained Si / Relaxed SiGe (b) Strained silicon / Relaxed SiGe – On – Insulator (SGOI) (c) Strained Si Directly – On – Insulator (SSDOI) …………………………………………………. Figure 1.3 : Various techniques to introduce different type of strain to the channel region of MOS devices ……………………………………………………………………………… Figure 1.4 : Valence band structure of (a) unstrained Si and (b) tensile strained Si on Si1-xGex. Tensile strain lowers the energy of the heavy hole and spin-orbit sub bands relative to the light hole sub band and modifies the shape of the sub bands [28] … .………… Figure 1.5 : Schematic representation of the constant energy ellipses for (a) unstrained Si and (b) strained Si [10] …………………………………………………………… ……… 10 Figure 1.6 : Conduction band splitting and sub-band energies lineups of Si under biaxial tensile strain [10] …………………………………………………………… ……… 10 Figure 2.1 : Schematic illustration of Silicon On DEpletion Layer (SODEL) nMOSFET. The counter-doped layer (shaded) is of the same doping type as the source/drain regions. As a result of the counter-doped layer, an enlarged depletion region as indicated by the gray region and bounded by dashes is achieved. SODEL pMOSFET has the same structure but of opposite dopant-type …………….…………………………… .… 14 Figure 2.2 : Schematic of a simulated Source/Drain on Depletion Layer (SDODEL) nMOSFET transistor structure showing counter-doped regions (shaded) beneath the source/drain regions. The counter-doped regions are of the same doping type as the source/drain regions. As a result of the counter-doped regions, the depletion region as indicated by the gray region and bounded by dashes is significantly enlarged over that of the control transistor. The original boundary of the depletion region in the control transistor is indicated by dotted lines. SDODEL pMOSFET has the same structure but of opposite dopant-type………….… …………….…… .…………………… 15 Figure 2.3 : (a) Simulated SDODEL nMOSFET device with a gate length of 65nm and (b) Concentration profile of dopants along a vertical line A-A’ as depicted in (a) … . 16 viii SiGe Control 90 0.16 DIBL (V/V) Subthreshold Swing S (mV/decade) 100 80 70 SiGe Control 0.12 0.08 0.04 60 0.00 50 100 1000 100 Gate Length LG (nm) 1000 Gate Length LG (nm) Figure 6.21 : (a) Si0.54Ge0.46 S/D pMOSFET shows improved subthreshold swing over control devices for all gate lengths. Excellent subthreshold swing of less than 70 mV/decade is obtained for the Si0.54Ge0.46 S/D pMOSFET. (b) DIBL characteristics against physical gate length for both control and strained devices 200 160 140 VDS = -1.2 V 120 100 80 60 40 20 VDS = -50 mV 250 Transconductance Gmmax (µS) Transconductance Gm (S) 180 Gate Length, Lg = 70 nm Device Width, w = µm SiGe S/D Control SiGe S/D Control 200 150 100 Gmmax @ VDS = -1.2 V 50 Gmmax @ VDS = -50 mV -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 100 1000 Gate Length LG (nm) Gate Voltage VGS (V) Figure 6.22 : (a) Transconductance Gm as a function of gate bias VGS for both Si0.54Ge0.46 S/D and control pMOSFETs at both high and low VDS. (b) Increasing Gmmax with decreasing gate length LG. Si0.54Ge0.46 S/D pMOSFETs reveal a larger increase in Gmmax with reducing LG due to the larger strain effect of the SiGe S/D regions. 108 6.3 Summary A novel strained-Si pMOSFET comprising SiGe S/D regions formed by local Ge condensation has been demonstrated. By using local Ge condensation, a Si recess etch step in the formation of SiGe S/D can be eliminated. Ge concentration in the source/drain can also be increased using the Ge condensation process, resulting in higher strain in the channel for enhanced hole mobility. This allows the implementation of SiGe S/D structures on ultra thin body SOI devices. Therefore, strained UTB pMOSFETs with nm body thickness were demonstrated. The Ge content (~46%) in the S/D regions is the highest reported to date, realized using a Ge condensation technique. Significant IDsat enhancement was observed in the strained UTB pFET at 70 nm gate length. Excellent device performance can be achieved with this integration scheme, making it a promising option for future high speed devices. 109 CHAPTER Conclusion 7.1 Summary This thesis has examined several novel device structures for enhancement in MOSFET device performance. The key contributions are summarized below followed by recommendations for future work. 7.1.1 Source/Drain On Depletion Layer (SDODEL) CMOSFET for Reduced Parasitic Junction Capacitances. Complementary MOSFET devices with better performance have been fabricated. By simply adding a high energy, low dose implant of the same conductivity type as the S/D, a low, counter-doped layer can be formed beneath the S/D regions. Reduction in parasitic junction capacitance for both n and pMOSFETs have been demonstrated. Fabricated ring oscillator structures also experimentally verify the improvement in circuitry speed. In addition, simulation has been performed to project the feasibility of SDODEL devices for future sub-50nm high speed devices. 7.1.2 Strained Si on Relaxed SiGe MOSFET Complementary CMOS device have been fabricated using a conventional 0.18 µm technology node process flow. Electrical device characterization was performed and drive current enhancement was observed in the strained devices fabricated on strained Si / 110 relaxed SiGe substrates. However, there are also various issues and challenges related to strained Si on relaxed SiGe. Some of these issues and challenges have been addressed. 7.1.3 Material Characterization of Strained Si MOSFET Structures An alternative technique to analyze strain distribution in MOSFET structures have been proposed. This technique involves the analysis of high resolution TEM (HRTEM) images. In particular, this method has been applied on MOSFET structures with S/D stressors. Another technique which involves the use of EDS on TEM images to characterize the Ge content in SiGe S/D regions have also been discussed. 7.1.4 Strained nMOSFETs with SiC S/D Regions A novel strained nMOSFET structure featuring SiC S/D regions is proposed. Devices are fabricated for electrical and material characterization. The use of SiC S/D regions induces a lateral tensile and vertical compressive strain in the Si channel of the device, which benefits electron mobility to give a larger drive current. The implementation of such a structure on SOI substrate for further enhancement in device performance was carried out. Channel orientation dependence and multiple stressor effect are also investigated. 111 7.1.5 Strained pMOSFETs with Condensed SiGe S/D Regions The implementation of SiGe S/D regions on thin body SOI substrates faces potential challenges like control of Si S/D recess etch depth and difficulty in growing SiGe on extremely thin layer of Si. A novel device structure using local condensation is proposed to alleviate these problems. This structure has also been applied on ultra-thinbody SOI substrates with less than 10nm of Si. 7.2 Future Work There are several issues opened up by this thesis that deserve further exploration. These include : • Silicidation of SiC S/D regions. • The effect of various S/D annealing on C substitutional efficiency. • Laser annealing of SiC S/D regions to explore possibility of increasing C substitutional efficiency. • To further increase Ge content in the SiGe S/D MOSFETs to investigate whether higher Ge content in the S/D regions can lead to higher drive current enhancement. • To fabricate local condensed SiGe S/D on different surface orientation. • Reliability issues of SiC S/D and condensed SiGe S/D devices. 112 REFERENCES 1. International Technology Roadmap for Semiconductors, Semiconductor Industry Association, 2003 2. Y. Taur , C. H. Wann and D. J. Frank, ”25nm CMOS design considerations”, IEDM, pp. 789-792, 1998 3. Y.C. Yeo, Q. Lu, P. Ranade, H. Takeuchi, K. J. Yang, I. Polishchuk, T. –J. King, C. Hu, S. C. Song, H. F. Luan and D. –L. Kwong, “Dual-metal gate CMOS technology with ultra-thin silicon nitride gate dielectric” IEEE Electron Device Letters, vol. 22, no. 5, pp. 227-229, 2001 4. B. Chen, M. Cao, R. Rao, A. Inani, P. V. Voorde, W. M. Greene, J. M. C. Stork, Z. Yu, P. M. Zeitzoff, J. C. S. Woo, “The impact of high-k gate dielectrics and metal gate electrodes on sub-100nm MOSFETs”, IEEE Trans. Electron Devices, vol. 46, no.7, pp. 1537-1544, 1999 5. I. De, D. Johri, A. Srivastava, and C. M. Osburn, “Impact of gate workfunction on device performance at the 50nm technology node”, Solid State Electronics, vol. 44, no. 6, pp. 1077-1080, 2000 6. K. Maitra and V. Misra, “A Simulation study to evaluate the feasibility of midgap workfunction metal gates in 25nm bulk CMOS”, IEEE Electron Device Letters, vol. 24, no.11, pp. 707-709, 2003 7. R. Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros and Matthew Metz, “Highk/metal gate and its MOSFET characteristics”, IEEE Electron Device Letters, vol. 25, no.6, pp. 408-410, 2004 8. M. Morita, H. Fukumoto, T. Imura, Y. Osaka and M. Ichihara, “Growth of crystalline zirconium dioxide films on silicon”, Journal of Applied Physics, vol. 58, no.6, pp 2407-2409, 1985 9. K. Rim, S. Koester, M. Hargrove, J. Chu, P. M. Mooney, J. Ott, T. Kanarsky, P. Ronshiem, M. Leong, A. Grill, “Strained Si NMOSFETs for high performance CMOS technology”, VLSI Symposium, pp. 59-60, 2001. 113 10. K.Rim, J. L. Hoyt, J. F. Gibbons, “Fabrication and analysis of deep submicron strained-Si n-MOSFET's”, IEEE Transactions on Electron Devices ,vol. 47, Issue , pp. 1406-1415, 2000 11. Wang, H.C.-H.; Wang, Y.-P.; Chen, S.-J.; Ge, C.-H.; Ting, S.M.; Kung, J.-Y.; Hwang, R.-L.; Chiu, H.-K.; Sheu, L.C.; Tsai, P.-Y.; Yao, L.-G.; Chen, S.-C.; Tao, H.-J.; Yeo, Y-C.; Lee, W.-C.; Hu, C., “Substrate-strained silicon technology: process integration,” IEDM, pp. 61-64, 2003 12. C. Gallon, G. Reimbold, G. Ghibaudo, R. A. Blanchi, R. Gwoziecki, C. Raynaud, “Electrical analysis of mechanical stress induced by shallow trench isolation (MOSFETs)”, ESSDERC, pp.359 – 362, 2003 13. G. Scott, J. Lutze, M. Rubin, F. Nouri, M. Manley, “NMOS drive current reduction caused by transistor layout and trench isolation induced stress”, IEDM., pp. 827830, 1999 14. A. Steegen and K. Maex, “Silicide-induced stress in Si : origin and consequences for MOS technologies”, Material Sci. and Engineering, R38, pp.1-53, 2002 15. S. Ito, H. Namba, K. Yamaguchi, T. Hirata, K. Ando, S. Koyama, S. Kuroki, N. Ikezawa, T. Suzuki, T. Saitoh, T. Horiuchi, ”Mechanical Stress Effect of Etch Stop Nitride and its Impact on Deep Submicron Transistor Design”, IEDM., pp. 247250, 2000 16. C. D. Sheraw, M. Yang, D. M. Fried, G. Costrini, T. Kanarsky, W.-H. Lee, V. Chan, M. V. Fischetti, J. Holt, L. Black, M. Naeem, S. Panda, L. Economikos, J. Groschopf, A. Kapur, Y. Li, R. T. Mo, A. Bonnoit, D. Degraw, S. Luning, D. Chidambarrao, X. Wang, A. Bryant, D. Brown, C.-Y. Sung, P. Agnello, M. Ieong, S.-F. Huang, X. Chen, M. Khare, ”Dual stress liner enhancement in hybrid orientation technology”, VLSI Symposium, pp. 12- 13, 2005 17. T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffman, K. Johnson, C. Kenyon, J. Claus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, J. Siberstein, S. Sivakumar, P. Smith, K. Zadwazki, S. Thompson, M. Bohr, “A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors”, IEDM., pp. 978 – 980, 2003 114 18. Omura, Y.; Kurihara, K.; Takahashi, Y.; Ishiyama, T.; Nakajima, Y.; Izumi, K.; “50-nm channel nMOSFET/ SIMOX with an ultrathin 2- or 6-nm thick silicon layer and their significant features of operations”, IEEE Electron Device Letters, Vol. 18, 5, pp.190 – 193, 1997 19. Yan, R.-H.; Ourmazd, A.; Lee, K.F.; “Scaling the Si MOSFET: from bulk to SOI to Bulk,” IEEE Trans. Electron Devices., Vol. 39, no. 7, pp. 1704-1710, 1992 20. Y.-K. Choi, K. Asano, N. Lindert, V. Subramanian, T.-J. King, J. Bekor and C. Hu, “Ultrathin-body SOI MOSFET for deep-sub-tenth micron era,” IEEE Electron Device Letters, vol. 21, no. 5, pp. 254-255, 2000 21. B. Yu, Y.Wang, H. Wang, Q. Xiang, C. Ricobenne, S. Talwar, M. R. Lin, “70 nm MOSFET with ultra-shallow, abrupt, and super-doped S/D extension implemented by laser thermal process (LTP)” IEDM, pp. 509-512, 1999 22. K. Rim, P. Gusev , C. D'Emic, T. Kanarsky, H. Chen, J. Chu, J. Ott, K. Chan, D. Boyd, V. Mazzeo, B. H. Lee, A. Mocuta, J. Welser, S. L. Cohen, M. Ieong, and H.S. Wong, “Mobility enhancement in strained Si NMOSFETs with HfO2 gate dielectrics,” VLSI Symposium, pp 12-13, 2002 23. E.A. Fitzgerald, Y.-H. Xie, M. L. Green, D. Brasen, A.R. Kortan, J. Michel, Y. –J. Mii and B. E. Weir, “Totally relaxed GexSi1-x Layers with low threading dislocation densities grown on Si substrates”, Applied Physics Letter, Vol. 59, pp. 811-813, 1991 24. E.A. Fitzgerald, Y.-H. Xie, M. L. Green, D. Brasen, A.R. Kortan, J. Michel, Y. –J. Mii and B. E. Weir, L. C. Feldman and J. M. Kuo, “Strain-Free GexSi1-x Layers with low threading dislocation densities grown on Si substrates”, Material Research Society Symposia Proceedings, 1991, 220, 211 25. J. B. Lasky, “Wafer bonding for silicon-on-insulator technologies”, Applied Physics Letter, Vol. 48, pp.78-80, 1986 26. C.-H. Ge, C.-C. Lin, C.-H. Ko, C.-C. Huang, Y.-C. Huang, B.-W. Chan, B.-C. Perng, C.-C. Sheu, P.-Y. Tsai, L.-G. Yao, C.-L. Wu, T.-L. Lee, C.-J. Chen, C.-T. Wang, S.-C. Lin, Y.-C. Yeo, C. Hu, “Process strained-Si (PSS) CMOS technology featuring 3D strain engineering”, IEDM, pp. 3.7.1-3.7.4, 2003 115 27. H. Irie, K. Kita, K. Kyuno, A. Toriumi, “In-plane mobility anisotropy and universality under uni-axial strains in n- and p-MOS inversion layers on (100), (110) and (111) Si”, IEDM, pp.225-228, 2004 28. D. K. Nayak and S. K. Chun, “Low field hole mobility of strained Si on (100) Si1xGex substrate”, Applied Physics Letter, Vol. 64, pp.2514-2516, 1994 29. Inaba, S.; Miyano, K.; Hokazono, A.; Ohuchi, K.; Mizushima, I.; Oyamatsu, H.; Tsunashima, Y.; Toyoshima, Y.; Ishiuchi, H.; “Silicon on Depletion Layer FET (SODEL FET) for sub-50 nm high performance CMOS applications: novel channel and S/D profile engineering schemes by selective Si epitaxial growth technology” IEDM., pp. 659-662, 2002 30. M. Miyamoto, R. Nagai, and T. Nagano, “Pseudo-SOI: P-N-P-channel-doped bulk MOSFET for low-voltage high-performance applications,” International Electron Device Meeting Technical Digest, pp. 411-414, 1998 31. K. J. Chui, G. Samudra, Y.-C. Yeo, K.-C. Tee, F. Benistant, K.-W. Leong, K. M. Tee, and L. Chan, "Source/drain on depletion layer (SDODEL) MOSFET for performance enhancement," IEEE Electron Device Letters, vol. 26, no. 3, pp. 205207, Mar. 2005 32. Synopsys, “TSUPREMIV ver202.4 manual” 33. Synopsys, “MEDICI ver2002.4 manual” 34. R. F. Lever, J. M. Bonar, A. F. W. Willoughby, “Boron Diffusion across Si – SiGe Boundaries”, Journal of Applied Physics, Vol.83 (4), pp. 1988-1994, 1998 35. S. Eguchi, J. L. Hoyt, C. W. Leitz, E. A. Fitzgerald., “Comparison of As and P Diffusion in SiGe Alloys”, Applied Physics Letter, Vol. 80 (10), pp.1743-1745, 2002 36. A. Toda, N. Ikarashi, H. Ono and K. Okonogi, " Determining the relationship between local lattice strain and slip systems of dislocations around shallow trench isolation by convergent-beam electron diffraction," Applied Physics Letters, vol. 80, no. 13, pp.2278-2280, Apr. 2002 116 37. A. Armigliato, R. Balboni and S. Frabboni, " Improving spatial resolution of convergent beam electron diffraction strain mapping in silicon microstructures," Applied Physics Letters, vol. 86, no. 6, 063508, Jan. 2005 38. Y.-C. Yeo and J. Sun, "Finite element study of strain distribution in transistor with silicon-germanium source and drain regions," Applied Physics Letters, vol. 86, no. 2, 023103, Jan. 2005 39. D. B. Williams and C. B. Carter, Transmission Electron Microscopy Spectrometry IV, New York, Plenum Press 40. G. E. Pikus and G. L. Bir, Symmetry and Strained-Induced Effects in Semiconductors, New York, J. Wiley, 1974 41. J. Welser, J. Hoyt, S. Takagi and J. F. Gibbons, ”Strained dependence of performance in strained-Si n-MOSFETs,” in IEDM Tech. Dig., pp. 373-376, 1994 42. K. Natori, “Ballistic metal-oxide-semiconductor field effect transistor,” J. Appl. Phys., vol. 76, no. 8, pp. 4879-4890, Oct. 1994. 43. M. Lundstrom and Z. Ren, “Essential physics of carrier transport in nanoscale MOSFETs,” IEEE Trans. Electron Devices, vol. 49, no. 1, pp. 133-141, Jan. 2002. 44. T. Mizuno, N. Sugiyama, T. Tezuka, Y. Moriyama, S. Nakaharai, T. Maeda and S. Takagi, “High velocity electron injection MOSFETs for ballistic transistors using SiGe/strained Si heterojunction source structures,” Symp VLSI Tech, pp. 202, 2004 45. K. Rim, J. Chu, H. Chen, K.A. Jenkins, T. Kanarsky, K. Lee, A. Mocuta, H. Zhu, R. Roy, J. Newsbury, J. Ott, K. Petrarca, P. Mooney, D. Lacey, S. Koester, K. Chap, D. Boyd, M. Leong, and H.-S. P. Wong, “Characteristics and device design of sub-100 nm strained Si N- and P-MOSFETs,” Symp VLSI Tech. pp. 98-99, 2002 46. K. A. Jenkins and K. Rim, “Measurement of the self-heating in strained-silicon MOSFETs,” IEEE Electron Device Letters, Vol. 23, no. 6. pp. 360-362, Jun. 2002. 117 47. J. L. Hoyt, H. M. Nayfeh, S. Eguchi, I. Aberg, G. Xia, T. Drake, E. A. Fitzgerald, and D. A. Antoniadis, “Strained-silicon MOSFET technology,” in IEDM Tech. Dig., pp. 23-26, 2002 48. S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C.-H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z. Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, S. Sivakumar, R. Shaheed, L. Shifen, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, “A 90-nm logic technology featuring strained-silicon,” IEEE Trans. Electron Devices, vol. 51, no. 11, pp. 1790-1797, Nov. 2004. 49. P. Ranade, H. Takeuchi, Wen-Chin Lee, V. Subramanian and Tsu-Jae King, “Application of silicon-germanium in the fabrication of ultra-shallow extension junctions for sub-100 nm PMOSFETs,” IEEE Trans. Electron Devices, vol. 49, no. 8, pp. 1436-1446, Aug. 2002. 50. K.-W. Ang, K.-J. Chui, V. Bliznetsov, A. Du, N. Balasubramanian, G. Samudra, M. F. Li and Y.-C. Yeo, “Performance Enhancement in 50nm N-MOSFETs with Silicon-Carbon Source/Drain Regions” IEDM Tech. Dig., pp. 1069 -1071, 2004 51. P. C. Kelires, “Short-range order, bulk moduli, and physical trends in c-Si1-xCx alloys,” Phys. Rev. B, vol. 55, no. 14, pp. 8784, Apr. 1997. 52. J. M. Hartmann, T. Ernst, V. Loup, F. Ducroquet, G. Rolland, D. Lafond, P. Holliger, F. Laugier, M. N. Semeria and S. Deleonibus, “ Reduced pressure chemical vapor deposition of Si/Si1-yCy heterostructures for n-type metal-oxidesemiconductor transistors,” Journal of Applied Physics, vol. 92, no. 5, pp. 2368 – 2373, Sep. 2002. 53. H. J. Osten, J. Griesche, P. Gaworzewski and K. D, Bolze, “Influence of interstitial carbon defects on electron transport in strained Si1-yCy layers on Si (001),” Applied Physics Letters, vol. 76, no. 2, pp. 200 – 202, Jan. 2000. 54. T. Ernst, F. Ducroquet, J. M. Hartmann, O. Weber, V. Loup, R. Truche, A. M. Papon, P. Holliger, B. Previtali, A. Toffoli, J. L. Di Maria and S. Deleonibus, “A 118 new Si:C epitaxial channel nMOSFET architecture with improved drivability and short channel characteristics,” Symp VLSI Tech. pp. 51-52, 2003 55. D. J. Lockwood, H. X. Xu and J.-M. Baribeau, “Lattice vibrations of Si1-xCx epi layers on Si (100),” Phys. Rev. B, vol. 68, 115308, Sep. 2003 56. K. Brunner, K. Eberl, and W. Winter, “Near-band-edge photoluminescence from pseudomorphic Si1-yCy/Si quantum well structures,” Phys. Rev Lett., vol. 76, no. 2, pp. 303, Jan. 1996. 57. H. Rucker, B. Heinemann, D. Bolze, D. Knoll, D. Kruger, R. Kurps, H. J. Osten, P. Schley, B. Tillack and P. Zaumseil, “Dopant diffusion in C-doped Si and SiGe: Physical model and experimental verification,” IEDM Tech. Dig., pp. 345 – 348, 1999 58. Y. Kanda, “A graphical representation of the piezoresistance coefficients in Si,” IEEE Trans. Elect. Dev. ED-29, pp. 64, 1982. 59. K.-W. Ang, K.-J. Chui, V. Bliznetsov, Y. Wang, L.-Y. Wong, C.-H. Tung, N. Balasubramanian, M. F. Li, G. Samudra, and Y.-C. Yeo, "Thin body silicon-oninsulator n-MOSFET with silicon-carbon source/drain regions for performance enhancement," IEEE International Electron Device Meeting 2005, Washington, D.C., Dec. 5-7, pp. 503-506, 2005 60. P. Verheyen, N. Collaert, R. Rooyackers, R. Loo, D. Shamryan. A. De Keersgieter, G. Eneman, F. Lys, A. Dixit, M. Goodwin, Y. S. Yim, M. Cayax, K. De Meyer, P. Absil, M. Jurczak, S. Biesemans, “25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si0.8Ge0.2 in the source and drain regions”, Symp. VLSI Tech, pp. 194, 2005 61. D. Zhang, B. Y. Nguyen, T. White, B. Goolsby, T. Nguyen, V. Dhandapani, J. Hildreth, M. Foisy, V. Adams, Y. Shibo, A. Thean, D. Theodore, M. Canonico, S. Zollner, S. Baichi, S. Murphy, R. Rai, J. Jiang, M. Jahanbani, R. Nibble, M. Zavala, R. Cotton, D. Eades, S. Parsons, P. Montogomery, A. Martinez, B. Winstead, M. Medicino, J. Cheek, J. Liu, P. Grudoswki, N. Ramami, P. Tomasinini, C. Arena, C. Werkhoven, H. Kirby, C. H. Chang, C. T. Liu, H. C. Tuan, Y. C. See, S. Vankatesan, V. Kolagunta, N. Cave and J. Mogab, “Embedded 119 SiGe S/D PMOS on thin body SOI substrate with drive current enhancement,” Symp VLSI Tech. pp. 26-29, 2005. 62. T. Tezuka, N. Sugiyama, T. Mizuno, S. Takagi, “High-performance strained Si-oninsulator MOSFETs by novel fabrication processes utilizing Ge-condensation technique”, Symp. VLSI Tech, pp. 96, 2002 63. K.-J. Chui, K.-W. Ang, A. Madan, Y. Wang, L.-Y. Wong, S.-F. Choy, C.-H. Tung, N. Balasubramanian, M. F. Li, G. S. Samudra, and Y.-C. Yeo, “Source/drain Ge condensation for p-channel strained ultra-thin body transistors,” IEDM Tech. Dig., pp. 499-502, 2005. 120 LIST OF CONFERENCE / PUBLICATIONS From Thesis Work : 1. K.-J. Chui, G. Samudra, Y.-C. Yeo, K.-C. Tee, F. Benistant, K.-W. Leong, K. M. Tee, and L. Chan, "Source/drain on depletion layer (SDODEL) MOSFET for performance enhancement," IEEE Electron Device Letters, vol. 26, no. 3, pp. 205207, Mar. 2005. 2. K. W. Ang, K.-J. Chui, V. Bliznetsov, A. Du, N. Balasubramanian, M. F. Li, G. Samudra, and Y.-C. Yeo, "Enhanced performance in 50 nm N-MOSFETs with silicon-carbon source/drain regions," IEEE International Electron Device Meeting Technical Digest, San Francisco, CA, pp. 1069-1071, Dec. 13-15, 2004. 3. K.-W. Ang, K.-J. Chui, V. Bliznetsov, C.-H. Tung, A. Du, N. Balasubramanian, G. Samudra, M. F. Li, and Y.-C. Yeo, "Lattice strain analysis of transistor structures with silicon-germanium and silicon-carbon source/drain stressors," Applied Physics Letters, vol. 86, 093102, Feb. 2005 4. K.-J. Chui, K.-W. Ang, A. Madan, G. H. Wang, C.-H. Tung, L.-Y. Wong, Y. Wang, S.-F. Choy, N. Balasubramanian, M. F. Li, G. Samudra, and Y.-C. Yeo, "Source/drain germanium condensation for p-channel strained ultra-thin body transistors," IEEE International Electron Device Meeting 2005, Washington, D.C., pp. 499-502, Dec. 5-7, 2005. 5. K.-W. Ang, K.-J. Chui, V. Bliznetsov, Y. Wang, L.-Y. Wong, C.-H. Tung, N. Balasubramanian, M. F. Li, G. Samudra, and Y.-C. Yeo, "Thin body silicon-oninsulator n-MOSFET with silicon-carbon source/drain regions for performance enhancement," IEEE International Electron Device Meeting 2005, Washington, D.C., pp. 503-506, Dec. 5-7, 2005. 6. K.-W. Ang, K.-J. Chui, H.-C. Chin, Y.-L. Foo, A. Du, W. Deng, Ming-Fu Li, G. Samudra, N. Balasubramanian, and Y.-C. Yeo, "50 nm silicon-on-insulator NMOSFET featuring multiple stressors: silicon-carbon source/drain regions and tensile stress silicon nitride liner," Symposium on VLSI Technology, Honolulu, Jun. 13-15, 2006. 121 7. K.-J. Chui, K.-W. Ang, A. Madan, A. Du, C.-H. Tung, N. Balasubramanian, G. Samudra, and Y.-C. Yeo, "Ultra-thin-body P-MOSFET featuring silicongermanium source/drain stressors with high germanium content formed by local condensation," 36th European Solid-State Device Research Conference (ESSDERC), Montreux, Switzerland, Sep. 18-22, 2006 8. K.-W. Ang, H.-C. Chin, K.-J. Chui, M.-F. Li, G. Samudra, and Y.-C. Yeo, "Carrier backscattering characteristics of strained N-MOSFET featuring siliconcarbon source/drain regions," 36th European Solid-State Device Research Conference (ESSDERC), Montreux, Switzerland, Sep. 18-22, 2006. 9. K.-J. Chui, K.-W. Ang, H.-C. Chin, C. Shen, L.-Y. Wong, C.-H. Tung, N. Balasubramanian, M. F. Li, G. S. Samudra, and Y.-C. Yeo, "Strained silicon-oninsulator n-channel transistor with silicon-carbon source/drain regions for carrier transport enhancement," to appear in IEEE Electron Device Letters, vol. 27, 2006 10. K.-J. Chui, K.-W. Ang, N. Balasubramanian, M. F. Li, G. Samudra, and Y.-C. Yeo, "N-MOSFETs with silicon-carbon source/drain for enhancement of carrier transport," Submitted to IEEE Trans. Electron Device. 11. K.-J. Chui, K.-W. Ang, A. Madan, N. Balasubramanian, A. Du, C.-H. Tung, M. F. Li, G. Samudra, and Y.-C. Yeo, “Strained Ultra-Thin-Body P-Channel Transistors Featuring Locally Condensed High Germanium Content SiGe Source/Drain Regions”, Submitted to IEEE Trans. Electron Device. 12. K.-W. Ang, K.-J. Chui, A. Madan, L.-Y. Wong, N. Balasubramanian, C.-H. Tung, M. F. Li, G. Samudra, and Y.-C. Yeo, “Strained Thin-Body P-MOSFET with Condensed Silicon-Germanium Source/Drain for Enhanced Drive Current Performance”, Submitted to IEEE Electron Device Letter. From Collaborative Work : 13. W. H. T. Phua, D. S. Ang, C. H. Ling, K.-J. Chui, “STI-induced damage and hotcarrier reliability in the narrow width short channel NMOSFET fabricated using global strained-Si technology”, Solid-State Device Research Conference, ESSDERC 2005, Sept 12-16, 2005, pp. 533 – 536 122 14. R. T. P. Lee, T.-Y. Liow, K.-M. Tan, K.-W. Ang, K.-J. Chui, G.-Q. Lo, D.-Z. Chi, and Y.-C. Yeo, "Process-Induced Strained P-MOSFET Featuring Nickel-Platinum Silicided Source/Drain," to be presented at Materials Research Society Spring 2006 Meeting. 15. K.-M. Tan, T.-Y. Liow, R. T.-P. Lee, K.-J. Chui, C.-H. Tung, N. Balasubramanian, G. S. Samudra, W.-J. Yoo, and Y.-C. Yeo, "Sub-30 nm strained p-channel FinFETs with condensed SiGe source/drain stressors," 2006 International Conference on Solid State Devices and Materials, Yokohama, Japan, Sep. 13-15, 2006. LIST OF PATENTS 1. Y. Li, F. Benistant, K.M. Tee, K.-J. Chui, “Low cost source drain elevation through poly amorphizing implant technology”, filed in US Patent Office – Application No. 20050148125. 2. K.-J. Chui, F. Benistant, G. Samudra, K.M. Tee, Y. Li, K.W.Leong, K.C. Tee, “Structure and method to form source drain regions over doped depletion regions”, filed in US Patent Office – Application No. 20050156253. 3. K.-J. Chui, G. Samudra, Y.-C. Yeo, J. Liu, K.C. Tee, W.H. Phua, L. Wong, “Method of manufacturing a semiconductor device with a strained channel”, filed in US Patent Office – Application No. 20060030094. 4. K. K. Ong, K.-J. Chui, K. L. Pey, G. Samudra, Y.-C. Yeo, “Formation of strained si channel and Si1-xGex S/D structures using laser annealing”, filed in US Patent Office – Reference No. 11/195,196. 123 [...]... substrates will be explored for reduction in parasitic capacitance C In 11 addition, focus will also be given to the various methods of inducing strain in the channel of MOSFET devices for enhanced device performance 1.4 Outline of the report Chapter 1 includes a brief discussion of the recent technology to improve the performance of the MOSFET devices For eventual improvement in device performance at the circuitry... with the hope of improving CMOS devices performance Some of these include the use and implementation of metal gates [2] – [6], high-k gate dielectrics [7], [8], channel strain engineering [9] – [17], silicon-on-insulator (SOI) substrates [18] - [20], shallow junction formation [21] and/or a combination of some of these features [22] for continual improvements in CMOS device performance As the gate length... circuit speed performance In this thesis, various ways to improve the circuitry speed, by means of either reduction in parasitic capacitance C and/or increase in drive current I, will be explored as the power supply voltage is mainly dictated by power consumption and roadmap requirements 2 1.2 Background 1.2.1 Present TechnologyTrend : Novel Devices and Architecture for Enhanced CMOS Performance As explained... Motivation Device scaling is essential for the continued improvement in CMOS technology Gordon Moore predicted that the speed performance of integrated circuits would double every 18-24 months Until now, this is achieved mainly by the down sizing of conventional silicon (Si) CMOS devices However, with the progression of each technology node, sustaining the performance improvement to meet the ITRS roadmap... to meet the ITRS roadmap [1] through scaling alone becomes increasingly difficult to maintain Therefore, new materials and novel device structures are essential in order to keep up with the expected level of performance improvement as required by the roadmap In order to propose alternatives for device performance enhancement, it is essential to look at the equation that governs circuitry speed The time... other hand, parasitic capacitance C can be reduced significantly by the implementation of MOSFET devices on SOI substrates 1.3 Objectives of the research The main objective of this thesis is to explore various ways to enhance the performance of CMOS device, and ultimately resulting in an improvement in speed performance of integrated circuits This can be achieved by reducing the parasitic capacitance C... equation (1.1), the key to enhancing circuit performance lies in the manipulation of the 3 parameters (C, Vdd and I) In a bid for continual performance enhancement and meeting the requirements of the Moore’s Law, which until now is heavily reliant on device scaling, there is an ever increasing need to introduce new structures and materials into the present CMOS technology At present, many types of device... capacitance C In chapter 2, a low cost alternative to SOI substrates for reduction in parasitic capacitance is explored Electrical characterization of fabricated devices is performed at the transistor as well as the circuit level TCAD simulation is also being done concurrently for optimization of the devices and projection of its feasibility for future technology nodes Chapters 3, 4, 5 and 6 discuss the... control UTB pMOSFETs Strained UTB pMOSFET devices with condensed Si0.54Ge0.46 S/D shows improved short channel characteristics over control devices ………………………………………………………………… 107 Figure 6.21 : (a) Si0.54Ge0.46 S/D pMOSFET shows improved subthreshold swing over control devices for all gate lengths Excellent subthreshold swing of less than 70 mV/decade is obtained for the Si0.54Ge0.46 S/D pMOSFET (b) DIBL... Es …… 92 Figure 6.7 : Drive current IDsat as a function of LG, before (solid symbols) and after correction (open sybols) for series resistance Rs In both cases, IDsat enhancement increases with decreasing LG Improvement in Rs accounts for 13% in IDsat enhancement …93 xv Figure 6.8 : Ioff-Ion characteristics comparing the drive current performance of control and strained p-MOSFET with condensed SiGe S/D . NOVEL DEVICES FOR ENHANCED CMOS PERFORMANCE CHUI KING JIEN NATIONAL UNIVERSITY OF SINGAPORE 2006 NOVEL DEVICES FOR. Trend : Novel Devices and Architecture for Enhanced Performance CMOS Performance …………… 3 1.2.2 Channel Strain Engineering …………………………………………………. 5 1.2.3 Silicon-On-Insulator (SOI) for reduced. UNIVERSITY OF SINGAPORE 2006 Novel Devices for Enhanced CMOS Performance ABSTRACT Complementary Metal Oxide Semiconductor (CMOS) transistors form the basis of many integrated circuit