Simulation, modelling and fabrication of novel devices with steep subthreshold slope

SIMULATION AND FABRICATION OF NOVEL DEVICES WITH STEEP SUBTHRESHOLD SLOPE TOH ENG HUAT (B.Eng (Hons.), NUS) A THESIS SUBMITTED FOR THE DEGREE OF Ph.D (ENGINEERING) DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2008 ABSTRACT CMOS device scaling faces several fundamental limits as it scaled beyond the sub-30 nm regime. Non-scalability of the subthreshsold swing and adverse short channel effects like drain-induced barrier lowering, and band-to-band tunneling have led to high off-state leakage current. Thus, the impact-ionization MOS (I-MOS) transistor and tunneling fieldeffect transistor (TFET) have been explored as an alternative switching device for sub-60 mV/decade subthreshold swing. Both are essentially gated p-i-n diode. The former employs an impact-ionization region (I-region) for avalanche of carriers to occur, while the latter creates a region near the source-channel junction for band-to-band tunneling of carriers to occur. This work is devoted to addressing the issue of the non-scalability of the subthreshold swing, and evaluating and advancing the I-MOS and TFET technologies. For the I-MOS technology, process and device design innovations like the doublespacer I-MOS were applied to achieve excellent device performance with good short channel effects. The employment of SiGe in SiGe complementary I-MOS (C-I-MOS) further reduces the power supply voltage requirement, while boosting the device performance in terms of off-state and on-state current. For compactness and better scalability, an I-MOS transistor with an elevated I-region or the L-shaped I-MOS transistor had been proposed as a promising candidate among various I-MOS structures for enhanced performance through strain and materials engineering. The elevated Iregion allows for the incorporation of novel materials for introduction of strain and i reduction in the bandgap to increase impact-ionization activity. Both I-MOS with an elevated Si1-yCy RSD and I-MOS with an elevated Si1-xGex RSD had been realized and proved to be viable not only in reducing the breakdown voltage, but also to enhance the performance further. An impact-ionization nanowire multiple-gate field-effect transistor (I-FinFET) was also proposed and fabricated, leading to a significant reduction in the source bias needed to sustain impact-ionization. In situ doping, strain and material engineering technology were employed for enhanced device performance. In addition, a simulation study on the Ge LI-MOS technology revealed promising potential. The TFET technology had been studied by extensive device simulation. A doublegate Si TFET with SiGe source was proposed and explored. Less than 60 mV/decade subthreshold swing with extremely low off-state leakage current is achieved by optimizing the device parameters and Ge content in the source. Power supply voltage scaling is projected to be possible with the introduction of much narrower bandgap material like Ge or InAs. Thus, low supply voltage coupled with bandgap engineering helps to pave the way for transistor downscaling while maintaining low power consumption. In summary, novel devices with steep subthreshold slope were proposed and studied. They reveal promising potential for augmenting the performance of conventional CMOS transistors. ii ACKNOWNLEDGEMENTS I would like to express my sincere gratitude to my advisor, Dr Yeo Yee-Chia for his generous help throughout my four years of post graduate study at National University of Singapore (NUS). Dr Yeo Yee-Chia is an admirable academic professional and a great role model. He taught me not only his precious knowledge, but also his exceptional professionalism. I typically enjoyed those inspiring discussions we had. I especially thank him for his prompt reading and careful critique of my thesis. Throughout my life, I will benefit from the experience and knowledge I gained working with Dr Yeo Yee-Chia. I am also indebted to my co-advisor, Prof Ganesh Samudra for his valuable guidance and insightful suggestions to my research work. Since my undergraduate study, he had been providing me with lots of guidance in research for the past five years. He impressed me very much by his responsibility and strict attitude in training students to be independent. He always provided timely and warm encouragement and support in difficult times. As a respected elder, he introduced me to the various opportunities in research. I am also grateful to my mentor, Dr Lap Chan from Chartered Semiconductor Manufacturing Ltd. (CHRT) who had been very supportive of my work. His willingness to share both his work and life experience really widened my perspectives. I would also like to thank Dr Francis Benistant (CHRT) for his guidance in carrying out TCAD simulation. A lot of precious knowledge was learned from him. iii Special thanks to Dr. Patrick Lo for facilitating my fabrication work at the Institute of Microelectronics (IME). I also thank the research staffs and engineer assistants at IME for their support. I would also like to take this opportunity to thank my working partner, Miss Grace Wang Huiqi, who introduced me to semiconductor processing equipments and shared her expertise in materials analysis; my colleagues at the Silicon Nano Device Laboratory (SNDL), Dr. Zhu Ming, Mr Shen Chen, Mr Ang Kah Wee, Mr Chui King Jien, Mr Tan Kian Meng, Mr Jason Liow, Mr Rinus Lee, and Mr Andy Lim for their help and discussions; and the Special Project Group students (CHRT) for providing a wonderful research atmosphere to work in. Finally, I owe more than words can describe to my family and friends. This work is dedicated to them. iv TABLE OF CONTENTS ABSTRACT ACKNOWNLEDGEMENTS i iii TABLE OF CONTENTS v LISTS OF FIGURES x LISTS OF TABLES xxvii LISTS OF SYMBOLS AND ABBREVIATIONS xxviii CHAPTER INTRODUCTION 1.1 Motivation 1.2 Background 1.3 Objectives of Research 1.4 Outline of Thesis CHAPTER DEVICE PHYSICS FOR I-MOS and TFET 12 2.1 Introduction 12 2.2 Physics of Impact-ionization 12 2.3 Avalanche Multiplication 17 2.4 Band-to-band Tunneling 20 2.5 Summary 24 CHAPTER THE IMPACT-IONIZATION MOS (I-MOS) TRANSISTOR 25 3.1 Introduction 25 3.2 Device Operation and Physics 26 v 3.3 3.4 3.5 The Double-Spacer (DS) I-MOS Transistor 28 3.3.1 Background 28 3.3.2 New Device Structure with Double Spacer 29 3.3.3 Device Fabrication 30 3.3.4 Device Characterization and Analysis 33 3.3.5 Summary for DS I-MOS Transistor 37 The Lateral SiGe I-MOS Transistor 38 3.4.1 Background 38 3.4.2 SiGe-on-Insulator (SGOI) Substrate Formation 39 3.4.3 Device Structure and Fabrication 42 3.4.4 Impact of Impact-ionization Threshold Energy Engineering 44 3.4.5 Device Performance of SiGe I-MOS Transistor 47 3.4.6 Summary of SiGe I-MOS Transistor 48 Summary 51 CHAPTER THE L-SHAPED IMPACT-IONIZATION MOS (LI-MOS) TRANSISTOR 53 4.1 Introduction 53 4.2 I-MOS Device Structures 54 4.3 LI-MOS Device Structure and Design 55 4.4 CMOS-Compatible Process Flow of LI-MOS 59 4.5 Strain Engineering of LI-MOS 61 4.6 Material Engineering of LI-MOS 68 4.7 Summary 72 CHAPTER THE IMPACT-IONIZATION NANOWIRE TRANSISTOR 74 5.1 Introduction 74 5.2 New Device Structure: From LI-MOS to I-FinFET 75 5.3 Process Flow of I-FinFET 76 vi 5.4 5.5 5.6 5.7 The Silicon I-FinFET Technology 77 5.4.1 Background 77 5.4.2 Breakdown Characteristics 81 5.4.3 Gate Transfer Characteristics 83 In situ Doping and Strain Engineering Technology 85 5.5.1 Background 85 5.5.2 Device Physics and Structures 86 5.5.3 Process Flow of I-FinFETs with In Situ Doping and Strain Technology 87 5.5.4 Device Performance of I-FinFETs with in situ doping and strain 89 5.5.5 Summary of I-FinFETs with in situ doped Source 93 Impact-ionization Threshold Energy Engineering Technology 93 5.6.1 Background 93 5.6.2 Material, Device Structure, and Physics 94 5.6.2 Device Fabrication 95 5.6.3 Device Performance of SiGe I-FinFET 97 5.6.4 Summary of SiGe I-FinFET Summary CHAPTER THE Ge LI-MOS TECHNOLOGY: AN OUTLOOK 100 102 104 6.1 Introduction 104 6.2 Device Structure and Physics 104 6.3 Material Engineering 106 6.4 Device Design and Optimization 108 6.5 Device Scalability 113 6.6 Summary 116 CHAPTER THE SILICON TUNNELING FIELD-EFFECT TRANSISTOR (TFET) 117 7.1 Introduction 117 7.2 Device Operation, Physics and Modeling 117 7.3 The Double-Gate (DG) TFET Device 120 vii 7.3 7.5 The DG TFET with SiGe Source 125 7.3.1 Background 125 7.3.2 Device Structure and Design 125 7.3.3 Device Characteristics and Performance 131 7.3.4 Summary of DG TFET with SiGe Source 139 Summary CHAPTER THE GERMANIUM OR NARROW BANDGAP MATERIAL TFET 139 141 8.1 Introduction 141 8.2 The Ge TFET 142 8.2.1 Background 142 8.2.2 Device Structure and Physics 142 8.2.3 Performance of Ge TFET 144 8.2.4 Drain Engineering 147 8.2.5 Source Engineering 151 8.2.6 Gate Stack Engineering 155 8.2.7 Power Supply Voltage Scaling 158 8.2.8 Summary of Ge TFET 160 8.3 Material Engineering for TFET 161 8.4 Summary 163 CHAPTER CONCLUSION 164 9.1 Overview 164 9.2 Performance Enhancement with DS I-MOS and SiGe Channel 164 9.3 A Novel LI-MOS Structure with Strain and Material Engineering 165 9.4 I-FinFET with In Situ Doping, Strain, and Material Engineering 165 9.5 The Ge LI-MOS Technology 166 9.6 The Double-Gate TFET with SiGe Source 166 9.7 The Ge or Narrower Bandgap Material TFET 167 9.8 Summary 167 viii CHAPTER 10 RECOMMENDATIONS FOR FUTURE WORK 168 10.1 Overview 168 10.2 Future Work for I-MOS Transistor 168 10.3 Future Work for TFET 169 10.4 Summary 169 REFERENCES 170 CURRICULUM VITAE 178 LIST OF PUBLICATIONS 180 ix References 172 [26] K. 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Yeo, "Device physics and guiding principles for the design of double-gate tunneling field effect transistor with silicongermanium source heterojunction," Applied Physics Letters, vol. 91, no. 24, 243505, Dec. 2007. [75] E.-H. Toh, G. H. Wang, L. Chan, D. Sylvester, C.-H. Heng, G. Samudra, and Y.-C. Yeo, "A double-gate tunneling field-effect transistor with silicon-germanium source for highperformance, low standby power, and low power technology applications," Extended Abstracts of the 2007 International Conference on Solid State Devices and Materials, Ibaraki, Japan, Sep. 18-21, 2007, pp. 894-895. [76] E.-H. Toh, G. H. Wang, L. Chan, D. Sylvester, C.-H. Heng, G. Samudra, and Y.-C. Yeo, "Device design and scalability of a double-gate tunneling field-effect transistor with silicongermanium source," Japanese Journal of Applied Physics, vol. 47, no. 4, pp. 2593-2597, Apr. 2008. [77] E.-H. Toh, G. H. Wang, G. Samudra, and Y.-C. Yeo, "Device physics and design of germanium tunneling field effect transistor with source and drain engineering for low power and high performance applications," J. Applied Physics, vol. 102, 104504, May 2008 [78] G. Samudra, Y.-C. Yeo, C.-H. Heng, E.-H. Toh, and L. Yang, "Simulation of material and strain engineering of tunneling field-effect transistor with subthreshold swing below 60 mV/decade," 2008 International Conference on Solid-State Devices and Materials, Ibaraki, Japan, Sep. 23 - 26, 2008. CURRICULUM VITAE Personal Name Eng-Huat Toh Date of Birth January, 19, 1979 Nationality Singaporean Affiliations * Silicon Nano Device Laboratory (SNDL) Department of Electrical and Computer Engineering National University of Singapore (NUS), 10 Kent Ridge Crescent, S119260, Singapore. † Chartered Semiconductor Manufacturing Ltd. 60 Woodlands Industrial Park D, Street 2, Singapore 738406 Professional Experience Senior Engineer, TD, Chartered Semiconductor Mfg. Ltd. Research Engineer 2008 – present Device Group Project: Research and Development of Advance Technologies Researcher, Device Group, National University of Singapore Ph.D. Candidate 2004 – 2008 Dr. Yee-Chia Yeo’s Group Research Topic: Simulation and Fabrication of Novel Devices Researcher, Special Projects Group, Chartered Semiconductor Mfg. Ltd. Ph.D. Scholar 2004 – 2008 Dr. Lap Chan’s Group Research Topic: Simulation and Fabrication of Novel Devices Teaching Assistant, National University of Singapore Teaching/Lab Assistant 2005 – 2007 Curriculum Vitae 179 Modules: CMOS Front-End Processes and Integration CMOS Digital Circuit Design Integrated Analog Design 2004 – 2005 Intern, TD, Chartered Semiconductor Mfg. Ltd. Ph.D. Intern TCAD Group Project: TCAD Development for 90 nm SOI Technology Undergraduate, Final Year Project, National University of Singapore Final Year B.Eng Student 2003 – 2004 Prof. Ganesh Samudra’s Group Research Topic: Simulation and Analysis of Double-Gate SOI MOSFETs Intern, Product Engineering (PE), Micron Semiconductor Asia Pte. Ltd. Industrial Attachment 2003 0.13 µm DRAM PE Group Project: Testing and Software Development for DRAM Education National University of Singapore (NUS), Singapore Ph.D. Electrical and Computer Engineering, Candidate CAP Score: 5/5 Expected Date of Graduation: Aug 2008 Research Advisors: Asst. Prof. Yee-Chia Yeo, and Assoc. Prof. Ganesh Samudra Dissertation: Simulation, Modeling and Fabrication of Novel Devices with Subthreshold Swing Smaller than kT/q National University of Singapore (NUS), Singapore B.Eng. Electrical and Computer Engineering, 2004 First Class Honors Final Year Thesis: Simulation and Analysis of Double-Gate SOI MOSFETs Anderson Junior College (AJC), Singapore GCE A-Level. Science and Mathematics, 1997 A’s (Physics, Chemistry, and Mathematics C), B’s (Further Mathematics), and Special (S) paper distinctions (Physics, and Mathematics C) LIST OF PUBLICATIONS Journals Publications Regular Papers [1] G. H. Wang, E.-H. Toh, C.-H. Tung, A. Du, G.-Q. Lo, G. Samudra, and Y.-C. Yeo, "Strained silicon-germanium-on-insulator n-channel transistor with silicon source and drain regions for performance enhancement," Japanese Journal of Applied Physics, vol. 46, no. 4B, pp. 2062-2066, Apr. 2007. [2] E.-H. Toh, G. H. Wang, L. Chan, G.-Q. Lo, G. Samudra, and Y.-C. Yeo, "Strain and materials engineering of the I-MOS transistor with an elevated impact-ionization region," IEEE Trans. Electron Devices, vol. 54, no. 10, pp. 2778-2785, Oct. 2007. [3] E.-H. Toh, G. H. Wang, L. Chan, G. Samudra, and Y.-C. Yeo, "Simulation and design of germanium L-shaped impact-ionization MOS transistor," Semiconductor Science and Technology, vol. 23, no. 1, 015012, Jan. 2008. [4] G. H. Wang, E.-H. Toh, C.-H. Tung, S. Tripathy, G. Samudra, and Y.-C. Yeo, "Concept of strain-transfer-layer (STL) and integration with silicon-germanium source/drain stressors for p-MOSFET performance enhancement," Japanese Journal of Applied Physics, vol. 47, no. 4, pp. 2551-2555, Apr. 2008. [5] E.-H. Toh, G. H. Wang, L. Chan, D. Sylvester, C.-H. Heng, G. Samudra, and Y.-C. Yeo, "Device design and scalability of a double-gate tunneling field-effect transistor with silicongermanium source," Japanese Journal of Applied Physics, vol. 47, no. 4, pp. 2593-2597, Apr. 2008. [6] G. H. Wang, E.-H. Toh, X. Wang, K.-M. Hoe, S. Tripathy, G. Samudra, and Y.-C. Yeo, "Strain relaxed high quality Silicon-Germanium-on-Insulator (Si0.17Ge0.83OI) substrates formed by pulsed laser irradiation technology," Japanese Journal of Applied Physics, vol. 47, no. 4, pp. 3015-3019, Apr. 2008. List of Publications [7] 181 E.-H. Toh, G. H. Wang, L. Chan, G. Samudra, and Y.-C. Yeo, "Device physics and performance optimization of impact-ionization MOS transistors formed using a doublespacer fabrication process," Japanese Journal of Applied Physics, vol. 47, no. 4, pp. 30773080, Apr. 2008. [8] E.-H. Toh, G. H. Wang, G. Samudra, and Y.-C. Yeo, "Device physics and design of germanium tunneling field effect transistor with source and drain engineering for low power and high performance applications," J. Applied Physics, vol. 103, no. 10, 104504, 2008. Letters and Briefs [9] G. H. Wang, E.-H. Toh, Y.-L. Lim, C.-H. Tung, S.-F. Choy, G. S. Samudra, and Y.-C. Yeo, "High quality silicon-germanium-on-insulator wafers fabricated using cyclical thermal oxidation and annealing," Applied Physics Letters, vol. 89, 053109, Aug. 2006. [10] E.-H. Toh, G. H. Wang, L. Chan, G.-Q. Lo, G. S. Samudra, and Y.-C. Yeo, "I-MOS transistor with an elevated silicon-germanium impact-ionization region for bandgap engineering," IEEE Electron Device Letters, vol. 27, no. 12, pp. 975-977, Dec. 2006. [11] E.-H. Toh, G. H. Wang, G.-Q. Lo, L. Chan, G. Samudra, and Y.-C. Yeo, "Performance enhancement of n-channel impact-ionization MOS (I-MOS) transistor by strain engineering," Applied Physics Letters, vol. 90, no. 2, 023505, Jan. 2007. [12] E.-H. Toh, G. H. Wang, G. Samudra, and Y.-C. Yeo, "Device physics and design of doublegate tunneling field-effect-transistor by silicon film thickness optimization," Applied Physics Letters, vol. 90, no. 24, Jun. 2007. [13] E.-H. Toh, G. H. Wang, L. Chan, G. Samudra, and Y.-C. Yeo, "Reduction of impactionization threshold energies for performance enhancement of complementary impactionization metal-oxide-semiconductor (C-I-MOS) transistors," Applied Physics Letters, vol. 91, no. 15, 153501, 2007. [14] G. H. Wang, E.-H. Toh, X. Wang, S. Tripathy, T. Osipowicz, T. K. Chan, K.-M. Hoe, S. Balakumar, G.-Q. Lo, G. Samudra, and Y.-C. Yeo, "Strained SiGeSn formed by Sn implant into SiGe and pulsed laser annealing," Applied Physics Letters, vol. 91, no. 20, 202105, 2007. List of Publications 182 [15] E.-H. Toh, G. H. Wang, L. Chan, G. Samudra, and Y.-C. Yeo, "Device physics and guiding principles for the design of double-gate tunneling field effect transistor with silicongermanium source heterojunction," Applied Physics Letters, vol. 91, no. 24, 243505, Dec. 2007. [16] G. H. Wang, E.-H. Toh, A. Du, G.-Q. Lo, G. Samudra, and Y.-C. Yeo, "Strained silicongermanium-on-insulator N-MOSFET with embedded silicon source and drain stressors," IEEE Electron Device Letters, vol. 29, no. 1, pp. 77-79, Jan. 2008. [17] E.-H. Toh, G. H. Wang, L. Chan, G. Samudra, and Y.-C. Yeo, "A double-spacer I-MOS transistor with shallow source junction and lightly-doped drain for reduced breakdown voltage and enhanced device performance," IEEE Electron Device Letters, vol. 29, no. 2, pp. 189-191, Feb. 2008. [18] J. Lin, E.-H. Toh, C. Shen, D. Sylvester, C.-H. Heng, G. Samudra, and Y.-C. Yeo, "Compact HSPICE model for IMOS device," IEEE Electronics Letters, vol. 44, no. 2, pp. 91-92, 2008. [19] E.-H. Toh, G. H. Wang, L. Chan, D. Weeks, M. Bauer, J. Spear, S. G. Thomas, G. Samudra, and Y.-C. Yeo, "Co-integration of in situ doped silicon-carbon source and silicon-carbon Iregion in p-channel silicon nanowire impact-ioniztion transistor," IEEE Electron Device Letters, vol. 29, 2008. Conference Publications [1] E.-H. Toh, G. H. Wang, G.-Q. Lo, N. Balasubramanian, C.-H. Tung, F. Benistant, L. Chan, G. Samudra, and Y.-C. Yeo, "A novel CMOS-compatible L-shaped Impact Ionization MOS (LI-MOS) transistor," IEEE International Electron Device Meeting 2005, Washington, D.C., Dec. 5-7, 2005, pp. 971-974. [2] G. H. Wang, E.-H. Toh, K.-W. Ang, C.-H. Tung, A. Du, Y.-L. Foo, G.-Q. Lo, G. Samudra, and Y.-C. Yeo, "Strained SiGe-On-Insulator N-MOSFET with Silicon Source/Drain for Drive Current Enhancement," Extended Abstracts of the 2006 International Conference on Solid State Devices and Materials, Yokohama, Japan, Sep. 13-15, 2006, pp. 1048-1049. List of Publications [3] 183 G. H. Wang, E.-H. Toh, K. M. Hoe, S. Tripathy, S. Balakumar, G.-Q. Lo, G. Samudra, and Y.-C. Yeo, "Strained silicon-germanium-on-insulator n-MOSFETs featuring lattice mismatched source/drain stressor and high-stress silicon nitride liner," IEEE International Electron Device Meeting 2006, San Francisco CA, Dec. 11-13, 2006, pp. 469-472. [4] G. H. Wang, E.-H. Toh, C.-H. Tung, Y.-L. Foo, S. Tripathy, S. Balakumar, G.-Q. Lo, G. Samudra, and Y.-C. Yeo, "Fabrication of strain relaxed silicon-germanium-on-insulator (Si0.35Ge0.65OI) wafers using cyclical thermal oxidation and annealing," Materials Research Society Spring 2007 Meeting, San Francisco, CA, Apr. 9-13, 2007. [5] G. H. Wang, E.-H. Toh, K. M. Hoe, S. Tripathy, S. Balakumar, G.-Q. Lo, G. Samudra, and Y.-C. Yeo, "Sub-50 nm strained n-FETs formed on silicon-germanium-on-insulator substrates and the integration of silicon source/drain stressors," Materials Research Society Spring 2007 Meeting, San Francisco, CA, Apr. 9-13, 2007. [6] E.-H. Toh, G. H. Wang, G.-Q. Lo, S.-F. Choy, L. Chan, G. Samudra, and Y.-C. Yeo, "A strained N-channel impact-ionization MOS (I-MOS) transistor with elevated silicon-carbon source/drain for performance enhancement," International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA), Hsinchu, Taiwan, Apr. 23-25, 2007, pp. 86-87. [7] E.-H. Toh, G. H. Wang, L. Chan, G.-Q. Lo, D. Sylvester, C.-H. Heng, G. S. Samudra, and Y.-C. Yeo, "A Complementary-I-MOS Technology Featuring SiGe Channel and I-region For Enhancement of Impact-ionization, Breakdown Voltage, and Performance," 37th European Solid-State Device Research Conference (ESSDERC), Munich, Germany, Sep. 11-13, 2007, pp. 295-298. [8] G. H. Wang, E.-H. Toh, Y.-L Foo, S. Tripathy, S. Balakumar, G.-Q. Lo, G. S. Samudra, and Y.-C. Yeo, "Uniaxial Strained Silicon n-FETs on Silicon-Germanium-on-Insulator Substrates with an e-Si0.7Ge0.3 Stress Transfer Layer and Source/Drain Stressors for performance enhancement," 37th European Solid-State Device Research Conference (ESSDERC), Munich, Germany, Sep. 11-13, 2007, pp. 311-314. [9] G. H. Wang, E.-H. Toh, C.-H. Tung, S. Tripathy, S. Balakumar, G.-Q. Lo, G. Samudra, and Y.-C. Yeo, "Silicon Strain-Transfer-Layer (STL) and graded source/drain stressors for enhancing the performance of silicon-germanium channel P-MOSFETs," Extended Abstracts of the 2007 International Conference on Solid State Devices and Materials, Ibaraki, Japan, Sep. 18-21, 2007, pp. 38-39. List of Publications 184 [10] E.-H. Toh, G. H. Wang, G.-Q. Lo, L. Chan, G. Samudra, and Y.-C. Yeo, "Double-spacer impact-ionization MOS transistor: Characterization and analysis," Extended Abstracts of the 2007 International Conference on Solid State Devices and Materials, Ibaraki, Japan, Sep. 18-21, 2007, pp. 208-209. [11] G. H. Wang, E.-H. Toh, X.-C. Wang, K.-M. Hoe, S. Tripathy, G.-Q. Lo, G. Samudra, and Y.-C. Yeo, "Pulsed laser irradiation of silicon-germanium-on-insulator (Si0.17Ge0.83OI) substrates for strain relaxation and defect reduction," Extended Abstracts of the 2007 International Conference on Solid State Devices and Materials, Ibaraki, Japan, Sep. 18-21, 2007, pp. 290-291. [12] C. Shen, E.-H. Toh, J. Lin, C.-H. Heng, D. Sylvester, G. Samudra, and Y.-C. Yeo, "A physics-based compact model for I-MOS transistors," Extended Abstracts of the 2007 International Conference on Solid State Devices and Materials, Ibaraki, Japan, Sep. 18-21, 2007, pp. 608-609. [13] E.-H. Toh, G. H. Wang, L. Chan, D. Sylvester, C.-H. Heng, G. Samudra, and Y.-C. Yeo, "A double-gate tunneling field-effect transistor with silicon-germanium source for highperformance, low standby power, and low power technology applications," Extended Abstracts of the 2007 International Conference on Solid State Devices and Materials, Ibaraki, Japan, Sep. 18-21, 2007, pp. 894-895. [14] E.-H. Toh, G. H. Wang, L. Chan, G. Samudra, and Y.-C. Yeo, "Device Design and Scalability of an Impact-Ionization MOS Transistor with an Elevated Impact Ionization Region," 2007 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Vienna, Austria, Sep. 25-27, 2007. [15] C. Shen, J. Lin, E.-H. Toh, K.-F. Chang, P. Bai, C.-H. Heng, G. S. Samudra and Y.-C. Yeo, “On the performance limit of I-MOS transistors,” IEEE International Electron Device Meeting 2007, Washington, D.C., Dec. 10-12, 2007, pp. 117-120. [16] G. H. Wang, E.-H. Toh, X. Wang, D. H.-L Seng, S. Tripathy, T. Osipowicz, T.-K Chan, K.M. Hoe, C.-H. Tung, S. Balakumar, G.-Q. Lo, G. S. Samudra, and Y.-C. Yeo, " SiliconGermanium-Tin (SiGeSn) Source and Drain Stressors formed by Sn Implant and Laser Annealing for Strained Silicon-Germanium Channel P-MOSFETs ," IEEE International Electron Device Meeting 2007, Washington, D.C., Dec. 10-12, 2007, pp. 131-134. List of Publications 185 [17] E.-H. Toh, G. H. Wang, M. Zhu, C. Shen, L. Chan, G.-Q. Lo, C.-H. Tung, D. Sylvester, C.H. Heng, G. Samudra, and Y.-C. Yeo, "Impact ionization nanowire transistor with multiplegates, silicon-germanium impact ionization region, and sub-5 mV/decade subtheshold swing," IEEE International Electron Device Meeting 2007, Washington DC, Dec. 10-12, 2007, pp. 195-198. [18] G. H. Wang, E.-H. Toh, D. Weeks, T. Landin, J. Spear, C. H. Tung, S. G. Thomas, G. Samudra, and Y.-C. Yeo, "Strained Si n-FET featuring compliant SiGe Stress Transfer Layer (STL) and Si0.98C0.02 Source/Drain Stressors for Performance Enhancement," International Semiconductor Device Research Symposium, College Park MD, USA, Dec. 12-14, 2007. [19] E.-H. Toh, G. H. Wang, C. Shen, M. Zhu, L. Chan, C.-H. Heng, G. Samudra, and Y.-C. Yeo, "Silicon Nano-Wire Impact Ionization Transistors with Multiple-Gates For Enhanced Gate Control and Performance," International Semiconductor Device Research Symposium, College Park MD, USA, Dec. 12-14, 2007. [20] G. H. Wang, E.-H. Toh, X.-C. Wang, D. K.-Y. Low, S. Tripathy, Y.-L. Foo, G. Samudra, and Y.-C. Yeo, "Lattice compensation of Boron in Sn+ implanted Silicon-Germanium p+/n to achieve high quality strained SiGeSn upon pulsed laser annealing," Materials Research Society Spring Meeting, Mar. 24-28, 2008. [21] E.-H. Toh, G. H. Wang, X.-C. Wang, S. Tripathy, Y.-L. Foo, L. Chan, G. Samudra, and Y.C. Yeo, "Formation of germanium-tin (Ge0.85Sn0.15) on germanium by co-sputtering and pulse laser annealing," Materials Research Society Spring Meeting, Mar. 24-28, 2008. [22] G. H. Wang, E.-H. Toh, X.-C. Wang, D. H. L. Seng, S. Tripathy, Y.-L. Foo, G. Samudra, and Y.-C. Yeo, "Contact technology for germanium-tin (GeSn) source/drain using nickel and nickel-platinum alloys," Materials Research Society Spring Meeting, Mar. 24-28, 2008. [23] Best Paper Award. E.-H. Toh, G. H. Wang, D. Weeks, M. Zhu, T. Landin, J. Spear, L. Chan, S. G. Thomas, G. Samudra, and Y.-C. Yeo, "P-Channel I-MOS transistor featuring silicon nano-wire with multiple-gates, strained Si1-yCy I-region, In situ doped Si1-yCy Source, and sub-5 mV/decade subthrehold swing," International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, Apr. 21-23, 2008. List of Publications 186 [24] G. H. Wang, E.-H. Toh, T. Osipowicz, T. K. Chan, Y.-L. Foo, C. H. Tung, G. Samudra, and Y.-C. Yeo, "Strained silicon-germanium channel P-MOSFETs featuring Sn implanted silicon-germanium-tin (SiGeSn) source and drain stressors formed by solid phase epitaxy," International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, Apr. 21-23, 2008. [25] G. H. Wang, E.-H. Toh, X. Wang, D. H. L. Seng, S. Tripathy, T. Osipowicz, T. K. Chan, G. Samudra, and Y.-C. Yeo, "Performance enhancement schemes featuring lattice mismatched S/D stressors for CMOS: Embedded SiGeSn S/D for pFETs by Sn+ implant and SiC S/D for nFETs by C+ implant," Symp. on VLSI Tech. 2008, Honolulu HI, USA, Jun. 17-19, 2008. [26] Invited Paper. Y.-C. Yeo, G. Samudra, C.-H. Heng, E.-H. Toh, and C. Shen, "Nanowire Impact Ionization Transistor (I-FETs),"2008 International Conference on Solid-State Devices and Materials, Ibaraki, Japan, Sep. 23 - 26, 2008. [27] Invited Paper. G. Samudra, Y.-C. Yeo, C.-H. Heng, E.-H. Toh, Litao Yang, and S.P. Vijayaran, "Simulation of Strain and Material Engineering of Tunneling Field-Effect Transistor with Subthreshols Swing below 60 mV/decade,"2008 International Conference on Solid-State Devices and Materials, Ibaraki, Japan, Sep. 23 - 26, 2008. [28] C. Shen, L. T. Yang, E.-H. Toh, C.-H. Heng, G. S. Samudra, and Y.-C. Yeo, "A new robust non-local algorithm for band-to-band tunneling simulation and its application to tunnelFET," International Symposium on VLSI Technology, Systems and Applications (VLSITSA), Hsinchu, Taiwan, Apr. 27-29, 2009, pp. 113-114. "Many of life's failures are people who did not realize how close they were to success when they gave up." -- Thomas Edison [...]... (a) Plot of drain current ID as a function of gate overdrive (VG –VT) for I-MOS with Si RSD, and Si0.99C0.01 RSD Both devices have a LG of 60 nm and LI of 60 nm with an EOT of 30 Å The elevated I-region (TI) for both Si RSD and Si0.99C0.01 RSD is 30 nm Excellent subthreshold swing S of 4.46 mV/decade and 3.56 mV/decade is achieved, respectively (b) Plot of transconductance Gm as a function of gate overdrive... –VT) for I-MOS with Si RSD, and Si0.75Ge0.25 RSD Both devices have a LG of 60 nm and LI of 60 nm with and EOT of 30 Å The elevated I-region (TI) for both Si RSD and Si0.75Ge0.25 RSD is 30 nm Excellent subthreshold swing S of 4.46 mV/decade and 3.28 mV/decade is achieved, respectively (b) Plot of transconductance Gm as a function of gate overdrive (VG –VT) for I-MOS with Si RSD, and Si0.75Ge0.25 RSD A three-fold... from the off-state to the on-state With LH of 2 nm, ωT is reduced This will enhance the band-to-band tunneling (BTBT) rate, and hence on-state current Ion .127 Figure 7.8 (a) Plot of (a) off-state current Ioff, and (b) on-state current Ion, as a function of LH Generally, both Ioff and Ion increase as the overlap of the hetero-junction with the gate (LH) increases Both minimum and maximum... 6.6 Plot of Ioff and Ion/Ioff ratio as a function of substrate doping concentrations NB Ioff decreases as NB increases This also causes the Ion/Ioff ratio to increase .111 Figure 6.7 Threshold voltage VT generally increases with increasing TI LS and TI are two adjustable parameters that allows for the flexibility of VT tuning 112 Figure 6.8 Plot of Ioff and Ion/Ioff ratio as a function of I-region... nchannel devices Ion is measured at (VG–VT) = 1.0 V An Ion enhancement of ~2-3 times is observed for Si060Ge0.40 devices at matched VT or the same Ioff 50 Figure 3.21 (a) Plot of off-state current Ioff measured at (VG–VT) = 0.2 V as a function of VT for pchannel I-MOS devices The Ioff of Si I-MOS device is much higher than that of SiGe I-MOS device at the same VT (b) Plot of Ioff as a function of Ion... coefficient of Ge is at least 1-2 orders of magnitude higher than that of Si 107 Figure 6.3 Simulated ID-VG plot of Si and Ge n-channel LI-MOS transistors with source bias VS of -5.25V and -1.8V respectively The drain is grounded Excellent subthreshold swing of sub-5 mV/decade is achieved for both devices Ge LI-MOS has a much superior Ion/Ioff ratio than Si LI-MOS due to the lower bandgap of Ge ... 5.16 (a) Overview of the I-FinFET process flow The fabrication of I-FinFET is CMOS process-compatible, and could be integrated with conventional CMOS planar and FinFET devices SEM view of (b) I-FinFET after gate formation, and (c) I-FinFET rotated by 135º, showing the source being masked by photo-resist (d) TEM view of the fabricated SiGe-SD/SiGe I-FinFET with a gate length LG of 50 nm and a total IRegion... Measured ID-VG and (b) Gm -(VG -VT) for n-channel I-FinFET devices with 50nm gate length, and 40nm I-region The threshold voltages VT are 1.28 V and 0.46 V, respectively SiGe I-Region results in lower VT and higher Ioff at a fixed VS and VD of -4.75 V and 1.0 V, respectively .99 Figure 5.20 Gate transfer characteristics for p-channel I-FinFET devices with 50nm gate length, and 40nm I-region... are -1.22 V and -0.56 V, respectively SiGe I-Region results in lower VT and higher Ioff at a fixed VS and VD of 4.75 V and 1.0 V, respectively 99 Figure 5.21 (a) Off-state current Ioff measured at (VG –VT) = -0.2 V plotted as a function of VT for n-channel I-FinFET revealing that at matched VT, the Ioff of Si I-FinFET is much higher than that of SiGe I-FinFET (b) Measured Ioff - Ion plot... lower breakdown voltages VBD (experimentally measured) for both nand p-channel SiGe I-MOS devices .46 Figure 3.18 Plot of (a) drain current ID and (b) transconductance Gm, as a function of gate overdrive (VG–VT) for Si, Si0.75Ge0.25 and Si0.40Ge0.40 n-channel I-MOS devices All devices have a LG of 50 nm and LI of 40 nm with an EOT of 30 Å Higher ID is achieved at higher Ge content due to lower . Plot of drain current I D as a function of gate overdrive (V G –V T ) for I-MOS with Si RSD, and Si 0.75 Ge 0.25 RSD. Both devices have a L G of 60 nm and L I of 60 nm with and EOT of 30. Plot of drain current I D as a function of gate overdrive (V G –V T ) for I-MOS with Si RSD, and Si 0.99 C 0.01 RSD. Both devices have a L G of 60 nm and L I of 60 nm with an EOT of 30. SIMULATION AND FABRICATION OF NOVEL DEVICES WITH STEEP SUBTHRESHOLD SLOPE TOH ENG HUAT (B.Eng (Hons.), NUS) A THESIS SUBMITTED FOR THE DEGREE OF Ph.D (ENGINEERING)