Development of an integrated bake chill system for microlithography

Founded 1905 DEVELOPMENT OF AN INTEGRATED BAKE/CHILL SYSTEM FOR MICROLITHOGRAPHY WANG LAN (M.Sc., M.Eng., B.Eng.) A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2008 Summary In this thesis, an integrated bake/chill system for microlithography process using a stream of air is introduced. This system has the ability to deliver uniform temperature distribution across the wafer surface and to achieve a fast temperature transient response. Intuitively, uniform airflow in terms of temperature and velocity can ensure good temperature uniformity across the wafer surface. We also expect the transient response to be relatively proportional to the velocity of the airflow. This novel idea is verified by the wind tunnel experimental results. In the first design, a simple prototype which tries to emulate the wind tunnel environment with its simple and small structure is presented. According to the simulation and experimental results, this prototype can deliver reasonably good temperature uniformity across the wafer surface. However, this design has some major drawbacks: 1). Low energy efficiency. A lot of energy will be lost from the single layer steel stainless wall. 2). Because the wafer is immersed into the chamber, there will be a layer of “crust” on the top surface of the photoresist which prevents the solvent from evaporating from the photoresist. This will affect the function of the photoresist. 3). The temperature uniformity across the wafer is hard to control. Therefore, a box-type chamber is introduced to overcome these limitations. In the box-type chamber design, the function of the linearly taped bottom surface is to achieve different airflow velocity profile along the passage so that desirable heat transfer coefficient distribution can be achieved. Therefore, good temperature uniformity across the wafer surface can be achieved during the baking i Summary ii process. In addition, the wafer sits on top of the chamber and is heated up by only back-heating so that “crust” can be avoided on the top surface of the photoresist. Also, the airflow can be recirculated into the chamber to increase the energy efficiency. Ideally, a nonlinear profiled bottom surface should be designed to achieve better temperature uniformity. However, such a surface will be very difficult to achieve as the analytical relationship between surface profile and temperature uniformity is extremely complex. A 2-slope profile for the bottom surface is investigated and simulation results show the effectiveness of this profile. In addition, the effects of the airflow velocity and airflow temperature on the temperature uniformity are also evaluated through extensive simulations. Acknowledgments To begin with, I would like to express my utmost gratitude to my supervisors, A/P Loh Ai Poh and Dr Gong ZhiMing, for their wisdom, patience and unfailing guidance throughout the course of my PhD study. I have indeed benefited tremendously from the regular discussions with them. Without their encouragement and help, this project and thesis would have been impossible. I would also like to thank Mr. Chow Siew Loong for helping me to set up the experiments and giving me many critical support through the project. Then, I would like to thank Professor Arun Sadashiv Mujumdar for many useful discussion on my project. In addition, special thanks goes to Dr Lou Jing and Mr. Zhang BaiLi from Institute of High Performance Computing for their help in the FLUENT simulation work. I am also grateful to Madam Vathi, Lim LiHong, Lu JingFang, Huang Ying, Fu Jun, Wu XiaoDong, Ye Zhen, Hu Ni, Lu Xiang, Liu Min and many others in the Advanced Control Technology Lab for their friendship and invaluable technical assistance to me. Furthermore, I would like to thank National University of Singapore and Singapore Institute of Manufacturing Technology for their funding to this project. Last but not least, I would also like to thank my family, especially my wife Shan DongMei, for their love, encouragement, understanding and support. Wang Lan August, 2008 iii Contents Summary i Acknowledgments iii List of Figures viii List of Tables xii Introduction 1.1 Research Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Challenges and Trends in the Semiconductor Industry . . . . . . . . 1.3 Microlithography . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.1 Bake/Chill Steps in Microlithography . . . . . . . . . . . . . 1.3.2 Temperature Effects on CD in Microlithography . . . . . . Methods to Achieve Temperature Requirements . . . . . . . . . . . 1.4.1 Design of Thermal Processing Equipment . . . . . . . . . . . 1.4.2 Modelling and Temperature Control Techniques . . . . . . . 10 1.5 Scope of Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.6 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.4 iv Contents v Overview Of Wafer Bake/Chill System For Microlithography 18 2.1 State of the Art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2 Related Prior Art . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.1 Conduction Approach . . . . . . . . . . . . . . . . . . . . . 21 2.2.2 Convection Approach . . . . . . . . . . . . . . . . . . . . . . 23 2.2.3 Radiation Approach . . . . . . . . . . . . . . . . . . . . . . 25 2.2.4 Combined Modes . . . . . . . . . . . . . . . . . . . . . . . . 26 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.3 Design Consideration And Proof Of Concept 3.1 29 Design 1: Based on the Wind Tunnel . . . . . . . . . . . . . . . . . 29 3.1.1 Experimental Set-up . . . . . . . . . . . . . . . . . . . . . . 30 3.1.1.1 Results for Vertical Configuration . . . . . . . . . . 31 3.1.1.2 Results for Horizontal Configuration . . . . . . . . 32 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.2 Design 2: The Vertical Integrated Bake/Chill System . . . . . . . . 35 3.3 Design : Tapered Box Chamber . . . . . . . . . . . . . . . . . . . 36 3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.1.2 The Vertical Integrated Bake/Chill Prototype System 37 4.1 Prototype Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4.2 Simulation Model and Steady State Results . . . . . . . . . . . . . 38 4.3 Experimental Set-up and Results . . . . . . . . . . . . . . . . . . . 42 4.3.1 42 Prototype System . . . . . . . . . . . . . . . . . . . . . . . . Contents 4.4 vi 4.3.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . 43 4.3.3 Comparison with Transient Simulation Result . . . . . . . . 45 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Tapered Box Design 48 5.1 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.2 Model and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.2.1 Mathematic Model (Navier-Stokes Equations) . . . . . . . . 51 5.2.2 Boundary Conditions . . . . . . . . . . . . . . . . . . . . . . 53 Effect of Tapered Chamber . . . . . . . . . . . . . . . . . . . . . . . 54 5.3.1 Effect of Gradient on Heat Transfer . . . . . . . . . . . . . . 54 5.3.2 Grid Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . 56 5.4 Merits of Box-type Chamber Design . . . . . . . . . . . . . . . . . . 62 5.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.3 Effect Of A Two-Slope Profile For The Bottom Surface 66 6.1 Design of a Piecewise Linear Profile . . . . . . . . . . . . . . . . . . 66 6.2 Effect of a 2-Slope Profile . . . . . . . . . . . . . . . . . . . . . . . 68 6.2.1 2D Simulation Results . . . . . . . . . . . . . . . . . . . . . 69 6.2.2 3D Simulation Results . . . . . . . . . . . . . . . . . . . . . 70 6.2.3 Effect of Bottom Surface Curvature . . . . . . . . . . . . . . 72 Effect of Inlet Velocity . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3.1 75 6.3 Effect of Different Velocity Settings . . . . . . . . . . . . . . Contents 6.3.2 6.4 6.5 vii Effect of Different Velocity Profile . . . . . . . . . . . . . . . Effect of Inlet Temperature 76 . . . . . . . . . . . . . . . . . . . . . . 78 6.4.1 Effect of Different Temperature Settings . . . . . . . . . . . 79 6.4.2 Effect of Different Temperature Profile . . . . . . . . . . . . 80 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Conclusion 83 7.1 Summary of Results . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.2 Future Developments . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Publication 87 Bibliography 88 Appendix 97 List of Figures 1.1 Typical steps in microlithography . . . . . . . . . . . . . . . . . . . . 1.2 Line width change as a function of PEB time [24] . . . . . . . . . . . . 2.1 Track systems used in semiconductor manufacturing industry . . . . . . 19 2.2 NUS multi-zone hot plate baking system . . . . . . . . . . . . . . . . . 20 2.3 Schematic of hot plate . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.4 Schematic of an integrated bake/chill system . . . . . . . . . . . . . . 22 2.5 Schematic of hot plate with variable surface . . . . . . . . . . . . . . . 23 2.6 Schematic of hot air chamber for PEB step . . . . . . . . . . . . . . . 24 2.7 Schematic of a re-circulated liquid bath baking apparatus . . . . . . . . 24 2.8 Schematic of a programmable multi-zone baking system . . . . . . . . . 25 2.9 Schematic of a radiation heating apparatus . . . . . . . . . . . . . . . 25 2.10 Schematic of a combined wafer baking chamber . . . . . . . . . . . . . 26 2.11 Schematic of a combined wafer baking system . . . . . . . . . . . . . . 27 2.12 Schematic of a combined baking resist system . . . . . . . . . . . . . . 27 2.13 Schematic of a multi-zone bake/chill thermal cycling module . . . . . . 28 3.1 30 Wind tunnel set up . . . . . . . . . . . . . . . . . . . . . . . . . . . viii List of Figures ix 3.2 Wafer with RTDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.3 Temperature profile under vertical case(airflow is 5m/s) . . . . . . . 32 3.4 Temperature profile under horizontal case(airflow is 5m/s) . . . . . 33 3.5 Schematic of vertical system . . . . . . . . . . . . . . . . . . . . . . 35 3.6 Schematic of tapered box chamber . . . . . . . . . . . . . . . . . . 36 4.1 Prototype schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.2 Schematic of simulation model . . . . . . . . . . . . . . . . . . . . . . 39 4.3 Wafer temperature distribution at steady state . . . . . . . . . . . . . 41 4.4 Temperature distribution across section . . . . . . . . . . . . . . . . . 41 4.5 Velocity distribution across section . . . . . . . . . . . . . . . . . . . . 42 4.6 Prototype(external view) . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.7 Prototype(internal view) . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.8 Temperature profile on wafer . . . . . . . . . . . . . . . . . . . . . . . 43 4.9 Temperature uniformity across the wafer . . . . . . . . . . . . . . . . . 44 4.10 Transient response comparison between simulation and experiment . . . 46 5.1 Schematics of box-type chamber with curved bottom surface . . . . . . 49 5.2 Schematics of flatten-bottom box-type chamber with slope angle . . . . 50 5.3 Grid design of wafer and chamber top surface . . . . . . . . . . . . . . 57 5.4 Cross section view of flatten-bottom box-type chamber with slope angle 58 5.5 Airflow pattern in cross section with 4.6◦ slope angle . . . . . . . . . . 58 5.6 Wafer temperature contour (θ = 0◦ ) . . . . . . . . . . . . . . . . . . . 59 5.7 Temperature profile of wafer diameter under different slope angle . . . . 60 Bibliography [1] K. C. Saraswat, “Programmable Factory for IC Manufactuing for the 21st Centry”, IEEE/SEMI International Semiconductor Manufacturing Science Symposium, pp 2-6, 1993. [2] Y. Nishi, R. Doering, Handbook of Semiconductor Manufacturing Technology, Marcel Dekker INC, 2000. [3] “International Technology Roadmap for Semiconductor”, Semiconductor Industry Association, 2004 update. [4] L. L. Lee , “Microlithography: Control of Temperature and Resist Thickness”, Ph.D. Thesis, National University of Singapore, 2003. [5] M. Quirk, J. Serda, Semiconductor Manufacturing Technology, Prentice Hall, 2001. [6] S. Limanond, J. Si, K. S. Tsakalis, “Monitoring and Control of Semiconductor Manufacturing Processes”, IEEE Control Systems, Vol.18, 6, pp 46-58, December 1998. [7] Introduction and Overview of Semiconductor Manufacturing Process, Singapore-MIT Alliance Course 6301 Lecture Notes, 2001. [8] B. Cohen, W. Renken, P. Miller, “Dynamic temperature profiling for post exposure bake”, in http://www.reed-electronics.com/semiconductor /article/CA274034?text=peb. 88 Bibliography 89 [9] P. V. Zant, Microchip Fabrication, 4th edition, McGraw-Hill, 2000. [10] H. J. Levison, Lithography Process Control, SPIE Optical Press, 1999. [11] G. Arthur, N. Eilbeck, B. Martin, “Effect of Temperature Variations in the Post-Exposure Processes of Optical Lithography”, Microelectronic Engineering, 35, pp 137-140, 1997. [12] R. A. Soper, “Adaptive Control of Photolithography”, Ph.D. Thesis, University of California, Santa Barbara, 1992. [13] M. L. Miller, “Use of Scatterometric Measurements for Control of lithography”, Ph.D. Thesis, University of California, Santa Barbara, 1994. [14] R. A. Soper, D. A. Mellochamp, D. E. Seborg, “Adaptive Photo-lithography Control Using Development Time Manipulation”, SPIE, Process Module Metrology, Contol and Clustering, 1594, pp 508-526, 1991. [15] L. L. Lee, C. D. Schaper, W. K. Ho, “Real-time Control of Photoresist Thickness Uniformity During the Bake Process”, Proceeding of SPIE, Vol.4182, pp 54-64, 2000. [16] L. L. Lee, C. D. Schaper, W. K. Ho, “Real-time Predictive Control of Photoresist Film Thickness Uniformity”, IEEE Transaction on Semiconductor Manufacturing, Vol.15, No.1, pp 51-59, 2002. [17] W. K. Ho, L. L. Lee, C. D. Schaper, “On Control of Resist Film Uniformity In the Microlithography Process”, 15th IFAC World Congress, Barcelona, 2002. [18] W. K. Ho, L. L. Lee, A. Tay, C. D. Schaper, “Resist Film Uniformity In the Microlithography Process”, IEEE Transaction on Semiconductor Manufacturing, Vol.15, No.3, pp 323-330, 2002. [19] L. Peters. “Designing tracks for better CD control”, in http://www.reedelectronics.com/semiconductor/article/CA319214?text=tracks. Bibliography 90 [20] Y. S. Sohn, D. S. Sohn, H. K. Oh, “Effect of temperature variation during post exposure bake on 193 nm chemically amplified resist simulation”, IEEE on Microprocesses and Nanotechnology Conference, pp 100-101, July 2000. [21] O. Nalamasu, E. Reichmanis, A. G. Timko, R. Tarascon, A. E. November, S. Slater, H. Holzwarth, P. Falcigno and N. M¨ unzel, “A unified approach to resist materials design for the advanced lithography”, Microelectronic Engineering, 27, pp 367-370, 1995. [22] J. L. Sturtevant, S. J. Holmes, T. G. V. Kessel, P. C. Hobbs, J. C. Shaw, R. R. Jackson, “Post-Exposure Bake As a Process-Control Parameter for Chemically-Amplified Photoresists”, Proceeding of SPIE, Vol.1926, pp 106114, 1993. [23] M. D. Simith, C. A. Mack, J. S. Petersen, “Modeling the Impact of Thermal History during Post Exposure Bake on the Lithography Performance of Chemically Amplified Resist”, SPIE’s 26th Annual International Symposium on Microlithography , 2001. [24] Y. M. Lee, M. G. Sung, E. M. Lee, Y. S. Sohn, H. J. Bak, H. K. On, “Temperature Rising Effect of 193 nm Chemically Amplified Resist during Post Exposure Bake”, Proceeding of SPIE, Vol.3999, 2000. [25] J. Parker, W. Renken, “Temperature metrology for CD control in DUV lithography”. Semiconductor International, Vol. 20, No. 10, pp 111-116, September 1997. [26] A. P. Loh, A. Huang, W. W. Tan, K. W. Lim, W. K. Ho, “Control of an integrated Bake/Chill System”, Proceedings of the 38th Conference on Decision & Control, Phoenix, Arizona, USA. pp 4198-4203, December 1999. [27] K. EI-Awady, C. D Schaper, T. Kailath, “Integrated bake/chill for photoresist processing”. IEEE Transaction on Semiconductor Manufacturing, Vol. 12, No. 2, May 1999. Bibliography 91 [28] C. D. Schaper, K. EI Awady, T. Kailath, “Multizone bake/chill thermal cycling modules”, US patent: 5802856, 1998. [29] http://www.sematech.org/resources/publishing/directionary. [30] N. Namanan, F. F. Liang, J. B. Sims, “Conjugate heat-transfer analysis of 300-mm bake station”, Proceeding of SPIE, Vol.3678, pp 1296-1306, 1999. [31] B. Zhou, “Thermal analysis of hot plate resist baking using a lumped capacitance model”, Proceeding of SPIE, Vol.3677, pp 754-763, 1999. [32] D. P. DeWitt, T. C. Niemoeller, C. A. Mack, G. Yetter, “Thermal design methodology of hot and chill plate for photolithography”, Proceeding of SPIE, Vol.2196, pp 432-448, 1994. [33] C. A. Mack, D. P. DeWitt, B. K. Tsai, G. Yetter, “Modeling of Solvent Evaporation Effects for Hot Plate Baking of Photoresist”, Proceeding of SPIE, Vol.2195, pp 584-595, 1994. [34] C. W. Liu, M. H. Lee, C. Y. Chao, C. Y. Chen, C. C. Yang, “The Design of Rapid Thermal Process for Large Diameter Applications”. IEEE 1998 Semiconductor Manufacturing Technology Workshop, Hsin Chu, Taiwan, April 1998. [35] T. F. Edgar, S. W. Butler, W. J. Campbell, C. Pfeiffer, C. Bode, S. B. Hwang, K. S. Balakrishnan, J. Hahn, “Automatic control in microelectronic manufacturing: Practices, challenges, and possibilities”, Automatica, Vol. 36, pp 1567-1603, 2000. [36] F. Y. Sorrell, H. A. Harris, R. S. Gyurcsik, “A Global Model for Rapid Thermal Processors”, IEEE Transaction on Semiconductor Manufacturing, Vol. 3, No. 4, November 1990. [37] R. S. Gyurcsik, T. J. Riley, F. Y. Sorrell, “A Model for Rapid Thermal Processing: Achieveing Uniformity Through Lamp Control”, IEEE Transaction on Semiconductor Manufacturing, Vol. 4, No. 1, pp 9-13, February 1991. Bibliography 92 [38] A. Tay, W. K. Ho, Y. P. Poh, “Minimum Time Control of Conductive Heating System for Microelectronics Processing”, IEEE Transaction on Semiconductor Manufacturing, Vol. 14, No. 4, pp 381-386, November 2001. [39] W. K. Ho, A. Tay, C. D. Schaper, “Optimal Predictive Control with Constraints for the Processing of Semiconductor Wafers on Bake Plates”, IEEE Transaction on Semiconductor Manufacturing, Vol. 13, No. 1, pp 88-96, February 2000. [40] N. Matsunaga, I. Nanno, M. Tanaka, S. Kawaji, “A New Method of Temperature Control for the Uniform Heating”, The 29th Annual Conference of the IEEE in Industrial Electronics Society, Vol. 3, pp 2097-2102, November 2003. [41] P. Dress, T. Gairing, W. Saule, U. Dietze, J. Szekeresch, “Improved Baking of Photomasks by a Dynamically Zone-Controlled Process Approach”, Proceeding of SPIE, Vol.4409, pp 356-363, 2001. [42] P. R. N. Childs, J. R. Greenwood, C. A. Long, “Review of temperature measurement”, Review of Scientific Instruments, Vol. 71, No. 8, pp 2959-2978, August 2000. [43] Y. J. Lee, C. H. Chou, B. T. Khuri-Yakub, K. C. Saraswat, M. Moslehi, “Photoacoustic Measurements of Silicon Wafer Processing Temperature”, 1989 IEEE Ultrasonics Symposium, pp 535-538, 1989. [44] S. Bhardwaj, S. S. Mohan, R. J. Drozd, B. T. Khuri-Yakub, K. C. Saraswat, “In-Situ Film Thickness And Temperature Monitoring Using GHz Acoustic Phase Measurement System”, 1991 Ultrasonics Symposium, pp 965-967, 1991. [45] F. L. Degertekin, J. Pei, Y. J. Lee, B. T. Khuri-Yakub, K. C. Saraswat, “In-situ Ultrasonic Thermometry of Semiconductor Wafers”, 1993 Ultrasonics Symposium,pp 375-377, 1993. Bibliography 93 [46] Y. J. Lee, F. L. Degertekin, J. Pei, B. T. Khuri-Yakub, K. C. Saraswat, “Insitu Acoustic Thermometry and Tomography for Rapid Thermal Processing”, IEEE IEDM 1993, pp 187-190, 1993. [47] F. L. Degertekin, J. Pei, B. V. Honein, B. T. Khuri-Yakub, K. C. Saraswat, “Thin Film Effects in Ultrasonic Wafer Thermometry”, 1994 Ultrasonics Symposium,pp 1337-1341, 1994. [48] F. L. Degertekin, J. Pei, B. T. Khuri-Yakub, K. C. Saraswat, “In-situ Acoustic Temperature Thermometry of Semiconductor Wafers”, Appl. Phys. Lett., Vol.64(11), pp 1338-1340, March 1994. [49] J. Pei, F. L. Degertekin, B. V. Honein, B. T. Khuri-Yakub, K. C. Saraswat, “In-Situ Thin Film Thickness Measurement Using Ultrasonics Waves”, 1994 IEEE Ultrasonics Symposium, pp 1237-1240, 1994. [50] Y. J. Lee, B. T. Khuri-Yakub, K. C. Saraswat, “Temperature Measurement in Rapid Thermal Processing Using the Acoustic Temperature Sensor”, IEEE Trans. On Semiconductor Manufacturing, Vol.9, No.1. pp 115-121, February 1996. [51] J. Pei, B. T. Khuri-Yakub, F. L. Degertekin, B. V. Honein, F. E. Stanke, K. C. Saraswat, “In-Situ Simultaneous Measurement of Temperature and Thin Film Thickness with Ultrasonic Techniques”, 1996 IEEE Ultrasonics Symposium, pp 1039-1042, 1996. [52] S. L. Morton, F. L. Degertekin, B. T. Khuri-Yakub, “Ultrasonic Cure Monitoring of Photoresist During Pre-Exposure Bake Process”, 1997 IEEE Ultrasonics Symposium, pp 837-840, 1997. [53] S. L. Morton, F. L. Degertekin, B. T. Khuri-Yakub, “Ultrasonic Sensor for Photoresist Process Monitoring”, IEEE Transaction on Semiconductor Manufacturing, Vol.12, No.3, pp 332-339, August 1999. Bibliography 94 [54] J. Carman, M. A. Logan, J. Monkowski, “CVD platen heater system utilizing concentric electric heating elements”, US patent: 5294778, 1994. [55] B. I. Sloan, “Vertical multi-process bake/chill apparatus”, US patent: 5431700, 1995. [56] M. D. Webster, “Method of heating a substrate using a variable surface hot plate for improved bake uniformity”, US patent: 6576572 B2, 2003. [57] Y. Noritsugu, “Baking device and method”, JP patent: 10055951, 1996. [58] B. J. Rolfson, “Method and apparatus for uniformly baking substrate such as photomasks”, US patent: 2003/0124469 A1, 2003. [59] M. M. Moslehi, C. J. Davis, R. T. Matthews, “Programmable multizone has injector for single-wafer semiconductor processing equipment”, US patent: 5453124, 1995. [60] H. Amada, “Method and apparatus for the heat-treatment of a plate-like member”, US patent: 4593168, 1986. [61] Y. Matsuyama, “Heat processing method and apparatus”, US patent: 6246030 B1, 2001. [62] K. Shouzou, F. Takamitsu, T. Keisuke, S. Kouhei, W. Akira, N. Tadashi, M. Koki, Y. Azuza, O. Katsuo, “Method and apparatus for performing baking treatment to semiconductor wafer”, US patent: 2003/0057198 A1, 2003. [63] J. G. Cho, “Apparatus for baking resists on semiconductor wafers”, US patent: 6056544, 2000. [64] FLUENT Users Manual, Fluent Inc., Lebanon, New Hampshire, 1998. [65] F. P. Incropera, D. P. DeWitt, Fundamentals of Heat and Mass Transfer, 5th Edition, Wiley, 2002. [66] B. E. Launder and D. B. Spalding, Mathematical Models of Turbulence, Academic Press, Londer, England, 1972. Bibliography 95 [67] J. P. Holman, Heat Transfer, 8th Edition, McGram-Hill, 1997. [68] A. Bejan. Convection Heat Transfer, 2nd Edition, John Wiley & Sons Inc, 1995. [69] “What is NURBS” in http://www.rhino3d.com/nurbs.htm [70] L. Piegl, “On NURBS: A Survey”, IEEE Computer Graphics and Application, Vol.11, No.1, pp 55-71, January 1991. [71] L. Piegl, W. Tiller, The NURBS Book, 2th Edition, Springer, 1996. [72] A. C. Pfahnl, J. H. Lienhard, V, adn Alexander H. Slocum, “Heat-Transfer Enhancing Features for Handler Tray-Type Device Carriers”, IEEE Trans. on Computer, Packing, and Manufacturing Technology, Vol. 21, No. 4, pp 302-310, Octbter 1998. [73] W. M. Rohsenow, J. P. Hartnett, E. N. Gani´ c, Handbook of Heat Transfer Applications, 2th Edition, McGraw-Hill Book Company, 1985. [74] H. R. E. M. H¨ornlein, K.Schittkowski. Software System For Structural Optimization, Birkh¨auser, 1993. [75] L. T. Lamont, “Method of thermal treatment of a wafer in an evacuated environment”, US patent: 4743570, 1998. [76] N. Yoshiaki, “Method and device for baking photoresist”, JP patent: 01243063, 1989. [77] J. Blechschmid, R. D. Coyne, D. Palmer, J. A. Piatt, “Apparatus for vapor sheathed baking of semiconductor wafers”, US patent: 4556785, 1985. [78] W. T. Batchelder, “Method and apparatus for baking and cooling semiconductor wafers and the like”, EP patent: 0657918 A2, 1995. [79] H. Bolandi, A. Tepman, “Integrated bake and chill plate”, US patent: 2001/0003901 A1, 2001. Bibliography 96 [80] M. A. McNeily, “Semiconductor substrate heater and reactor process and apparatus”, US patent: 4778559, 1988. [81] B. Lu, E. Weisbrod, D. J. Resnick, K. J. Nordquist, “Method of making an integrated circuit”, US patent: 2002/0092839 A1, 2002. [82] C. J. Yun, “Baking apparatus for manufacturing a semiconductor device”, US patent: 2004/0048219 A1, 2004. Appendix: Prior Art Search Report And Comments This table contains the results of prior art search, comments on the relevancy of these prior arts and describe the differences or similarities accordingly with the box-type chamber design. Prior Arts Comments [ Refnumber&Title ] Relevant portion(s) / claim(s). Relevance: [ N: Not, L:Low, M: Medium, H: High ] 1. JP patent[10055951], 1998: [ H ] For Post Exposure Bake application. Wafer is baked by using a stream Baking device and method [57] of inert gas. The gas is injected into processing chamber from bottom and exhausted from the top. Wafer is supported by three pins. Difference with our invention: Air flow direction is different from the horizontal one in our invention. Chamber wall is in regular shape. No chilling is included. 97 Appendix: Prior Art Search Report And Comments 2. 98 US patent[4743570],1988: [ H ]. In the vacuum chamber apparatus, a wafer is heated or cooled by Method of thermal treatment introducing a low pressure gas in a region between wafer and heating element. of a wafer in an evacuated en- The gas conducts thermal energy between wafer and heating element. vironment [75] Difference with our invention: Air flow direction is different from the horizontal one in our invention. Chamber wall is flat. This apparatus is operated in vacuum status with a pressure of approximately 100 to 1000 micro. 3. JP patent[01243063],1989: [ H ]. For photo resist baking process. A stream of inert gas at prescribed Method and device for baking temperature is blown for the prescribed period of time to the wafer on which photoresist [76] photo resist is formed. Many holes for blowing gas are disposed uniformly at the plate to improve the temperature uniformity of the baking state. Difference with our invention: Air flow direction is different from the horizontal one in our invention. Uniform temperature distribution across the wafer can be achieved by uniform distribution of holes. No chilling is included. 4. US patent[5453124],1994: [ H ]. A programmable multi-zone fluids injector is used in single wafer pro- Programmable multizone has cessing. Each zone is connected to a source of process fluids by means of injector for single-wafer semi- appropriate passageways. Each zone has at least one independent fluid con- conductor processing equip- trol device to control the amounts and the ratios of fluids. ment [59] Difference with our invention: Air flow direction is different from the horizontal one in our invention. Uniform or non-uniform gas distribution across the wafer is obtained by uniform distribution of orifices. The apparatus is not limited to baking and chilling process. Appendix: Prior Art Search Report And Comments 5. US patent[2003/0057198 A1], 2003: 99 [ H ]. For photo resist baking process. In the baking oven, wafer is heated on Method and ap- a hot plate. A stream of hot air is injected into the oven. A gas temperature paratus for performing bak- controller is used to make sure that the gas flowing around a peripheral edge ing treatment to semiconduc- or outer portion of the wafer has a higher temperature than that around the tor wafer [62] center portion of the wafer. Difference with our invention: Wafer is heated mainly on hot plate. Air flow direction is different from the horizontal one in our invention. Uniform temperature distribution on wafer surface is achieved by temperature compensation of air flow around the wafer. No chilling is included 6. US patent[6246030 B1], [ H ]. For uniformly baking. Wafer is heated on hot plate. A gas pre-heated 2001: Heat processing method by a heater pass through the space above the wafer in parallel pattern so that and apparatus [61] the wafer is kept uniform during heat processing. Difference with our invention: Wafer is heated by hot plate. Air flow direction is different from the horizontal one in our invention. Uniform temperature distribution on wafer surface is obtained by the parallel gas flow over the wafer. No chilling is included Appendix: Prior Art Search Report And Comments 100 7. US patent[6056544], 2000: [ H ]. For photo resist baking. Wafer is baked on hot plate inside the oven. Apparatus for baking resists on Hot air surrounds the baking chamber to achieve uniform temperature distri- semiconductor wafers [63] bution inside the oven Difference with our invention: Wafer is heated on hot plate. Air flow surrounds the baking chamber. Uniform temperature distribution on wafer surface is obtained by uniform temperature distribution in side the oven. No chilling is included. 8. US patent[4556785], 1985: [ H ]. Wafer is baked on a circular hot plate. The hot plate is sheathed by Apparatus for vapor sheathed a uniform vapour flow. The vapour sheath can be drawn into the exhaust baking chamber after passing over the wafer. of semiconductor wafers [77] Difference with our invention: Wafer is heated on hot plate. Vapour is used to improve the uniform temperature distribution on wafer surface. No chilling is included 9. US patent[5431700],1995: Vertical multi-process /chill apparatus [55] bake [ H ]. Wafer is baked on hot plate. Baking and chilling are integrated into one apparatus. Uniform heating of the wafer is achieved by minimizing air movement between wafer and the bake plate. Wafers loading and unloading are minimized. Difference with our invention: Wafer is heated on hot plate. Uniform temperature distribution on wafer is achieved by minimizing air movement between wafer and the bake plate Appendix: Prior Art Search Report And Comments 10. 101 EP patent[0657918 A2], [ H ]. Baking and chilling are integrated into one apparatus. Wafer is placed 1995: Method and apparatus in close proximity to a hot plate. A thermally conductive and non-reactive for baking and cooling semi- gas is introduced into the air gap between wafer and hot plate. The gas is conductor wafers and the like preheated before introducing into the airspace from a bore of the hot plate. [78] Difference with our invention: Wafer is heated on hot plate by proximity heating. Air flow direction is different from the horizontal one in our invention. 11. US patent[2001/0003901 [ H ]. Baking and chilling are integrated into one apparatus. The integrated A1], 2001: Integrated bake and bake and chill plate has one or more fluid channel in spiralling arrangement chill plate [79] inside. Different fluid flow pattern in different channels are used to achieve uniformity temperature distribution on wafer surface. The integrated bake and chill plate, the thermally conductive plate and the thermoelectric devices are all in thermal contact with each other. Difference with our invention: Wafer is heated mainly by hot plate. Fluids in multiple channels are used. 12. US patent[5802856], 1998: [ H ]. Baking and chilling are integrated into one apparatus. Each zone in the Multi-zone bake/chill thermal multi-zone plate is controlled independently. Fluids are used to provide bulk cycling module [28] heating or cooling to the plate via a fluid heat exchanger. Thermoelectric devices is used to provide localized, precise and rapid control of both heating and cooling. Difference with our invention: Wafer is heated mainly on hot plate. Fluids are used. Appendix: Prior Art Search Report And Comments 13. 102 US patent[2003/0124469 [ H ]. For photo resist baking process. Wafer is baked on hot plate. Liquid A1], 2003: Method and appa- bath is used to provide heat to hot plate, and liquid can be re-circulated to ratus for uniformly baking sub- maintain a constant and uniform temperature gradient across the plate. strate such as photomasks [58] Difference with our invention: Wafer is heated on hot plate. Fluids are used to provide heat to the plate. No chilling is included. 14. US patent[5294778], 1994: [ H ]. Wafer is baked on hot plate. Hot plate includes multiple graphite CVD platen heater system uti- resistance heaters and each heater is controlled independently. The multiple lizing concentric electric heat- heaters include a spiral shaped main resistance heater and two single turn ing elements [54] edge loss heaters. Difference with our invention: Wafer is heated on hot plate. No chilling is included. No air flow is used. 15. patent[4778559], [ H ]. For uniformly heating process. Wafer is heated on hot plate. Hot plate 1988: Semiconductor substrate US contacts directly with the heating source positioned within the reactor. Heat heater and reactor process and is uniformly transferred to the plate by molten metal which has a low melting apparatus [80] point and high boiling point. Difference with our invention: Wafer is heated on hot plate. No chilling is included. No air flow is used. Appendix: Prior Art Search Report And Comments 16. 103 US patent[6576572 B2], [ H ]. For uniformly baking process. Hot plate has a non-flat top surface. 2003: Method of heating a sub- Uniform temperature distribution across the substrate can be achieved by strate using a variable surface varying the distance between wafer and plate. hot plate for improved bake Difference with our invention: Wafer is heated on hot plate. No chilling uniformity [56] is included. No air flow is used. 17. US patent[2002/0092839 [ H ]. The invention can be used for photo resist baking process. Wafer is A1], 2002: Method of making heated both by below hot plate and upper heating element. Wafer is inserted an integrated circuit [81] between to get uniformly baking. Difference with our invention: Wafer is heated on hot plate. No chilling is included. No air flow is used. 18. US patent[2004/0048219 [ H ]. Wafer sits on the hot plate. Hot plate is located in the chamber, and A1], 2004: Baking apparatus a thin film with low emissivity extends over the inner surface of the cover so for manufacturing a semicon- that the heat loss to the outside can be reduced. ductor device [82] Difference with our invention: Wafer is heated on hot plate. No chilling is included. No air flow is used. [...]... section, an overview of the bake/ chill steps in microlithography is first described, followed by the discussion on the temperature effects on CD in microlithography 1.3.1 Bake/ Chill Steps in Microlithography Figure 1.1 illustrates the typical steps in a microlithography process [7] It can be seen that there are four steps involving baking They are: dehydration bake, soft bake, post exposure bake (PEB) and... effects of the microlithography process on CD control During the baking steps of microlithography, not only is the temperature uniformity at steady state important, but the temperature uniformity during transient will also affect the CD In the next section, an overview of the bake/ chill steps in the microlithography process and the temperature effects on CD are discussed Chapter 1 Introduction 1.3 3 Microlithography. .. process One possible solution for this problem is to integrate the bake/ chill steps into a single station With the integrated system, bake and chill can be carried out on the same plate More importantly, temperature control on the wafer is not interrupted because the handling of the wafer is minimized [26] In Schaper’s design [27][28], a thermal cycling unit for baking and chilling was developed The unit... to gain insights into the heat transfer to the wafer and to improve the wafer temperature uniformity, an exhaustive heat transfer analysis of the bake equipment was conducted by Ramanan [30] A lumped heat transfer model was also developed by Zhou [31] to simulate the transient response of the temperature on the wafer after being placed on the bake plate A collection of more detailed feature-based thermal... baking/chilling process In addition, high temperature uniformity across the wafer surface can be achieved Last but least, ease of integration is also one of the important advantages The above two fundamental conditions for uniform temperature are still valid in designing air flow baking system For example, uniform temperature near the wafer surface can be achieved by a proper chamber design, and constant... objectives, some of the challenges faced by the semiconductor industry, the temperature effects on the CD in microlithography process and methods to achieve uniform temperature distribution across the wafer surface Chapter 2 presents an overview of the state of art and related prior art for wafer bake and chill systems Chapter 3 shows the wind tunnel experimental results to demonstrate a proof of concept... as well as related prior arts on state of the art for wafer bake/ chill system used in microlithography process will be presented The objective is to evaluate the different technologies used in the current wafer bake/ chill system 2.1 State of the Art Thermal processes such as wafer baking and chilling during the Post Expo- sure Bake (PEB) are important steps in microlithography in the semiconductor industry... to chilling plates by some mechanical means Figure 2.1 shows two examples of track machines with the hot plate baking/chilling systems Figure 2.1(a) shows a baking/chilling system with several hot plates and chilling plates placed in a row Figure 2.1(b) shows a more advanced system with several layers of plates stacked inside its cabinets (a) (b) Figure 2.1: Track systems used in semiconductor manufacturing... However, the configuration and control of the large number of heater cartridges is a complicated problem yet to be resolved Chapter 2 Overview Of Wafer Bake/ Chill System For Microlithography 21 4 The temperature transient response is slow because of the large thermal mass of the hot plate 5 The wafer temperature control is lost during transfers from the hot plate to the chill plate 6 Mechanically moving the... time and increasing product diversity [1] The most obvious challenge is the increasing capital cost The increasing rate of the capital cost is faster than that of revenues Currently, the cost of setting up a plant for chip manufacturing is nearly $10 billion, and more than 60% of this cost can be attributed to equipment [2] In order to reduce the impact of the roaring cost, larger wafers are used and . Founded 1905 DEVELOPMENT OF AN INTEGRATED BAKE/ CHILL SYSTEM FOR MICROLITHOGRAPHY WANG LAN (M.Sc., M.Eng., B.Eng.) A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY DEPARTMENT OF ELECTRICAL. UNIVERSITY OF SINGAPORE 2008 Summary In this thesis, an integrated bake/ chill system for microlithography process using a stream of air is introduced. This system has the ability to deliver uniform temperature. that of soft bake: the evaporation of solvents to harden the resist and to achieve goo d adhesion of the resist to the wafer surface [9]. As in the soft bake, the temperature and time ranges for