High k MOSFETS with high mobility channels

HIGH-К MOSFETS WITH HIGH MOBILITY CHANNELS HUANG JIDONG (B. Sc., Jilin Univ., CHINA and M.Sc., NUS, SINGAPORE) A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY DEPARTMENT OF MECHANICAL ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2007 ACKNOWLEDGMENTS I would like to express my heartfelt gratitude and sincere appreciation to my supervisors, Dr. Chunxiang Zhu (Department of Electrical and Computer Engineering), and Professor Andrew A. O. Tay (Department of Mechanical Engineering), who have led me into this exciting area of microelectronics, and have offered me continuous encouragement, advice and support throughout this research project. I would like to thank Dr. Celine Wong and Dr. Vaidyanathan Kripesh from the Institute of Microelectronics, and Dr. Yongwei Zhang (Department of Material Science) for their helpful advice and guidance during the first year of my PhD study. My gratitude also goes to Dr. Minghui Hong, Guoxin Chen, Dr. Wendong Song from the Laser Microprocessing Lab for their great help on laser annealing; and Dr. Zhi-Yuan Cheng from the AmberWave System Corp. (U.S.A.), Dr. Mingbin Yu from the Institute of Microelectronics (Singapore) for their warm cooperation on substrate preparation. I gratefully acknowledge my lab fellows for their valuable discussion and help on research, learning, and many other aspects in life during the past four years: Nan Wu, Qingchun Zhang, Xiongfei Yu, Chi Ren, Rui Li, Sung Jin Whang, Moon Sig Joo, Jinghao Chen, Sung Jung Kim, Yingqian Wang, Chen Shen, Xinpeng Wang, Jingde Chen, Fei Gao,Yan Song, Rinus Tek-Po Lee, Kian Ming Tan, Wan Sik Hwang, Andy Eu-Jin Lim, Zerlinda Tan, Chia Ching Yeo, Debora Poon, Samanta Santanu Kumar, Eric Yeow-Hwee Teo, Jia Fu, Wei He, Gang Zhang, Yi Tong, Jing Pu, Hoon-Jung Oh, Yu Fu Yong, Patrick Tang, Wai Linn O-Yan, Boon Tech Lau and many others from the Silicon Nano Device Lab; and Audrey Chng, Chun Deng, Aiping Tan, Ebin Liao, Manyi Pan, Bing I Zhao, Guojun Hu, Vempati Srinivasa Rao, Katta Mohan Kumar, Zhengjun Xue, Jie Gu, Wei Sun, Kim Shyong Siow, Arthur Kin Mun Kwok etc. in the Nano/Micro Systems Integration Lab. In particular, I wish to express my sincere thanks to Nan Wu, Qingchun Zhang and Xiongfei Yu, for their innumerable helpful discussion and constructive suggestions on device fabrications, characterizations as well as data analyses in this project. The financial support from the National University of Singapore Nanoscience and Nanotechnology Initiative (NUSNNI) is also gratefully acknowledged. Finally, I want to thank my parents for their love, constant support and encouragement in all of my life. II CONTENTS ACKNOWLEDGMENTS I CONTENTS . III SUMMARY V List of Figures and Tables VII List of Symbols and Abbreviations .XI Chapter I Introduction . 1.1 Improvement of MOSFET performance 1.2 Scaling limit for traditional gate dielectric SiO2 1.3 Alternative high-к gate dielectrics . 10 1.4 Channel carrier mobility enhancement 14 1.4.1 Strain-induced mobility enhancement . 14 1.4.1.1 The piezoresistance effect . 15 1.4.1.2 Strain-induced energy-band structure modification . 16 1.4.1.3 Effect of strain type and stress direction on carrier mobility enhancement 19 1.4.1.4 Approaches to introduce strain in the carrier channel 20 1.4.2 Channel materials with high intrinsic carrier mobility 25 1.5. Literature review and objective of this study 27 1.5.1 High-к gate dielectrics with substrate strain channel materials 27 1.5.2 High-к gate dielectrics with germanium substrate . 29 1.5.3 Scope of this study 30 References 32 Chapter II Device fabrication and characterization 38 2.1 Fabrication process of MOSFET . 38 2.1.1 A typical fabrication process of MOSFET 38 2.1.2 Substrate structures . 45 2.1.3 Thin film techniques for high-к dielectrics and metal gate deposition . 47 2.1.4 Source and drain activation 50 2.2 Characterizations of MOSFET 52 2.2.1 Physical properties . 52 2.2.2 Electrical properties . 55 References 58 Chapter III Strained Si0.5Ge0.5 MOS capacitors with MOCVD HfO2 as gate dielectric . 59 3.1 Introduction . 59 3.2 Experiment details 60 III 3.3 Results and discussion 61 3.4 Summary . 67 References 68 Chapter IV Strained Si0.5Ge0.5 MOS capacitors with MOCVD HfAlO as gate dielectric 70 4.1 Introduction . 70 4.2 Experiment details 71 4.3 Results and discussion 72 4.4 Summary . 79 References 80 Chapter V Strained Si0.6Ge0.4 pMOSFETs with ALD HfO2 as gate dielectric 82 5.1 Introduction . 82 5.2 Experiment details 83 5.3 Results and discussion 84 5.4 Summary . 96 References 97 Chapter VI Germanium nMOSFETs with n+/p junctions activated by laser annealing . 99 6.1 Introduction . 99 6.2 Experiment details 100 6.3 Results and discussion 101 6.3.1 Ge n+/p junction . 101 6.3.2 Ge nMOSFET 108 6.4 Summary . 112 References 114 Chapter VII Conclusions 117 7.1 Conclusions 117 7.2 Recommendations for future study . 119 Appendix I: List of Publications . i IV SUMMARY Application of high mobility channel materials and high permittivity (high-к) gate dielectrics in metal-oxide-semiconductor field effect transistor (MOSFET) are of great interest to the modern semiconductor industry for further improvement of the performance of integrated circuits. This dissertation consists of two parts: i) integration of high-к gate dielectrics, HfO2 or HfAlO, on high hole mobility compressive strainedSiGe (ε-SiGe) surface channel for pMOSFET; and ii) demonstration of high electron mobility pure germanium channel nMOSFET with HfO2 as gate dielectric and source/drain (S/D) dopants activated by laser annealing (LA). Following the first introductory chapter, a detailed description of typical MOSFET fabrication process and a brief introduction of techniques for characterization of physical and electrical properties of the devices in this study are presented in chapter II. Chapters III, IV and V deal with the first part of this dissertation. The interfacial and electrical properties of metal organic chemical vapor deposition (MOCVD) HfO2 and HfAlO on compressively ε-Si0.5Ge0.5 substrate without or with surface rapid thermal nitridation (RTN) treatment were investigated. Both TaN/HfO2/ε-Si0.5Ge0.5 and TaN/HfAlO/ε-Si0.5Ge0.5 capacitors with RTN showed superior capacitance-voltage (C-V) and current-voltage (I-V) characteristics compared to the capacitors without RTN. However, RTN treatment resulted in hole mobility degradation for TaN/HfO2/ε-Si0.6Ge0.4 pMOSFET with atomic layer chemical vapor deposition (ALD) HfO2 as gate dielectric. The effective hole mobility of the devices without or with RTN was showed to be V respectively ~30% higher or ~10% lower than that of Si control at linear effective field region. In the second part of this dissertation, formation of germanium n+/p junction by phosphorous implantation and subsequent LA is demonstrated as shown in chapter VI. After being irradiated at a laser energy fluence of 0.16 J /cm2 with two successive pulses, the germanium n+/p junction exhibits a sheet resistance of ~50 Ohm/sq for the n+ region, a comparable I-V characteristic, and much less phosphorus dopant diffusion in comparison with those formed by rapid thermal process (RTP) annealing. Moreover, a gate-first self-aligned Al/TaN/HfO2/Ge nMOSFET with S/D activated by LA at a fluence of 0.22 J /cm2 with one pulse was showed to give small S/D resistance and good gatestack integrity simultaneously. It also has a larger drive current, a lower threshold voltage and a higher electron mobility at high effective field than those of the device with RTP annealing. Finally, the conclusions drawn from this PhD research are summarized. A few of recommendations for future study are also suggested. VI List of Figures and Tables Figure 1.1 Schematic illustration of a submicron channel length complimentary MOSFET (CMOSFET). Figure 1.2 A typical chip cross-section illustrating hierarchical scaling methodology (after the 1999 Semiconductor Industry Association (SIA) roadmap). Figure 1.3 Sketch of a typical MOSFET structure on a bulk (B) substrate, in which L and W represent the channel length and width, respectively. When the carrier channel is in inverted state with a voltage applied on the gate (G), carriers can flow from the source (S) to drain (D) forming the drive current of transistor. Figure 1.4 The gate leakage current density limit (Jg limit) versus the expected value of the gate leakage current density from the simulations (Jg, simulated) for high-performance logic (after IRTS 2005 [1.1]). EOT curves of planar bulk, fully depleted silicon-oninsulator (FDSOI) and dual-gate (DG) MOSFETs are also plotted for reference. Figure 1.5 Variation of dielectric constant with band gap of high-к materials (after [1.3]). 10 Figure 1.6 Energy-band diagram of an idea metal-insulator-semiconductor (MIS) structure, in which φM represents the work function of metal; φB , the electron barrier height from 11 metal to oxide; ∆EC and ∆EV , the conduction and valence band offset between semiconductor and dielectric; EC , EV , E g , EF , Ei ,ψ B , and χ are the conduction band edge, valence band edge, bandgap, Fermi level, intrinsic Fermi level, energy level between Fermi and intrinsic Fermi level, and electron affinity of semiconductor, respectively. Figure 1.7 Predicted band offsets for various high-к dielectric materials (after [1.3]). 12 Figure 1.8 Biaxial tensile strain-induced Si conduction band splitting in k-space (adapted from [1.7][1.8]) 17 Figure 1.9 Biaxial compressive strain-induced Si1-xGex valence bands splitting in k-space (after [1.9]). HH, LH and SO represent the heavy-hole band, light-hole band and spin-off band, respectively. 18 Figure 1.10 The effect of various stress on electron and hole mobility in channel on (001) silicon wafer (adapted from [1.11] [1.12]) 19 Figure 1.11 Schematic diagrams of a) uniaxial package strain produced by four-point bending method (adapted from [1.13]), and b) biaxial package strain by displacement of the center of wafer (adapted from [1.14]). 20 Figure 1.12 Schematic features of the various process strain (adapted from [1.8]): (a) silicon nitride capping layer to create a tensile channel, (b) STI to create a compressive channel, (c) silicide strain and (d) embedded SiGe S/D process strain to created a compressive strain. 21 Figure 1.13 A schematic diagram of lattice arrangement of Si1− x Gex / Si1− y Ge y (with x> y) 24 VII epitaxially grown on Si, and the corresponding band alignment (after [1.8] [1.19]). Figure 1.14 A schematic diagram of lattice arrangement of Si layer epitaxially grown on a relaxed SiGe layer and the corresponding band alignment (after [1.8] [1.19]). 24 Figure 2.1 A sketch of single mask ring-shaped MOSFETs with channel length of 20µm and width of 100µm, where G, S and D presenting gate, source and drain regions, respectively. A typical fabrication process flow of MOSFET in this project. 39 Figure 2.3 Schematics diagram of two kinds of ε-SiGe substrate structures in this project with corresponding energy band alignment. 46 Figure 2.4 A schematic sketch of the laser annealing experimental setup. 52 Figure 2.5 A schematic sketch of spectroscopic ellipsometer. 53 Figure 2.6 A schematic sketch of X-ray photoelectron spectroscopy. 54 Figure 2.7 Sample of irregular sharp with four contacts at arbitrary places along the circumference. 55 Figure 2.8 Comparison of effective electron mobility among universal curve, Si control and tensile strained Si channel nMOSFET with SiO2 as gate dielectric. 57 Figure 3.1 XPS data of (a) Ge 2p3/2 and (b) Si 2p3/2 spectra for a DHF-cleaned ε-Si0.5Ge0.5 substrate [curves (i)] and a DHF-cleaned ε-Si0.5Ge0.5 substrate with subsequent deposition of a layer of ~10Å HfO2 film by MOCVD without [curves (ii)] or with [curves (iii)] PDA at 600 ºC for 30 seconds. 62 Figure 3.2 XPS data of (a) Ge 2p3/2 and (b) Si 2p3/2 spectra for a DHF-cleaned ε-Si0.5Ge0.5 substrate [curve (i)], a DHF-cleaned ε-Si0.5Ge0.5 substrate with surface RTN treatment [curve (iv)], and a DHF-cleaned ε-Si0.5Ge0.5 substrate with RTN and subsequent deposition of a layer of ~10 Å HfO2 film by MOCVD without [curve (v)] or with [curve (vi)] PDA at 600 ºC for 30 seconds. The inset shows N 1s spectrum of the substrate with surface nitridation and a thin layer of HfO2 film [curves (v)]. 64 Figure 3.3 C-V characteristics (100-kHz) of the TaN/HfO2/ε-Si0.5Ge0.5 MOS capacitor without (solid line with open square) and with (solid line with open circle) surface nitridation treatment prior to HfO2 deposition. The physical thickness of HfO2 measured by an ellipsometer is ~82Å. 65 Figure 3.4 I-V characteristics of the TaN/HfO2/ε-Si0.5Ge0.5 MOS capacitor without (solid line with open square) and with (solid line with open circle) RTN prior to HfO2 deposition. 66 Figure 4.1 XPS data of (a) Ge 2p3/2 and (b) Si 2p3/2 spectra for DHF-cleaned ε-Si0.5Ge0.5 substrate [curve (i)] and DHF-cleaned ε-Si0.5Ge0.5 substrate with subsequent deposition of a layer of ~15Å HfAlO film without [curve (ii)] or with [curve (iii)] PDA at 600 ºC for 30 seconds. The inset shows Al 2p3/2 spectrum of the substrate with a thin layer of HfAlO film without PDA [curve (ii)]. 73 Figure 4.2 XPS data of (a) Ge 2p3/2 and (b) Si 2p3/2 spectra for DHF-cleaned ε-Si0.5Ge0.5 substrate [curve (i)], DHF-cleaned ε-Si0.5Ge0.5 substrate with surface nitridation treatment [curve (iv)], and DHF-cleaned ε-Si0.5Ge0.5 substrate with surface nitridation 74 Figure 2.2 45 VIII treatment and subsequent deposition of a layer of ~15 Å HfAlO film without [curve (v)] or with [curve (vi)] PDA at 600 ºC for 30 seconds. The inset shows N 1s spectrum of the substrate with surface nitridation and a thin layer of HfAlO film without PDA [curve (v)]. Figure 4.3 XPS data of (a) Al 2p3/2 and (b) Hf 4f spectra for DHF-cleaned ε-Si0.5Ge0.5 substrate with subsequent deposition of a layer of ~15Å HfAlO film without [curve (i)] or with [curve (ii)] PDA at 600 ºC for 30 seconds, and DHF-cleaned ε-Si0.5Ge0.5 substrate with surface nitridation treatment and subsequent deposition of a layer of ~15 Å HfAlO film without [curve (iii)] or with [curve (iv)] PDA at 600 ºC for 30 seconds. 75 Figure 4.4 C-V characteristics (100-kHz) of the TaN/HfAlO/ε-Si0.5Ge0.5 MOS capacitor without (solid line with open square) and with (solid line with open circle) RTN prior to HfAlO deposition. 76 Figure 4.5 EOT dependence of gate leakage currents at Vg = VFB-1V for the TaN/HfAlO/εSi0.5Ge0.5 MOS capacitor without (solid triangles) or with (solid squares) RTN prior to HfAlO deposition. The inset shows dependence of EOT on HfAlO physical thickness for both samples. 78 Figure 5.1 5.1. XPS data of (a) Ge 2p3/2 and (b) Si 2p3/2 spectra for a DHF-cleaned ε-Si0.6Ge0.4 substrate [curve (i)] and a DHF-cleaned ε-Si0.6Ge0.4 substrate with subsequent deposition of a layer of ~10Å HfO2 film by ALD without [curve (ii)] or with [curve (iii)] PDA at 600 ºC for 30 seconds. 85 Figure 5.2 5.2. XPS data of (a) Ge 2p3/2 and (b) Si 2p3/2 spectra for a DHF-cleaned ε-Si0.6Ge0.4 substrate [curve (i)], a DHF-cleaned ε-Si0.6Ge0.4 substrate with surface RTN treatment [curve (iv)], and a DHF-cleaned ε-Si0.6Ge0.4 substrate with RTN and subsequent deposition of a layer of ~10 Å HfO2 film by ALD without [curve (v)] or with [curve (vi)] PDA at 600 ºC for 30 seconds. 86 Figure 5.3 5.3. EOT and gate leakage current as a function of the PMA condition. The εSi0.6Ge0.4 samples with RTN show better thermal stability than that without RTN. 87 Figure 5.4 5.4. I-V characteristics of Boron implanted p+/n junctions of ε-Si0.6Ge0.4 samples with PMA at 650 ºC 50 seconds or 850 ºC 15 seconds. The later condition gives about one order magnitude lower of Ioff for all samples. 89 Figure 5.5 5.5. Split C-V characteristics of TaN/HfO2/ε-Si0.6Ge0.4 pMOSFETs without or with RTN, with PMA at 850 ºC for 15 seconds. 90 Figure 5.6 5.6. (A) output and (B) transfer characteristics of TaN/HfO2/ε-Si0.6Ge0.4 pMOSFETs without or with RTN, with PMA at 850 ºC for 15 seconds. 91 Figure 5.7 5.7. Charge pumping current for Si control, and ε-Si60Ge40 pMOSFET without or with RTN, with PMA at 850 ºC 15 s as function of base level of gate pulse. 93 Figure 5.8 5.8. XPS data of (a) Ge 2p3/2 and (b) Si 2p3/2 spectra for a DHF-cleaned ε-Si0.6Ge0.4 substrate [curve (i)] and a DHF-cleaned ε-Si0.6Ge0.4 substrate with subsequent deposition of a layer of ~10Å HfO2 film by MOCVD without [curve (vii)] or with [curve (viii)] PDA at 600 ºC for 30 seconds. 93 Figure 5.9 5.9. Comparison of effective hole mobility among Si control, and ε-Si60Ge40 pMOSFET without or with RTN, with PMA at 850 ºC 15 seconds. 95 IX CHAPTER VI: Germanium nMOSFETs with n+/p junctions activated by laser annealing. the number of successive irradiation pulses (see Fig. 6.3) from 3.9Å (as-implanted) to 47.0Å after pulses, and to 71.2Å after 10 pulses. A similar trend was observed by McCulloch and Brotherton [6.11] who found that the surface roughening mechanism was governed by the total number of pulses incident on the sample surface when the laser fluence was above the melt threshold of the semiconductor. Hence we believe that melting occurred on the Ge surface which resulted in a similar melting-induced step-like dopant profile (see Fig. 6.2). This is possible since the melting temperature of Ge (937 ºC) is much lower than that of Si (1415 ºC). The change of substrate surface morphology is probably due to the recrystallinzation of Ge implant-induced amorphous layer after laser anneal. Moreover, the increase of surface roughness increases the total energy absorbed through the sample surface, causing a deeper melting depth on the sample surface [6.10]. Consequently, the dopant profile advanced deeper upon successive pulses. Nevertheless, the diffusion of the dopants in substrates annealed by LA was much less severe in comparison with that by RTA, which indicates that LA is a promising activation/annealing technique for shallow junction formation. For instance, after RTA at 650 ºC for 10 s, a diffusion depth of ~100 nm was observed [6.12] by SIMS for phosphorus dopants implanted in Ge at 18 keV with a dose of 4×1015 cm-2, while for our substrate annealed by LA at a fluence of 0.16 J/cm2 with two pulses, the diffusion depth was only ~10 nm (see Fig. 6.2). The inset of Fig. 6.2 (b) shows the SIMS dose measured on the substrates annealed by LA at a fluence of 0.16 J/cm2 with different successive pulses. It is evident that serious dopant loss occurred with increasing pulse number, especially after more than two successive pulses (>50% dopant loss at 10 pulses). This is consistent with the results in Fig. 6.1 that dopant out-diffusion from the sample caused 106 CHAPTER VI: Germanium nMOSFETs with n+/p junctions activated by laser annealing. the Rs to increase when the sample was subjected to more than two successive pulses with sufficient fluence as shown in Fig. 6.1. A typical I-V characteristic curve of the Ge n+/p junction with an area of 100×100 µm2 formed by LA at a fluence of 0.16 J/cm2 with two successive pulses is shown in Figure 6.4. The as-implanted sample and the junction formed by RTA (5 minutes at 500 o C) were also characterized for comparison. A good rectifying diode characteristic was achieved for the n+/p junction on a Ge substrate annealed by LA which was comparable with that formed by RTA. 10 Junction Current (A/cm ) 10 10 -1 10 -2 10 -3 10 -4 10 as-implanted o RTA(500 C 5min) LA(0.16J/cm 2pulses) -5 10 -1.0 -0.5 0.0 0.5 1.0 Junction Voltage (V) FIG. 6.4. I-V characteristics of phosphorous-implanted Ge-n+/p junctions without annealing and with annealing by RTA or LA. RTA was performed at 500 ºC for minutes on substrate with phosphorus implanted at 50 keV with a dose of 5×1015 cm-2. 107 CHAPTER VI: Germanium nMOSFETs with n+/p junctions activated by laser annealing. 6.3.2 Ge nMOSFET It was reported that high-к/germanium stack has a poor thermal stability. A significant flat band shift toward the positive direction was commonly observed with various high-к materials (Ge oxynitride, Al2O3, HfO2) after post metal annealing (PMA) [6.2] [6.13] [6.14]. Fig. 6.5 (a) shows the EOT and flat band voltage changed after RTA at 400-600oC for 30 seconds. Although the EOT values did not change after RTA, the positive Vfb shift started to occur at 500oC, with a higher temperature RTA giving rise to a dramatic increasing of Vfb (∆Vfb=1.68V for RTA at 600oC). The positive Vfb shift is speculated due to germanium out-diffusion into the gate dielectric which introduces additional negative fixed charges [6.14]. These negative fixed charges result in an unacceptably high threshold voltage and may degrade electron mobility due to strong coulomb scattering effects. 2.0 (b) LA 2.0 1.5 EOT (nm) 1.5 1.0 1.0 0.5 0.5 EOT (nm) 1.8 Al/TaN gate fail TaN gate 0.6 1.6 0.4 1.4 1.2 Vfb (V) (a) RTA Vfb (V) 2.0 0.2 1.0 0.8 0.0 400 450 500 550 o Temperature ( C) 600 0.0 0.16 0.20 0.24 0.28 0.32 0.0 0.36 Energy (J/cm2) FIG. 6.5. EOT and flatband voltage variations of Ge nMOS capacitors after (a) RTA and (b) LA. 108 CHAPTER VI: Germanium nMOSFETs with n+/p junctions activated by laser annealing. To evaluate the thermal stability of high-к gate stack upon LA, Ge MOS capacitors with TaN or Al/TaN gate electrodes were prepared and subjected to LA. Fig. 6.5 (b) shows the EOT and flat band voltage changes after LA with different energy fluence for one pulse. The device with TaN gate electrode shows poor thermal stability with LA. When the laser energy is larger than 0.2 J/cm2, the device failed to work due to the deformation of the TaN gate which was observed under a high magnification microscope. In contrast, device with Al/TaN gate electrode shows superior gate stack integrity after LA. No EOT and flat band variation was observed after LA up to 0.34 J/cm2. The good thermal stability of devices with an Al/TaN gate electrode is due to the higher reflectivity of Al with a 248-nm laser than for the device with a TaN gate electrode (92% versus 69%). Therefore, much less energy is absorbed in the Al/TaN gate stack, and the S/D regions are selectively heated [6.17]. 200 LA with pulse Rs (ohm/sq) 150 100 Minimum Rs by RTA 50 Optimized fluence 0.15 0.20 0.25 0.30 0.35 Energy (J/cm ) FIG 6.6. The effects of laser energy fluence with single pulse on sheet resistance of phosphorous-implanted Ge substrates. Also shown are the minimum sheet resistances achieved by RTA. 109 CHAPTER VI: Germanium nMOSFETs with n+/p junctions activated by laser annealing. Since the Ge nMOSFET with Al/TaN gate keeps good thermal stability with LA fluence as high as 0.34 J/cm2, laser fluence higher than the values applied in the previous study of Ge n+/p junctions have been tried on the transistor study. The effects of laser fluence with single pulse on Rs of Ge substrates are shown in Fig. 6.6. Unlike the situation with the lower irradiation energy (see Fig. 6.1), it was found that irradiation energy higher than 0.20 J/cm2 is capable of giving low Rs values with a single pulse, and a higher fluence shows a lower Rs and a deeper junction. Considering the tradeoff between a shallow junction depth and a low Rs, an energy fluence of 0.22 J/cm2 was found to be an optimized LA condition with a junction depth of 96 nm and a Rs value of 57Ω/square for S/D activation in Ge nMOSFET [6.18]. Fig. 6.7 (a) shows the output characteristics of Ge nMOSFETs with RTA (450ºC 30 seconds) and LA (0.22 J/cm2 with pulse) activation. The device with RTA activation shows a slow saturation behavior due to large S/D serious resistance, while the LA device offers a well-behaved Id-Vd characteristic. In addition, the LA device exhibits larger saturation current than the RTA device (1.64µA/µm versus 1.47µA/µm @ VgVth=0.5 V). Fig. 6.7 (b) shows the transfer curve of the device with LA. The threshold voltage was extracted to be 0.54 V, which is 0.19 V lower than the one with RTA activation (0.73 V). This is consistent with our previous discussion that high temperature RTA resulted in additional negative fixed charges and, hence, a high threshold voltage. By implementing LA, due to the selective heating, the flat band shift problem can be successfully eliminated and a low threshold voltage can be achieved. 110 CHAPTER VI: Germanium nMOSFETs with n+/p junctions activated by laser annealing. I (µA/µm) 2.0 |Vg-Vth|=0~0.5V step=0.1V 1.5 L=20um (a) 1.0 0.5 LA RTA 0.0 0.0 0.2 0.4 0.6 Vd (V) 0.8 1.0 10 I (µA/µm) 10 nMOSFET L=20µ Vd= -1 10 Vd= 0.025V -2 10 (b -3 10 0. 0. 1. 1. Vg FIG. 6.7. (a) Output and (b) transfer characteristics of a Ge nMOSFET with S/D activated by LA. The output curve of device activated by RTA was also included in (a) as a Figure 6.8 shows the electron mobility as a function the effective electrical field of Ge nMOSFETs with S/D activated by LA or RTA. The electron mobility of Si control device is also shown for comparison. An increased electron mobility in the high effective electrical field region is observed in the device with LA, which attributed to the reduced 111 CHAPTER VI: Germanium nMOSFETs with n+/p junctions activated by laser annealing. series resistance. Compared with the HfO2/Si device, the Ge nMOSFET shows 175% peak electron mobility. FIG. 6.8. Extracted electron mobility as a function of the effective electrical field for Ge nMOSFETs with S/D activated by LA or RTA. 6.4 Summary The electrical characteristics of Ge n+/p junction activated by LA, and Ge nMOSFET with S/D activated by LA have been studied. It was demonstrated that steplike dopant profiles were formed with dopant atoms extending deeper upon increased laser energy fluence and successive pulse number in germanium. After being irradiated at a laser energy fluence of 0.16 J /cm2 with two successive pulses, the Ge n+/p junction exhibits a sheet resistance of ~50 Ohm/sq in the n+ region, a comparable current-voltage characteristic, and much less phosphorus dopant diffusion in comparison with those formed by RTA. For the first time, a gate-first self-aligned Ge nMOSFET with metal gate 112 CHAPTER VI: Germanium nMOSFETs with n+/p junctions activated by laser annealing. and MOCVD HfO2 as gate dielectric has been fabricated with dopant activated by LA. By applying an Al laser reflector on the TaN gate, the S/D regions are selectively annealed without heating the gate stack. Small S/D resistance and good gate-stack integrity are achieved simultaneously. With these benefits, a larger drive current, a lower threshold voltage, and a higher electron mobility at high effective electrical field are achieved in a Ge nMOSFET with an LA activation than with an RTA activation. 113 CHAPTER VI: Germanium nMOSFETs with n+/p junctions activated by laser annealing. References [6.1] S. M. Sze, Physics of Semiconductor Devices (Wiley, New York) 2nd ed., pp. 849 (1981). [6.2] H. Shang, K. L. Lee, P. Kozlowski, C. D. Emic, I. Babich, E. Sikorski, M. Ieong, H. S. P. Wong, K. Guarini, and W. Haensch, “Self-aligned n-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric and tungsten gate,” IEEE Electron Device Lett. 25, pp.135-137 (2004). [6.3] C. Jasper, L. Rubin, C. Lindfors, K. S. Jones, and J. Oh, “Electrical activation of implanted single crystal germanium substrates,” IEEE Proceedings of the 14th International Conference on Ion Implatation Technology, pp.548-551 (2002). [6.4] C. O. Chui, L. Kulig, J. Moran, W. Tsai, and K. C. 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[6.9] Y. F. Chong, K. L. Pey, A. T. S. Wee, A. See, L. Chan, Y. F. Lu, W. D. Song, and L. H. Chua, “Annealing of ultrashallow p+/n junction by 248 nm excimer laser and rapid thermal processing with different preamorphization depths,” Appl. Phys. Lett. 76, pp.3197-3199 (2000). [6.10] C. H. Poon, B. J. Cho, Y. F. Lu, M. Bhat, and A. See, “Multiple-pulse laser annealing of preamorphized silicon for ultrashallow boron junction formation,” J. Vac. Sci. Technol. B, 21, pp.706-709 (2003). [6.11] D. J. McCulloch and S. D. Brotherton, “Surface roughness effects in laser crystallized polycrystalline silicon,” Appl. Phys. Lett. 66, pp.2060-2062 (1995). [6.12] C. O. Chui, K. Gapalakrishnan, P. B. Griffin, J. D. Plummer, and K. C. Saraswat, “Activation and diffusion studies of ion-implanted p and n dopants in germanium,” Appl. Phys. Lett. 83, pp.3275-3277 (2003). [6.13] J. J.-H. Chen, N. A. Bojarczuk, Jr., H. Shang, M. Copel, J. B. Hannon, J. Karasinski, E. Preisler, S. K. Banerjee, and S. Guha, “Ultrathin Al2O3 and HfO2 gate dielectrics on surface-nitrided Ge,” IEEE Trans. Electron Devices, vol. 51, no. 9, p. 1441-1447 (2004). [6.14] W. P. Bai, N. Lu, and D.-L. Kwong, “Si interlayer passivation on germanium MOS capacitors with high-κ dielectric and metal gate,” IEEE Electron Devices Lett., vol. 26, no. 6, pp. 378-380 (2005). 115 CHAPTER VI: Germanium nMOSFETs with n+/p junctions activated by laser annealing. [6.15] Q. C. Zhang, N. Wu, D. M. Y. Lai, Y. Nikolai, L. K. Bera, and C. Zhu, “Germanium incorporation in HfO2 dielectric on germanium substrate,” J. Electrochem. Soc., vol. 153, no. 3, p. G207 (2006). [6.16] Q. C. Zhang, N.Wu, L. K. Bera, and C. Zhu, “Germanium out-diffusion in HfO2 and its impact on electrical properties,” in Proc. SSDM Tech. Dig., 2005, pp. 1– 14. [6.17] S. Baek, S. Heo, H. Choi, and H. Hwang, “Characteristics of HfO2 pMOSFET prepared by B2H6 plasma doping and KrF excimer laser annealing,” IEEE Electron Devices Lett., vol. 26, no. 3, pp. 157–159 (2005). [6.18] Qingchun Zhang, Jidong Huang, Nan Wu, Guoxin Chen, Minghui Hong, L. K. Bera, and Chunxiang Zhu, “Drive-current enhancement in Ge n-channel MOSFET using laser annealing for source/drain activation,” IEEE Electron Devices Lett., vol. 27, no. 9, pp. 728–730 (2006). 116 CHAPTER VII: Conclusions Chapter VII Conclusions 7.1 Conclusions Following the trend known as Moore’s law, the shrinking of transistor feature size has resulted in the traditional silicon-based integrated circuits technology approaching its fundamental limits today. Both high mobility channel materials and high-к gate dielectrics for MOSFET have been considered and even adopted in the modern semiconductor industry as key solutions to overcome the limitations. This dissertation consists of two parts following the above-mentioned approaches: i) integration of high-к gate dielectrics, HfO2 or HfAlO, on high hole mobility compressive ε-SiGe surface channel for pMOSFET; ii) demonstration of high electron mobility pure germanium channel nMOSFET with HfO2 as gate dielectric and S/D dopants activated by laser annealing (LA). In the first part of this dissertation, the interfacial and electrical properties of MOCVD HfO2 and HfAlO on compressively ε-Si0.5Ge0.5 substrate without or with surface rapid thermal nitridation (RTN) treatment were investigated. It was shown that an interfacial layer containing GeOx for HfO2 as gate dielectric, or GeOx and Al silicate for HfAlO as gate dielectric, existed on the substrates with direct deposition of the dielectrics, whereas an interfacial layer containing SiNxOy existed on the substrates with RTN prior to dielectrics deposition. The TaN/HfO2/ε-Si0.5Ge0.5 capacitor with RTN showed good capacitance-voltage characteristics with negligible hysteresis, much smaller interface trap 117 CHAPTER VII: Conclusions charge density and significantly improved gate leakage current in comparison with capacitors without RTN. Similarly, the TaN/HfAlO/ε-Si0.5Ge0.5 capacitor with RTN showed a larger permittivity of the entire gate dielectric with a thinner interfacial layer in terms of EOT, a smaller interface trap charge density, less severe flat-band shift as well as a two orders of magnitude lower gate leakage in comparison with those capacitors without RTN. However, it was shown that RTN results in hole mobility degradation for TaN/HfO2/ε-Si0.6Ge0.4 pMOSFET with ALD HfO2 as gate dielectric. The effective hole mobility of the devices without or with RTN was shown to be respectively ~30% higher or ~10% lower than that of Si control at the linear effective field region. Nevertheless, the device with RTN showed better thermal stability including a simultaneous reduction of EOT and gate leakage (and therefore a higher breakdown field), and a more negative threshold voltage as well as a larger density of interface states as compared to those devices without RTN. In the second part of this dissertation, the formation of germanium n+/p junction by phosphorous implantation and subsequent LA was demonstrated. It was observed that step-like dopant profiles were formed with dopant atoms extending deeper upon increased laser energy fluence and successive pulse number. After being irradiated at a laser energy fluence of 0.16 J /cm2 with two successive pulses, the germanium n+/p junction exhibits a sheet resistance of ~50 Ohm/sq for the n+ region, a comparable current-voltage characteristic, and much less phosphorus dopant diffusion in comparison with those formed by RTP annealing. 118 CHAPTER VII: Conclusions For the first time, a gate-first self-aligned Al/TaN/HfO2/Ge nMOSFET with silicon passivation on germanium substrate, MOCVD HfO2 as gate dielectric and LA for S/D activation was fabricated. By depositing an aluminum layer on the TaN gate as a laser light reflector, the S/D regions are selectively annealed. The device activated by LA at a fluence of 0.22 J /cm2 with one pulse is shown to give small S/D resistance and good gate-stack integrity simultaneously. It also has a larger drive current, a lower threshold voltage and a higher electron mobility at high effective field than those of the device with RTP annealing. 7.2 Recommendations for future study Based on the conclusions drawn and challenges encountered during this study, the following recommendations are suggested for future studies. i) New surface passivation technique on ε-SiGe surface. From the first part of this dissertation (chapters III to V), it has been shown that the integration of CVD high-к oxide as gate dielectric on ε-SiGe surface channel gives rise to serious oxidation of the εSiGe surface. The main component of the oxidation products, GeOx is water soluble and unstable at temperatures higher than ~ 400ºC which causes degradation of device performance. Although RTN treatment on ε-SiGe surface prior to the high-к dielectrics deposition prevents the formation of GeOx thereby improving some performance characteristics of the ε-SiGe devices, their Dit values are still relatively high and effective hole mobilities are very limited. Therefore, new approaches to integrate high-к gate dielectric on ε-SiGe surface with better dielectric/carrier-channel interface quality can be 119 CHAPTER VII: Conclusions investigated. This could take the form of a new surface passivation process on ε-SiGe substrate. ii) Different S/D activation technique. With regard to the issue of germanium atoms out-diffusion from ε-SiGe substrate into gate dielectric that happens particularly during the PMA process with a relatively high thermal temperature and a longer duration for S/D dopant activation, a different S/D activation technique such as laser annealing could be explored and applied to the ε-SiGe device. In the second part of this dissertation, laser annealing has been shown to effectively prevent Ge atoms diffusion from the pure germanium substrate in Ge nMOSFET since the gate area is protected and the S/D area is selectively heated. By applying a similar approach on ε-SiGe pMOSFET, the VFB and Vth shift of the device caused by additional negative fixed charges due to germanium atoms out-diffusion from the ε-SiGe substrate into gate dielectric could be reduced. iii) Reliability issues. Besides development of new process technologies for high performance devices, reliability issues related to MOSFET with high mobility channel and high-к gate dielectric should be also studied in future, such as bias temperature instability. 120 Appendix I Appendix I: List of Publications [1] Jidong Huang, Jia Fu, Chunxiang Zhu, Andrew A. O. Tay, Mingbin Yu, “Effect of ammonia pre-treatment on the physical and electrical characteristics of compressively strained-Si0.6Ge0.4 surface channel pMOSFETs with TaN/HfO2 gate stack,” IEEE Transactions on Electron Devices (submitted). [2] Jia Fu, Jidong Huang, Mingbin Yu, and Chunxiang Zhu, “A gate-first self-aligned surface channel strained-Si0.78Ge0.22 pMOSFET with HfO2 as gate dielectric,” IEEE, Electron Device Letters (submitted). [3] Jidong Huang, Jia Fu, Chunxiang Zhu, Andrew A. O. Tay, Zhi-Yuan Cheng, Chris. W. Leitz, and Anthony Lochtefeld, “A study of compressively strained Si0.5Ge0.5 metal-oxide-semiconductor capacitors with CVD HfAlO as gate dielectric,” Applied Physics letters, 90, pp. 023502 (2007). [4] Xiongfei Yu, Jidong Huang, Mingbin Yu, and Chunxiang Zhu, “Effect of gate doping concentration on leakage current in n+ poly-Si/HfO2 and examination of leakage paths by conducting AFM, ” IEEE, Electron Device Letters, 28, pp.373-375 (2007) [5] Qingchun Zhang, Jidong Huang, N. Wu, Guoxin Chen, Minghui Hong, L. K. Bera, and Chunxiang Zhu, “Drive current enhancement in Ge n-channel MOSFET using laser annealing for source/drain activation, ” IEEE, Electron Device Letters, 27, pp.728-730 (2006). [6] Jidong Huang, N. Wu, Qingchun Zhang, Chunxiang Zhu, M.-F. Li, Andrew. A. O. Tay, Zhi-Yuan Cheng, Chris. W. Leitz, and Anthony Lochtefeld, “Surface NH3 anneal on strained Si0.5Ge0.5 for metal-oxide-semiconductor application with HfO2 as gate dielectric,” Applied Physics letters, 88, pp.143506 (2006). [7] Jidong Huang, N. Wu, Qingchun Zhang, Chunxiang Zhu, Andrew. A. O. Tay, Guoxin Chen, and Minghui Hong, “Germanium n+/p junction formation by laser thermal process,” Applied Physics letters, 87, pp.173507 (2005). [8] J. D. Huang, M. H. Kuok, H. S. Lim and S. C. Ng, “Velocity angular dispersion of surface and bulk acoustic modes in SrTiO3,” Journal of Applied Physics 94 (11), pp.7341-7344 (2003). [9] H. S. Lim, J. D. Huang, V. L. Zhang, M. H. Kuok, and S. C. Ng, “Evaluation of acoustic physical constants of LiNbO3 at hypersonic frequencies,” Journal of Applied Physics 93 (12), pp.9703-9708 (2003). i [...]... it is proposed to integrate high permittivity/dielectric-constant (high- к) gate dielectrics on Ge-rich compressively-strained SiGe channels with high hole mobility and pure germanium channels with both high electron and hole motilities, seeking to attain their advantages to improve MOSFET performance In this introductory chapter, the relationship between performance of MOSFETs and device physical parameters... 16 CHAPTER I: Introduction phonon-carrier scattering, increasing the electron low-field mobility Non-strained Strained kz Δ4 kz Δ2 Δ2 Δ4 ky kx ky kx Ec Δ6 Δ4 Degenerate Δ2 FIG 1.8 Biaxial tensile strain-induced Si conduction band splitting in k- space (adapted from [1.7][1.8]) II Hole mobility enhancement The hole mobility enhancement can be explained by the valence band structure modification induced... saturation drive current, a high mobility carrier channel, in addition to high- к gate dielectric, should be implemented into CMOS technology Increase of the channel carrier mobility is achievable by means of either applying strain in the channel to gain strain-induced mobility enhancement, or using new channel materials with higher intrinsic carrier mobility, or both 1.4.1 Strain-induced mobility enhancement... a dielectric with better thermal stability including higher crystallization temperature is desired There are some other aspects which need to be considered for selection of high- к gate dielectrics, such as: A) high- к dielectrics without low-lying ‘soft’ polar modes have advantages since device mobility degradation related to remote scattering of carrier by low frequency phonon modes in high- к dielectrics... metal-oxidesemiconductor field effect transistors (MOSFETs) (see Fig 1.1), are nowadays scaled down to submicron size with the gate length below 100nm and the gate insulator SiO2 thickness below 2nm [1.1] The SiO2 with such a thin physical thickness may not have the insulating properties required, and the gate threshold voltage will be significantly reduced with a decrease of channel length to under one... conventional gate insulator with high- к dielectrics, very likely by 2008, in order to increase the physical thickness of the gate insulator and prevent tunneling currents while retaining the electronic properties of an ultrathin SiO2 film to enhance the gate dielectric capacitance density Cinv FIG 1.4 The gate leakage current density limit (Jg limit) versus the expected value of the gate leakage current density... physical thickness of the dielectric, Vdie is the voltage drop across the dielectric, and m∗ is the electron effective mass in the dielectric Obviously, the leakage current increases exponentially with decreasing barrier height and the dielectric thickness Therefore, dielectric with larger ∆EC and ∆EV values to substrate is desirable However, as shown in Fig 1.5, the band gap values of many of the high- к... induced by bending a substrate directly or by bending a package substrate with semiconductor chips glued firmly on its surface The package strain can be applied uniaxially by one-end-bending method, or four-pointbending method as sketched in Fig 1.11 (a), or biaxially by producing displacement of the center of a wafer as sketched in Fig 1.11 (b) Package strain can be applied to both short and long-channel... value of the gate leakage current density from the simulations (Jg, simulated) for high- performance logic (after IRTS 2005 [1.1]) EOT curves of planar bulk, fully depleted silicon-oninsulator (FDSOI) and dual-gate (DG) MOSFETs are also plotted for reference 9 CHAPTER I: Introduction 1.3 Alternative high- к gate dielectrics A high- к dielectric must meet various requirements to act as a satisfactory alternative... essential that the value of permittivity should be high enough to justify the cost of change Figure 1.5 shows dielectric constants of some high- к materials versus their band gap values The к values of some materials, such as Y2O3 and Al2O3, are not really high enough as potential candidates FIG 1.5 Variation of dielectric constant with band gap of high- к materials (after [1.3]) Secondly, the band offset . permittivity/dielectric-constant (high- к) gate dielectrics on Ge-rich compressively-strained SiGe channels with high hole mobility and pure germanium channels with both high electron and hole motilities,. TaN/HfO 2 /ε-Si 0.6 Ge 0.4 pMOSFETs without or with RTN, with PMA at 850 ºC for 15 seconds. 90 Figure 5.6 5.6. (A) output and (B) transfer characteristics of TaN/HfO 2 /ε-Si 0.6 Ge 0.4 pMOSFETs without or with. HIGH- К MOSFETS WITH HIGH MOBILITY CHANNELS HUANG JIDONG (B. Sc., Jilin Univ., CHINA