Carbon rich silicon (si1 ycy)for defect engineering of ion implantation damage in devices activated by solid phase epitaxy

CARBON RICH SILICON, Si1-yCy, FOR DEFECT ENGINEERING OF ION IMPLANTATION DAMAGE IN DEVICES ACTIVATED BY SOLID PHASE EPITAXY TAN CHUNG FOONG (B.Eng (Hons) NUS) A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2006 “… Every day you may make progress. Every step may be fruitful. Yet there will stretch out before you an ever-lengthening, ever-ascending, ever-improving path. You know you will never get to the end of the journey. But this, so far from discouraging, only adds to the joy and glory of the climb. “ Sir Winston Churchill, British Prime Minister (1874 - 1965) Acknowledgements However seemingly modest these acknowledgements are compared to my gratitude, I sincerely hope, nevertheless, that the following recognitions are appreciated. Developing a fundamental understanding is a necessarily lonely adventure which requires tremendous patience. For the times when the dreadful “blockades” step in with unpredictable anomalies, I wish to express the enjoyable insights and exchange of perspectives between the unofficial mentors from Chartered Semiconductor. I am especially grateful to Dr. Lee Hyeok Jae whose detailed observations have taught me how to look at results more carefully, and the aggressive optimism of Dr. Liu Jinping whose enthusiasm continues to propel endlessly. To the Special Project students, I am grateful for their making of a wonderful research atmosphere to work in. The frequent teases, meals and occasional outing had definitely lifted a huge burden off discussion about the rocking curves with Lydia. Oh what fun, it has been! I am most genuinely grateful to my research supervisor Assoc. Prof. Chor Eng Fong, from whom I have learned the most of all. Her patience, boundless insights, and unique talent to communicate have been a remarkable learning experience. I consider myself blessed to have had the opportunity to work with such combination of excellence both as a navigator and a teacher. Special thanks also goes to Dr. Lap Chan for enrolling me in the Chartered-URI program, the training and support which he provided. The technical presentations every Wednesday have broadened my horizons tremendously. To Kheng Chok, thank you for the guidance through the manufacturing protocol and integration perspective of the fabrication process. i At the university, colleagues from the Centre of Optoelectronics (COE), Haiting, Lip Khoon and Janis, who have selflessly lent a helping hand in training for operating the rapid thermal anneal and e-beam evaporator equipment. Many apologies for the “troubleshooting” phone calls on Sundays and weekends too! A special mention also goes to my family and friends, who knowingly or not, gave me the most appreciative support. Finally, I humbly thank God, for His presence and blessings, which has made this experience a safe and truly enriching journey. Thank you all! ii Table of Contents I. ACKNOWLEDGEMENTS i II. TABLE OF CONTENTS iii III. LIST OF TABLES x IV. CHAPTER INTRODUCTION AND MOTIVATION 1.1 Background 1.2 Technology Scaling 1.3 The challenging metal oxide semiconductor field effect transistor (MOSFET) 1.4 Significance of ion implantation 1.4.1 Implantation induced damage and annealing 1.4.2 Future Annealing Technologies 9 1.5 Research Objectives 13 1.6 Outline of the thesis 14 V. CHAPTER LITERATURE REVIEW 16 2.1 Introduction 16 2.2 Solid phase epitaxial regrowth (SPER) annealing 16 2.2.1 Concept of SPER 2.2.1 Factors affecting SPER rate 17 18 2.3 Extended defect evolution and dissolution during annealing 21 2.4 Carbon in silicon 24 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 2.5 Carbon as a sink for silicon interstitial Carbon and the suppression of boron diffusion Enhanced boron diffusion Suppressed boron diffusion in the presence of carbon Secondary EOR suppression Electrical activity in the presence of carbon Devices with incorporated carbon 2.5.1 Heterojunction bipolar transistor (HBT) 2.5.2 Metal oxide semiconductor field enhanced transistor (MOSFET) 2.5.3 Strained silicon MOSFET 24 26 26 28 30 31 32 33 35 37 iii VI. CHAPTER GROWTH AND CHARACTERIZATION OF CARBON IN SILICON 38 3.1 38 Carbon in silicon 3.1.1 Epitaxy Incorporation of carbon 3.1.2 Maximizing substitutional carbon incorporation 3.2 Quantification of the carbon content 3.2.1 3.2.2 3.2.3 3.2.4 3.3 39 40 41 Quantification of substitutional carbon with HRXRD rocking curve 42 Deviation from Vegard’s law at low carbon concentration 44 HRXRD rocking curve to determine the composition of the epitaxial layer 45 Simulation of HRXRD rocking curve for the determination of the thickness and composition of epitaxial layers 47 Determining the flow rate of methylsilane for the incorporation of carbon 49 VII. CHAPTER CARBON AND SUPPRESSION OF SECONDARY IMPLANTATION DEFECTS 55 4.1 Introduction 54 4.2 Indium as EOR markers 55 4.3 Determining indium dose for EOR defect formation 56 4.3.1 Results and discussion 4.4 Indium segregation with different annealing temperature 4.4.1 Experimental Setup 4.4.2 Results and Discussions 4.5 Eliminating indium EOR defect using substitutional carbon 56 58 59 60 62 4.5.1 Background 62 4.5.2 Effects of substitutional carbon incorporation on implanted indium end-of-range (EOR) defect under high temperature spike annealing conditions 64 4.5.3 Defect Suppression of Indium End-of-Range during Solid Phase Epitaxy Annealing Using Si1-yCy in Silicon 69 4.6 Conclusions 72 VIII. CHAPTER JUNCTION WITH CARBON INCORPORATION 74 5.1 Introduction 74 5.2 Gated Diode 75 5.2.1 Junction leakage dependence on gate biasing 5.2.3 Gate induced drain lowering (GIDL) 5.3 Incorporating carbon layer for device fabrication 5.3.1 S/D Implant Damage profile 5.3.2 Incorporating epitaxial layers to the substrate 5.3.3 Device fabrication 75 76 78 79 80 81 iv 5.4 Junction leakage in carbon incorporated devices under SPER annealing 5.4.1 Results and discussion 5.4.2 Conclusion 5.5 Improving junction leakages in Si1-yCy devices 5.5.1 Thermal driving to reduce interstitial carbon concentration 5.5.2 Thermal driving and junction leakage suppression in Si1-yCy devices 5.6 Summary 82 83 86 87 87 90 95 IX. CHAPTER FABRICATION AND CHARACTERIZATION OF CARBON INCORPORATED NMOSFETS 96 6.1 Introduction 96 6.2 Device fabrication 99 6.2.1 Determination of the dimension of the carbon layer 6.2.2 Device Fabrication 98 102 6.3 Junction leakage of n+-p junctions of the nMOSFET 103 6.4 Gate stack characteristics 108 6.5 I-V characteristics of carbon incorporated n-MOSFET 112 6.6 Analysis of body effect 117 6.7 Reducing SPER annealing temperature 122 6.8 Summary 125 X. CHAPTER SUMMARY AND FUTURE WORK 127 7.1 Summary 127 7.2 Future work 129 XI. APPENDICES A.1 Effects of impurity on the SPER growth rate 130 A.2 Material data of selected group-IV elements 135 A.3 Fabrication of gated diode 136 A.4 Fabrication of the nMOSFET 138 A.5 Channel dopant extraction with capacitance measurements [105] 141 A.6 Transistor with masking step 143 v XII. APPENDIX B List of publications and presentations resulting from this work XIII. LIST OF REFERENCES 146 148 vi List of Figures Figure 1.1 Actual and forecast sales figures in the world semiconductor industry [1].1 Figure 1.2 Evolution of number of transistors packed into each of Intel’s new generation of microprocessors, describing Moore’s law [2] .3 Figure 1.3 Cost of fabrication of transistors, DRAM and FPGA decreases progressively over the years with the advancement of semiconductors devices .4 Figure 1.4 Actual US government spending on computers compared to that as if the computer cost were maintained at a pricing at 1995 [3] Figure 1.5 Increasing processing power over the years which increases with the number of transistors packed in to the microprocessor [4] Figure 1.6 Cross-sectional XTEM image illustrating (a) the interconnection involving contacts, vias and levels of metal lines. Inset: Circle compares the relative dimension between the MOSFET with the contacts and vias. (b) a 180 nm gate length MOSFET Courtesy: Chartered Semiconductor Ltd .6 Figure 1.7 Micrograph of biological structures illustrating the dimension of (a) strand of hair and (b) an influenza viral strain (Source: www.about.com). It can be seen that an influenza virus is approximately 1000 times smaller than a strand of hair. .6 Figure 1.8 Illustration of the various implant regions in CMOS architecture. Source: Axcellis Technical Seminar .8 Figure 2.1 Different damage regions in crystal caused by an amorphizing implantation. 18 Figure 2.2 Solid-phase epitaxial regrowth versus annealing time for an amorphous implanted layer on silicon .19 Figure 2.3 (a) Regrowth rate versus the orientation of Si substrate for implanted amorphous Si annealed at 550 °C. (b) Arrhenius plot for isochronal anneal of amorphous layers on Si substrate for different substrate orientation [29] 20 Figure 2.4 Evolution of damage in implanted region during an annealing process 22 Figure 2.5 (a) Density of extended defects in the EOR, and (b) Density of interstitials bound by extended defects in the EOR as a function of annealing time at 750 °C. [14] 23 vii Figure 2.6 Schematics illustrating (a) an interstitial silicon located near a substitutional carbon species in a silicon lattice. (b) The resulting highly mobile interstitial carbon complex formed by binding the interstitial to the carbon atom 25 Figure 2.7 Schematics illustrating (a) an interstitial silicon located near a substitutional carbon species in a silicon lattice. (b) The resulting highly mobile interstitial carbon (Ci) species formed. 25 Figure 2.8 Schematics illustrating (a) an interstitial silicon located near a substitutional boron in a silicon lattice. (b) the resulting highly mobile boron interstitial cluster formed .27 Figure 2.9 The profiles of boron after diffusion (a) without carbon, (b) with carbon in the substrate. (c) Uniform carbon profile achieved by multiple implantations into the silicon substrate [19]. .29 Figure 2.10 Boron diffusion profiles for a superlattice containing a buried spike of substitutional carbon [19] 30 Figure 2.11 SIMS profiles of (a)Si0.8Ge0.2, (b)Si0.795Ge0.2C0.05, and (c)Si0.795Ge0.2C0.005 following ion implantation and annealing at 755 °C [25] 33 Figure 2.12 Gummel plots and collector current versus base-collector voltage plots for HBTs with a Si n-emitter and (a) a SiGe base, and (b) a SiGeC base [25]. 34 Figure 2.13 Threshold voltage as a function of gate-length for the Si1-yCy devices and the control pure silicon device [58]. 36 Figure 2.14 (a) The profiles of boron halo in Si and SiGe:C layer, (b) ID-Vgs sweep comparing the short channel effects of the SiGe:C device and the silicon control device [60]. 36 Figure 3.1 Substitutional carbon content (measured by XRD) versus total carbon content (measured by SIMS) for Si1-yCy films grown by Chemical Vapor Deposition at different temperatures and SiH4 partial pressures [69] 41 Figure 3.2 Schematics illustrating (a) the lattice arrangement of a silicon substrate, and (b) a pseudomorphically strained Si1-yCy layer grown on top of a silicon substrate. a Siy represents the lattice constant of silicon and symbols aSi⊥1− y C y and a Si|| 1− yC y indicate the lattice constant of the carbon layer in the indicated direction 43 Figure 3.3 Lattice constant of silicon, relaxed Si1-yCy and strained Si1-yCy as a function of carbon fraction. Inset indicates the value of lattice parameters of single crystal silicon and carbon .43 viii • Gate oxidation thermal through oxidation rapid (RTO), followed by LPCVD polysilicon deposition at 620 °C. Insitu doping. p − Sub • Gate masking and patterning p − Sub • Arsenic source and drain extension implantation • As ~1-2 ×1015 cm-2 p − Sub • Self aligned spacer deposition p − Sub 139 • Self amorphizing deep sourcedrain arsenic implantation. • As ~2-4×1015 cm-2 n+ n+ p − Sub • S/D activation annealing n+ n+ p − Sub • Salicide formation, either NiSi or CoSi, for contact formation prior n + n + to electrical probing p − Sub 140 A.5 Channel dopant extraction with capacitance measurements [105] Capacitance-Voltage (C-V) profiling is based on the measurement of differential capacitance as a function of gate bias. When an incremental charge density of dQG is added to the gate region, it causes a slight movement of the depletion layer edge by an amount, dw . This is such that the depletion region uncovers sufficient charge to compensate dQG . If the ionized dopant density is N (w) , where w is the depletion width under a given gate potential, then dQG = −qN ( w)dw eqn (A.1) This forms the main equation to be solved in C-V ionized impurity profiling. Obtaining dQG From eqn. (A.1), dQG may be obtained from capacitance measurements, C m since C m = dQG ; where dVG is the change gate potential. Therefore, dVG dQG = C m dVG eqn (A.2) Next, information on dw must be extracted in order to obtain N (w) from the C-V measurement. Obtaining dw The depletion layer capacitance, C dep maybe given by the expression, C dep = εs w eqn. (A,3) where ε s is the permittivity of silicon. 141 The change in w , dw may be obtained from a change in C dep from the expression,  dw = ε s d  C  dep  d C  dep     eqn (A.4)   can obtained by the change in capacitance when there is a change in   the gate potential, dVG . The changes in the capacitances can be related to the measured capacitances C m , by first substituting an oxide capacitance, Cox into eqn. (A.4). This is possible as Cox is independent of the gate potential. Therefore,  1 dw = ε s d  +  Cox C dep      eqn (A.5) The capacitances term in eqn (A.5) may be represented by an overall measured capacitance, C m .  dw = ε s d   Cm    eqn (A.6) Substituting eqn A2 into A1, C m dVG = − qN ( w)dw eqn (A.7) Then substituting eqn (A.6) into (A.7) to obtain  C m dVG = −qN ( w)ε s d   Cm    eqn. (A.8) Solving eqn. (A.8) yields, the impurity concentration at the depletion width,  d     N ( w) = − qε s C m dV C G m    The depletion width, −1 eqn. (A.9)  1   w = ε s  −  C m C ox  142 A.6 Transistor with masking step By surrounding the drain region with gate, the drain is always isolated from the source. Therefore it is possible to obtain a MOSFET structure with a single masking step. Such a structure can be seen in Version of the single mask transistor shown in Fig. A.1 Version 1: single mask transistor Width = 230 Drain Source 65 Gate 65 (a) (b) Figure A.1 Version of (a) single mask transistor illustrating the drain, source and gate region, and (b) the physical dimensions of the transistor. Advantages: • MOSFET transistor can be fabricated with a single masking layer which reduces the processing time tremendously. • No oxide isolation is needed as the drain is isolated from the source from layout • Suitable for extraction of electrical measurements which does not require normalization or comparison with literatures Disadvantages 143 • A common source, where the devices share a huge source region. Difficulty comes in when isolating the individual current components. For example, the component of drain leakage into source, as the source consistently displays huge leakage current. • Difficulty in the extraction of effective width of the transistor as the dominant path for current flow is undetermined. Version 2: Ladder structure The second version of the single mask transistor, ladder structure is shown in Fig. A.2. The layout was designed in order to improve the difficulties faced in the first version. In addition, the layout was optimized in order to obtain more variety of transistor gate lengths with minimal space. 110 Gated diode 110 0.18 Guard ring 10 0.11 0.35 1.0 0.13 80 Capacitor/ Common Gate Width = 80 (a) (b) Figure A.2 (a) Schematics illustrating the dimensions of the layout of the transistor and (b) the layout drawn in Cadence software Additional features • a guard ring to isolate the transistor from the other devices on the wafer. 144 • A shorter and defined width. This prevents the HP4156 parametric analyzer from reaching its compliance of 100 mA during measurements. Normalization of the Id,sat becomes more feasible. • For a given salicide thickness, devices show smaller series resistance as the overall magnitude of Id,sat is smaller during measurement. • A variety of gate length for assessment of short channel effect (SCE) • Large area diode for leakage measurement. • Larger pad size to ease probing. 145 Appendix B List of publications and presentations resulting from this work Journal articles 1. C. F. Tan, E. F. Chor, H. Lee, , E. Quek, and L. Chan, “Enhancing leakage suppression in carbon rich silicon junctions,” IEEE Electron Dev. Lett., vol. 27 pp. 442-444 June 2006. 2. C. F. Tan, E. F. Chor, J. Liu, H. Lee, E. Q., and L. Chan, “Influence of substitutional carbon incorporation on implanted indium related defect and transient enhanced diffusion,” Appl. Phys. Lett., vol. 83, pp. 4169-4171, 2003. 3. C. F. Tan, E. F. Chor, H. Lee, J. Liu, E. Quek, and L. Chan, "Defect suppression of indium end-of-range during solid phase epitaxy annealing using Si1-yCy in silicon," Thin Solid Films, vol. 504, pp. 132-135, May 2006. 4. C. F. Tan, E. F. Chor, H. Lee, J. Liu, E. Quek, and L. Chan, "Leakage suppression of gated diodes fabricated under low temperature annealing with substitutional carbon Si1-yCy incorporation," IEEE Electron Dev. Lett., vol. 26, pp. 252-254, May 2005. Conference papers/presentations 1. C. F. Tan, E. F. Chor, H. Lee, J. Liu, E. Quek, and L. Chan, "Buried epitaxial, Si1yCy (y = 0.07 %) for the suppression of leakage in SPER (550 °C 10 mins) activated junctions and current drive enhancement in nMOSFET," in Proc. International Conference on Solid State Devices and Materials (SSDM), Kobe, Japan, 2005, pp. 902-903. 2. C. F. Tan, E. F. Chor, H. Lee, J. Liu, E. Quek, and L. Chan, "Suppressed leakage in low temperature RTA (700°C 30s) Junctions with buried epitaxial Si1-yCy," in Proc. 207th Electrochemical Society (ECS) Conference, Canada, 2005. 3. C. F. Tan, E. F. Chor, H. Lee, J. Liu, E. Quek, and L. Chan, "Defect suppression of indium end-of-range during solid phase epitaxy Annealing using Si1-yCy Alloy in Silicon," presented at ICMAT 2005 & ICAM 2005, Singapore, 2005. 4. C. F. Tan, E. F. Chor, H. Lee, J. Liu, E. Quek, and L. Chan, "A Low-Leakage Low Temperature S/D Anneal (700 °C 30 s) n-MOSFET using Substitutional Si1yCy: elimination of secondary end-of-range (EOR) implant defects," presented at Symp. Of Microelectronics (SOM), Singapore, 2004. 146 Patents 1. C. F. Tan, J. Liu, H. Lee, K. C. Tee and E. Quek, “A material architecture for the fabrication of low temperature (< 800˚C) transistor”, US Patent No: 7,169,675, Jan 30 2007. 2. C. F. Tan, H. Lee, E.F. Chor and E. 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Ltd., 1991. 154 [...]... the silicon substrate brings about different characteristics which are usually not observed in a silicon substrate One of such characteristics is the dramatic suppression of boron diffusion [19-21] and elimination of implantation EOR defects [22, 23] in the presence of carbon The combined effects of dopant diffusion suppression and defects elimination make carbon incorporation in silicon potentially applicable... are EOR defect free In Chapter 5, the characterizations of junctions incorporated with carbon are reported and it is seen that junction leakages can be improved in the presence of carbon Further improvement in the leakages may be obtained in carbon junctions by prolonging the annealing at a temperature sufficient for interstitial carbon diffusion Using combinations of epitaxial silicon cap and carbon. .. harnessed by an effective carbon incorporation in the silicon device Contributions from this work to the field of material science and microelectronics engineering are as follows: 1 Demonstration of EOR defect elimination under spike annealing with carbon incorporation solely at the EOR region This was subsequently extended to the lower SPER annealing temperature range 2 Demonstration of reducing junction... effects of carbon incorporation and EOR defects are discussed in Chapter 4 With the use of indium markers (for implantation defects) and XTEM, the incorporation of carbon has shown to lead to a substantial elimination of EOR defects in spike annealed samples This work also extends into the lower SPER annealing temperature regime of 650 °C, which opens up the possibility of fabricating SPER devices. .. conventional nMOSFET fabrication 97 Figure 6.2 Simulated as-implant profile in the (a) S/D junction regions, and (b) channel region of the MOSFET Defect profile in the S/D junction regions xi is represented by the dashed line in (a) Amorphization and EOR defects are minimal in the channel region 99 Figure 6.3 (a) Schematic showing the locations of the channel implant profiles and EOR defect. .. the transition between the amorphous and crystalline region At the EOR, the silicon substrate retains its crystalline arrangement but contains a supersaturation of excess interstitial point defects [17] resulting from transmitted ions and recoiled atoms during the implantation Beyond the EOR, the substrate is not damaged by implantation and remains crystalline During annealing, the regrowth of the amorphous... differences in the electrical behavior of Si1-yCy devices, which includes junction leakage distribution, drive current enhancement and suppression of body bias 1.6 Outline of the thesis In chapter 2, a literature review is provided on the SPER annealing and the effects of carbon in silicon This chapter includes a discussion on the kinetics of SPER annealing and factors affecting the annealing The sinking mechanism... defects using carbon incorporated by means of an epitaxy growth technique (i.e., chemical vapour deposition) was examined In the later stage, fabrication and characterization of carbon incorporated devices was carried out in order to develop further understanding on the effects of carbon on devices, which include junctions and MOSFETs It is hoped that with a better understanding of these devices, desirable... and indium for p-type semiconductor Dopant incorporation may be achieved mainly through a diffusion process or ion implantation Ion implantation remains the industrial standard to introduce dopants into the silicon substrate for the fabrication of devices This is because it is the best known method for introducing high dopant concentration above classical solid source diffusion with good precision... current in SPER annealed Si1-yCy devices 3 Improvement in junction leakage suppression in Si1-yCy devices by thermally driving away interstitial carbon 4 Development, from an integration approach, of a MOSFET structure with a dual function carbon layer, i.e., to control boron diffusion at the channel and eliminate EOR defects in the source and drain regions under SPER annealing 13 5 An understanding of . CARBON RICH SILICON, Si 1-y C y , FOR DEFECT ENGINEERING OF ION IMPLANTATION DAMAGE IN DEVICES ACTIVATED BY SOLID PHASE EPITAXY . annealing conditions 64 4.5.3 Defect Suppression of Indium End -of- Range during Solid Phase Epitaxy Annealing Using Si 1-y C y in Silicon 69 4.6 Conclusions 72 VIII. CHAPTER 5 JUNCTION. Discussions 60 4.5 Eliminating indium EOR defect using substitutional carbon 62 4.5.1 Background 62 4.5.2 Effects of substitutional carbon incorporation on implanted indium end -of- range (EOR) defect