CRITICAL DIMENSION AND TEMPERATURE CONTROL IN MULTI ZONE THERMAL PROCESSING 2

i Acknowledgements I would like to express my deepest gratitude to my supervisor, Professor Ho Weng Khuen, for his excellent guidance and consistent support throughout my graduate research at the National University of Singapore. I have indeed benefited enormously from the insightful advice and instruction that he offered in our discussions. Without his dedicated help, this thesis would have been impossible. I would also like to express my appreciation to Professor Ling Keck Voon for his help rendered to my research in Multiplexed Model Predictive Control. I would also like to acknowledge the National University of Singapore for the generous scholarship and research facilities. I am also extremely thankful to my friends and colleagues: Dr. Fu Jun, Dr. Chen Ming, Dr. Yan Han, Dr. Wang Yuheng, Dr. Shao Lichun, Mr. Nie Maowen, Mr. Chua Teck Wee, Mr. Ngo Yit Sung, and many others working in the Advanced Control Technology Laboratory. I have enjoyed the excellent cooperation during the experiment implementation and entertaining time spent on the badminton court with them. We have all contributed to the conducive and congenial working environment. ii Finally and most importantly, my heartfelt thanks to my parents and girlfriend for their love and support. Their love is my impetus to overcome difficulties faced not only in research but also in my daily life. I would have never reached so far without their constant encouragement and support. iii Contents Acknowledgements i Table of Contents iii Summary vii List of Tables ix List of Figures x Introduction 1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1.1 Warpage Effects in Lithography . . . . . . . . . . . . . . . 1.1.2 Multiplexed MPC in Lithography . . . . . . . . . . . . . . iv 1.2 Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.1 Improvement of CD Uniformity by Real-Time Temperature Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2 Experimental Evaluation of MMPC Computation Load . . 1.2.3 Derivation and Experimental Verification of MMPC ISE formula for PEB process . . . . . . . . . . . . . . . . . . . 1.3 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CD and Real-Time Temperature Control for Warped Wafers 10 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Thermal Modeling of the Baking Process . . . . . . . . . . . . . . 15 2.3 Experiment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.1 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.2 Runs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.3 Real-Time Control . . . . . . . . . . . . . . . . . . . . . . 25 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.4 v Introduction to Multiplexed MPC and its Computational Load Evaluation 32 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.2 An Introduction to Multiplexed MPC . . . . . . . . . . . . . . . . 34 3.3 Multi-Zone Bake Plate Thermal Modeling . . . . . . . . . . . . . 41 3.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Integral Square Error Performance of Multiplexed MPC 54 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 4.2 ISE Formula for Multiplexed MPC . . . . . . . . . . . . . . . . . 56 4.3 Experiment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Conclusion 71 5.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 vi Bibliography 76 Author’s Publications 87 vii Summary This thesis investigates the application of advanced process control for thermal processing in the lithography step to improve lithography performance as the final Critical Dimension (CD) uniformity is sensitive to temperature during thermal processing. Wafer warpage affects the thermal processing in lithography and can result in CD nonuniformity. Real-time temperature control is proposed and demonstrated in the thesis that real-time control of the post-exposure bake temperature to give a non-uniform temperature distribution across a warped wafer can reduce CD non-uniformity across the wafer. Multiplexed Model Predictive Control (MMPC) has recently been proposed as a strategy to reduce computational complexity. It is experimentally demonstrated in the thermal processing step that MMPC has computational advantage over the Standard MPC (SMPC), for large horizon and when constraints are present. The reduction in computational load can be used gainfully to increase viii sampling rate and improve thermal processing performance. To provide a framework for systematic analysis of the MMPC, a formula to compute the Integral Square Error (ISE) performance for load disturbance is derived and validated on a multi-zone semiconductor manufacturing thermal process. Experimental results validate the formula and show that shorter sampling time can result in faster recovery of bake-plate temperature when a cold wafer is placed on the bake-plate. ix List of Tables 2.1 Thermophysical Properties . . . . . . . . . . . . . . . . . . . . . . 17 2.2 Thermal Capacitances and Resistances. . . . . . . . . . . . . . . . 17 2.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.1 Maximum Computation Time of MMPC and Standard MPC with Varying Horizon . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 49 Experimental and Theoretical Results for different sampling periods 68 x List of Figures 2.1 Baking of Flat Wafer 1. Solid-line: center, Dashed-line: edge . . . 13 2.2 Baking of Warped Wafer 4, Solid-line: center, Dashed-line: edge . 14 2.3 The bake-plate used in the experiment. . . . . . . . . . . . . . . . 15 2.4 Baking of Wafer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.5 Critical dimension measurements. Circle: center; Square: edge; Wafer 1–3: flat wafer with conventional baking; Wafer 4–6: warped wafer with conventional baking; Wafer 7–9: flat wafer with optimized baking; Wafer 10–12: warped wafer with real-time on-line adjustment of bake-plate temperature setpoints . . . . . . . . . . 2.6 Temperature measurement on a warped wafer with no photoresist nor pattern. Solid-line: center, Dashed-line: edge . . . . . . . . . 2.7 21 24 Bake-plate setpoint adjusted to give uniform CD for Flat Wafer 7. Solid-line: center, Dashed-line: edge . . . . . . . . . . . . . . . . . 26 72 In Chapter 2, a real-time temperature control method was implemented to improve CD uniformity for warped wafers. Wafer warpage results in CD nonuniformity due to the air-gap variation between wafer and bake plate. A double-zone bake plate was used to heat the wafer center zone and edge zone respectively during PEB. Shipley UVIII was used in the experiment. For at wafers with conventional bake, the within-wafer CD nonuniformity was around 23nm. To obtain uniform CD for at wafers, the bake plate temperature profiles were optimized. CD nonuniformity between the center and edge was improved to around 2nm. For wafers with 140µm center-to-edge warpage, the within-wafer CD nonuniformity was doubled to 46nm with conventional bake. To obtain uniform CD for warped wafers, the real-time temperature control strategy is implemented on the double- zone bake plate. For warped wafers, bake plate temperature setpoint was adjusted online immediately after the maximum bake plate temperature drops. Experimental results showed that the within-wafer CD nonuniformity was reduced to around 2nm for warped wafers. In addition, the nonuniformity between warped wafers and at wafers (wafer-to-wafer) was reduced to around 2nm. As a comparison, the wafer-to-wafer nonuniformity with conventional bake was 37nm for the center and 13.5nm for the edge respectively. In Chapter 3, a revision of the MMPC and results of experimental evaluation of MMPC computational load, which were carried out on a multi-zone bake plate system, were presented. In the experiment, the performances of Standard MPC and MMPC were tuned to be almost the same and then their computational 73 times of solving optimization problems were extracted. Maximum computational load was considered because control calculation must be completed before the next sampling instance for real-time control. MMPC computational load was compared with that of standard MPC. It is demonstrated that MMPC has computational advantage over the standard MPC. This is especially so when horizon is large and constraints are present. For example, the maximum computational time for MMPC with Nu = 25 is given by the peak as 0.45s, whereas for standard MPC the peak is 1.29s with Nu =25. In Chapter 4, we derived a formula to compute the MMPC ISE performance for load disturbance and validated it on a multi-zone semiconductor manufacturing thermal process. The experiment was conducted on a 3-zone bake plate. In addition, the temperature disturbance when a cold wafer was placed on the bake plate was determined experimentally. The room temperature was 25◦ C and the experiments were run at a set-point of 90◦ C. In the baking experiment, a wafer at room temperature was placed on the bake plate controlled with a MMPC controller. MMPC with different sampling intervals have been demonstrated experimentally and the sampling interval h = 0.4s was taken as the example to calculate MMPC ISE performance theoretically. For h = 0.4s, the experiment result of ISE was 0.77 × 103 and the theoretical result was 0.74 × 103 . The simulated results showed match to the experimental results. This would enable one to select a suitable sampling interval to achieve a desired ISE performance. 74 5.2 Future Work Further improvement can be expected if the wafer temperature variation before the maximum drop is taken into considerations. This effect is ignored in the thesis since this period is short (around 10s) compared to normal baking cycle time (1 several minutes). In addition, the wafer temperature during this initial period is low and activation on the chemical reaction is small compared to the high temperature region. While for future lithography when requirements on CD variation become more and more stringent, considering the initial stage will further improve the performance. A possible solution is to implement combined feed- forward and feedback control strategy. Wafer warpage can detected during the post-apply bake, and forwarded to the PEB process where CD is more sensitive to warpage. The bake plate setpoints can be initially adjusted before the wafer arrives. When the wafer arrives for PEB processing, fine adjustment can be accomplished using the real time control method proposed in this thesis since warpage may change somewhat during the intermediate process. The integration of the feed- forward information will further reduce wafer temperature variation. Robustness analysis of the MMPC in the presence of model uncertainty and disturbance would also be of interest. Since modeling error always exists in bakeplate modeling and disturbances are inevitable in PEB processing, it is necessary to ensure that the resulting closed loop system is stable in the presence of modeling error and disturbance. Robust MPC has received much attention and remains 75 an active area for research. A recent survey [62] gives a thorough list of work in this area so far. [63] considers robustness analysis of nominal MPC formulations and [64] presented some robustness results of receding horizon control with LMI formulations. In addition, [65]–[66] proposed a new RMPC method which aimed at constrained system with time-varying model uncertainty with various uncertainty set. A key challenge in designing a robust MPC algorithm suitable for embedded applications is to achieve the desired robustness without making the resulting computation complex. A recent work [52] extended the multiplexed MMPC with guaranteed robustness under uncertain but bounded disturbance. However, it is a very initial study, more thorough work still needs to be done. 76 Bibliography [1] C. A. Mack, Fundamental Principles of Optical Lithography, John Wiley & Sons, 2007. [2] H. Xiao, Introduction to Semiconductor manufacturing Technology, Prentice Hall, 2001. [3] C. A. Mack, Field Guide to Optical Lithography, SPIE Optical Engineering Press, 2006. [4] J. Sturtevant, “CD Control Challenges for Sub-0.25µm Patterning”, SEMAT- ECH DUV Lithography Workshop, Austin, TX, Oct. 16-18, 1996. [5] May G.S. and C.J. Spanos, Fundamentals of Semiconductor Manufacturing and Process Control, John Wiley & Sons. Inc. 2006. [6] J. Cain, P. Naulleau, and C. Spanos, “Critical Dimension Sensitivity to Postexposure Bake Temperature Variations in EUV Photoresists”, Proceedings of SPIE, Vol. 5751, pp. 1092-1100, 2005. 77 [7] H. J. Levinson, Principles of Lithography, SPIE Optical Engineering Press, 2005. [8] P.D. Friedberg, C. Tang, B. Singh, T. Brueckner, W. Gruendke, B. Schulz, and C. Spanos, “Time-based PEB Adjustment for Optimizing CD Distributions”, Proceedings of SPIE, Vol. 5375, pp. 703-712, 2004. [9] R. Kaesmaier, A. Wolter, H. L¨ochner, and S. Schunck, “Ion-projection Lithog- raphy: Nov00 Status and Sub-70nm Prospects”, Proceedings of SPIE, Vol. 4226, pp. 52-58, 2000. [10] A. Ehrmann, A. Elsner, R. Liebe, T. Struck, J. Butschke, F. Letzkus, M. Irmscher, R. Springer, E. Haygeneder, and H. L¨oschner, “Stencil Mask Key Parameter Measurement and Control”, Proceedings of SPIE, Vol. 3997, pp. 373-384, 2000. [11] K. Nordquist, E. Ainley, D. J. Resnick, E. Weisbrod, C. Martin, R. Engelstad, Z. Masnyj, and P. Mangat, “Inter- and intramembrane resist critical dimension uniformity across a SCALPEL mask”, Journal of Vacuum Science and Technology B, Vol. 18, No. 6, pp.3242-3247, 2000. [12] L. Berger, P. Dress, T. Gairing, “Global critical dimension uniformity improvement for mask fabrication with negative-tone chemically amplified resists by zone-controlled postexposure bake”, Journal of Microlithography, Microfabrication, and Microsystems, Vol. 3, No. 2, pp. 203-211, 2004. 78 [13] Q. Zhang, K. Poolla, and C. J. Spanos, “Across Wafer Critical Dimension Uniformity Enhancement Through Lighography and Etch Process Sequence: Concept, Approach, Modeling, and Experiment”, IEEE Trans. on Semi. Manu., Vol. 20, No. 4, pp. 488-505, 2007. [14] Q. Zhang, P. Friedberg, C. Tang, B. Singh, K. Poolla and C. Spanos, “Acrosswafer cd uniformity enhancement through control of multi-zone peb profiles”. Proceedings of SPIE, Vol. 5375, pp. 276-286, 2004. [15] H. C. Lee, C. J. Chen, H. C. Hsieh, L. Berger, W. Saule, P. Dress and T. Gairing, “Global cd uniformity improvement for car masks by adaptive post-exposure bake with cd measurement feedback”. Proceedings of Semiconductor Manufacturing Technology Workshop pp. 99-102, 2004. [16] C. D. Schaper, K. El-Awady, T. Kailath, A. Tay, L.L. Lee, W.K. Ho, and S. Fuller, “Characterizing Photolithographic Linewidth Sensitivity to Process Temperature Variations for Advanced Resists Using a Thermal Array”, Applied Physics A: Material Science and Processing, DOI: 10.1007/s00339003-2343-x, 2003. [17] Q. Zhang, C. Tang, T. Hsieh, N. Maccrae, B. Singh, K. Poolla, and C. Spanos, “Comprehensive CD Uniformity Control in Lithography and Etch Process”, Proceedings of SPIE, Vol. 5752, No. 3, 2005. 79 [18] S. Scheer, M. Carcasi, T. Shibata, and T. Otsuka, “CDU Minimization at the 45nm Node and Beyond: Optical, Resist, and Process Contributions to CD Control”, Proceedings of SPIE, 65204H, Vol. 6520, 2007. [19] A. Hisai, K. Kaneyama, C. Pieczulewski, “Optimizing CD uniformity by total PEB cycle temperature control on track equipment”, Advances in Resist Technology and Processing XIX, Proceedings of SPIE, Vol. 4690, pp. 754-760, 2002. [20] H. T. Chua, A. Tay, Y. H. Wang and X. D. Wu, “A heater plate assisted bake/chill system for photoresist processing in photolithography”, Applied Thermal Engineering, 2008, doi:10.1016/j.applthermaleng.2008.05.024. [21] K.El-Awady, C.D.Schaper, and T.Kailath, “Programmable thermal processing module for semiconductor substrates”, IEEE Trans.Control Syst.Technol., Vol. 12, No. 4, pp. 493-509, 2004. [22] T. Kailath and A. Tay, “Extending the life of optical lithography”, Innovation Mag, Vol. 2, No. 3, pp. 54-56, 2001. [23] M. Kagerer, D. Miller, W. Chang and D. J. Williams,“ArF Processing of 90-nm Design Rule Lithography Achieved Through Enhanced Thermal Processing”, Advances in Resist Technology and Processing XXIII, Proc. SPIE, Vol. 6153, pp. 615333, 2006. 80 [24] S. K. Bhattacharya, I. C. Ume and A. X. H. Dang. “Warpage measurement of large area multitilted silicon substrates at various processing conditions”, IEEE Transactions on Components and Packaging Technology, Vol. 23, No. 3, pp. 497-504, 2000. [25] S. Banerji, P. M. Raj, S. Bhattacharya and R. R. Tummala. “Warpageinduced lithographic limitations of fr-4 and the need for novel board materials for future microvia and global interconnect needs”, IEEE Transactions on Advanced Packaging Vol. 28, No. 1, pp. 102-113, 2005. [26] K. A. El-Awady, “Spatially Programmable Thermal Processing Module for Semiconductors. PhD thesis”, Stanford University, Department of Electrical of Engineering. 2000 [27] S. Y. Yang, Y. D. Jeon, S. B. Lee and K. W. Paik. “Solder reflow process induced residual warpage measurement and its influence on reliability of flipchip electronic packages”, Microelectronics Reliability Vol. 46, pp.512522, 2006. [28] H. Ding, R. E. Powell, C. R. Hanna and I. C. Ume. “Warpage measurement comparison using shadow moire and projection moire methods”, IEEE Transactions on Components and Packaging Technologies Vol. 25, No. 4, pp.714-721, 2002. [29] J. A. Fauque, “Extended range and ultra precision non contact dimensional gauge for ultra thin wafers and work pieces”, US Patent. 2001 81 [30] J. A. Fauque, and R. D. Linder. “Extended range and ultra-precision noncontact dimensional gauge”, US Patent. 1998 [31] Y. M. Lee, M. G. Sung, E. M. Lee, Y. S. Sohn, I. An and H. K. Oh, “Post exposure delay consideration in a 193-nm chemically amplied resist”, Journal of the Korean Physical Society, Vol. 38, No. 3, pp. 255-258, 2001. [32] L. A. P. Surez, P. Georgieva and S. F. Azevedo, “Error Tolerant MPC versus PI Control C a Crystallization Case Study”, Proceedings of the European Control Conference, Budapest, August 2009. [33] K. V. Ling, J. M. Maciejowski, and B. F. Wu, “Multiplexed Model Predictive Control”, 16th IFAC World Congress, Prague, July 2005. [34] K. V. Ling, J. M. Maciejowski, and B. F. Wu, Multiplexed Model Predictive Control, Technical report. Cambridge University Engineering Dept. CUED/FINFENG/ TR.561, 2006. [35] K. V. Ling, W. K. Ho, B. F. Wu, Andreas, and H. Yan, “Multiplexed MPC for Multi-Zone Thermal Processing in Semiconductor Manufacturing”, IEEE Transactions on Control Systems Technology, Vol. 18, No. 6, pp. 1371-1380, 2010. [36] S. Postnikov, S. Hector, C. Garza, R. Peters, V. Ivin, “Critical Dimension Control in Optical Lithography”, Microelectronic Engineering, Vol. 69, No. 24, pp. 452-458, 2003. 82 [37] M. Quirk and J. Serda, Semiconductor Manufacturing Technology, Prentice Hall, 2001. [38] A. Narasimhan and N. Ramanan, “Simulation studies and experimental verification of the performance of a lithocell combination bake-chill station”, Journal of Microlithography, Microfabrication, and Microsystems, Vol. 3, No. 2, pp. 332-338, 2004. [39] Q. Zhang, P. Friedberg, K. Poolla, C. Spanos, ”Enhanced Spatial PEB Uniformity through a Novel Bake Plate Design”, AEC/APC XVII 2005. [40] D. Steele, A. Coniglio, C. Tang, B. Singh, S. Nip and C. Spanos, “Characterizing post exposure bake processing for transient and steady state conditions, in the context of critical dimension control”, Proceedings of SPIE Vol. 4689, pp. 517-530, 2002. [41] S. K. Bhattacharya, I. C. Ume and A. X. H. Dang, “Warpage Measurement of Large Area Multitilted Silicon Substrates at Various Processing Conditions”, IEEE Trans. Components and Packaging Technology, Vol. 23, No. 3, pp.497504, 2000. [42] W. K. Ho, A. Tay, Y. Zhou and K. Yang, “In Situ Fault Detection of Wafer Warpage in Microlithography”, IEEE Transactions on Semiconductor Manufacturing, Vol. 17, No. 3, pp. 402-407, 2004. 83 [43] A. Tay, W. K. Ho, N. Hu, “An In-Situ Approach to Real-Time Spatial Control of Steady-State Wafer Temperature During Thermal Processing in Microlithography”, IEEE Transactions on Semiconductor Manufacturing, Vol. 20, No. 1, pp. 5-12, 2007. [44] K. Raznjevic, Handbook of Thermodynamic Tables and Charts, Washington, DC: Hemisphere, 1976. [45] National Instruments Corporation [Online]. Available: http://www.ni.com, 2007. [46] A. Tay, W. K. Ho, A. P. Loh, K. W. Lim, W. W. Tan, and C. D. Schaper, “Integrated bake/chill module with in situ temperature measurement for photoresist processing”, IEEE Transactions on Semiconductor Manufacturing, Vol. 17, No. 2, pp. 231-242, 2004. [47] L. L. Lee, C. Schaper and W. K. Ho, “Real-time predictive control of photoresist film thickness uniformity”, IEEE Transactions on Semiconductor Manufacturing, Vol. 15, No. 1, pp. 51-60, 2002. [48] M. M. J. Decre and P. H. G. M. Vromans, “Cover layer technology for high-numerical-aperture digital video recording system”, Japanese Journal of Applied Physics Part 1, Vol. 39, No. 2B, pp. 775-778, 2000. [49] N. Singh, H. Q. Sun, W. H. Foo, S. S. Mehta, R. Kumar, A. O. Adeyeye, H. Suda, T. Kubota, Y. Kimura, and H. Kinoshita, “Swing effects in alternating 84 phase shift mask lithography: Implications of low illumination”, Journal of Vacuum Science and Technology B, Vol. 24, No. 5, pp. 2326-2330, 2006. [50] S. S. Yu, B. J. Lin, A. Yen, C. M. Ke, J. Huang, B. C. Ho, C. K. Chen, T. S. Gau, H. C. Hsieh and Y. C. Ku, “Thin-film optimization strategy in high numerical aperture optical lithography, part 1: principles”, Journal Of Microlithography Microfabrication And Microsystem, Vol. 4, No. 4, pp. 043003-1-11, 2005. [51] S. S. Yu, B. J. Lin and A. Yen, “Thin-film optimization strategy in high numerical aperture optical lithography, part 2: applications to ArF”, Journal Of Microlithography Microfabrication And Microsystem, Vol. 4, No. 4, pp. 043004-1-9, 2005. [52] A. G. Richards, K. V. Ling, and J. M. Maciejowski, “Robust Multiplexed Model Predictive Control”, European Control Conference, pp. 441-446, 2007. [53] M. Quirk, and J. Serda., Semiconductor Manufacturing Technology, Prentice Hall, 2001. [54] K. Ruck, H. Weichert, S. Hornig, F. Finger, G. Fleischer, and D. Hetzer, “Effect and procedures of Post Exposure Bake temperature optimization on the CD uniformity in a mass production environment”, Proceedings of SPIE, Vol. 6518, pp. 651850, 2007. 85 [55] W. K. Ho, A. Tay, M. Chen, and C. M. Kiew, Optimal Feed-Forward Control for Multizone Baking in Microlithography, Industrial & Engineering Chemistry Research Vol. 46, No. 11, pp. 3623-3628, 2007. [56] Blanchini, “Set invariance in control”, Automatica, Vol. 35, No. 11, pp. 17471767, 1999. [57] W. K. Ho, A. Tay and C. D. Schaper, “Optimal Control of conductive heating systems for microelectronics processing of silicon wafers and quartz photomasks”, Proceedings of Industrial Electronics Society, November, 1999. [58] W. K. Ho, A. Tay, M. Chen, J. Fu, H. J. Lu and X. C. Shan, “Critical Dimension Uniformity via Real Time Photoresist Thickness Control”, IEEE Transactions on Semiconductor Manufacturing, Vol. 20, No. 4, pp. 376-380, 2007. [59] W. K. Ho, A. Tay, J. Fu, M. Chen and Y. Feng, “Critical dimension and real time temperature control for warped wafers”, Journal of Process Control, Vol. 18, No. 10, pp. 916-921, 2008. [60] K. V. Ling, J. M. Maciejowski and B. F. Wu, “Computing the Cost of Multiplexed MPC”, 10th Intl. Conf. on Control, Automation, Robotics and Vision, pp. 582-587, 2008. 86 [61] S. Bittanti, P. Colaneri and G. D. Nicolao. “The difference perios Riccati equation for the periodic prediction problem”, IEEE Transactions on Automatic Control, Vol. 33, No. 8, pp. 706-712, 1988. [62] A. Bemporad and M. Morari, “Robust model predictive control: A survey,” Robustness in Identification and Control, Vol. 245, pp. 207-226, 1999. [63] E. C. Kerrigan and J. M. Maciejowski, “Robust feasibility in model predicitive control: necessary and sufficient conditions”, 40th IEEE CDC, Orlando FL, December 2001. [64] J. Primbs and V. Nevisti´c, “A framwork for robustness analysis of finite receding horizon control”, IEEE Transactions on Automatic Control, Vol. 45, No. 10, pp. 1828-1838, 2000. [65] Y. J. Wang and J. B. Rawlings, “A new robust model predictive control method I: Theory and computation”, Journal of Process Control, Vol. 14, No. 3, pp. 249-262, 2004. [66] Y. J. Wang, “Robust model predictive control. PhD thesis”, University of Wisconsin-Madison, 2002. 87 Author’s Publications K. V. Ling, W. K. Ho, Y. Feng and B. F. Wu, “Integral-Square-Error Performance of Multiplexed Model Predictive Control”, accepted by IEEE Transactions on Industrial Informatics, 2010. W. K. Ho, A. Tay, J. Fu, M. Chen and Y. Feng, “Critical Dimension and RealTime Temperature Control for Warped Wafers”, Journal of Process Control, 2008 X.Q. Wang, W.K. Ho, K.V. Ling and Y. Feng, “Computational Load Comparison of Multiplexed MPC and Standard MPC”, submitted to The 18th World Congress of the International Federation of Automatic Control (IFAC), 2010. K. V. Ling, W. K. Ho, Aribowo, B. F. Wu, Y. Feng and H. Yan, “Experimental Evaluation of Multiplexed MPC for Semiconductor Manufacturing”, Asian Control Conference, August 2009. [...]... 408 400 401 23 46 1 1 128 .1 125 .4 128 .2 128 .2 128 .0 126 .9 126 .6 126 .6 8 9 11 12 Flat Flat Warp Warp 130.3 130.3 130.3 change to 133.8 130.3 change to 133.7 128 .5 128 .5 128 .5 change to 129 .6 128 .5 change to 129 .5 2. 12 2. 12 1. 52 1.53 1.98 1.98 1.70 1.71 401 398 400 399 400 400 399 400 1 2 1 1 128 .2 128 .2 128 .2 128 .2 126 .6 126 .6 126 .6 126 .6 23 140 120 100 80 60 40 20 0 10 20 30 40 50 60 70 80 90 100 60 70... (2. 1) and (2. 2) It is derived by substituting in nity into (2. 1) and (2. 2) and the derivative of wafer temperature is zero at steady state (2. 7) and (2. 8) demonstrate the required bake plate set point to achieve a desired steady state wafer temperature as Tp1 (∞) = Ra1 Tp2 (∞) = Ra2 1 1 Tw1 (∞) − Tw2 (∞) RT 1 Rw 12 1 1 Tw2 (∞) − Tw1 (∞) RT 2 Rw 12 (2. 7) (2. 8) 19 where Rw1 Ra1 Rw 12 Ra1 Rw 12 + Rw1 Rw 12. .. 44 .21 K/W 2 hπr1 1 Rw2 24 .11 K/W 2 2 hπ (r2 −r1 +dtw ) Rw 12 9. 52 K/W experimental l Ra1 changes with warpage kaa1 2 πr1 Ra2 changes with warpage k π lra2−r2 2 a ( 2 1) Cp1 101 .2 J/K experimental Cp2 165.8 J/K experimental 2 Cw1 2. 8 J/K ρw cw tw πr1 2 2 Cw2 4.98 J/K ρw cw tw π (r2 − r1 ) and standard heat transfer experiments [ 42] –[43] can be conducted to determine most of the thermal capacitance and resistance... wafer and bake-plate can be carried out to obtain a two dimensional model as follows Tp1 (t) − Tw1 (t) Tw2 (t) − Tw1 (t) Tw1 (t) ˙ + − Cw1 Tw1 (t) = Ra1 Rw 12 Rw1 Tp2 (t) − Tw2 (t) Tw1 (t) − Tw2 (t) Tw2 (t) ˙ Cw2 Tw2 (t) = + − Ra2 Rw 12 Rw2 Tp2 (t) − Tp1 (t) Tw1 (t) − Tp1 (t) ˙ Cp1 Tp1 (t) = u1 (t) + + − Rp 12 Ra1 Tp1 (t) − Tp2 (t) Tw2 (t) − Tp2 (t) ˙ + − Cp2 Tp2 (t) = u2 (t) + Rp 12 Ra2 (2. 1) (2. 2) Tp1... nonuniform temperature distribution across the warped Bake−plate Temp (Deg C) 13 1 32 130 128 126 0 20 40 0 20 40 (a) 60 80 60 80 100 Control Signal (V) 2. 5 2 1.5 1 0.5 (b) Time (s) 100 Figure 2. 1: Baking of Flat Wafer 1 Solid-line: center, Dashed-line: edge Bake−plate Temp (Deg C) 14 1 32 130 128 126 0 20 40 0 20 40 (a) 60 80 100 60 80 100 Control Signal (V) 2. 5 2 1.5 1 0.5 (b) Time (s) Figure 2. 2: Baking... Modeling of the Baking Process The distributed thermal processing system used in this work is shown in Figure 2. 3 It consisted of two heating zones, center and edge as shown in Figure 2. 4 Embedded within each of the heating zones were resistive heating elements and temperature sensors The zones were separated by a small air-gap of approximately 1 mm for thermal insulation Spatial distributions of temperature. .. Rw 12 + Rw1 Ra1 Rw2 Ra2 Rw 12 = Ra2 Rw 12 + Rw2 Rw 12 + Rw2 Ra2 RT 1 = RT 2 The thermal modelling is based on energy balance and when there is no input power the steady state bake plate temperature is the ambient temperature, instead of zero 2. 3 2. 3.1 Experiment Setup In all our experiments, commercial chemical amplified resist, Shipley UV3 was spin-coated at 6000 revolutions per minute on a 4-inch wafer After... values in Table 2. 2 A control software system was developed using the National Instruments LabView programming environment [45] Two proportional-integral controllers 18 of the following form were used to control the two zones of the bake-plate 1 TI1 1 e2 (t) + TI2 u1 (t) = Kc1 e1 (t) + e1 (t)dt (2. 5) u2 (t) = Kc2 e2 (t)dt (2. 6) e1 (t) = Tp1 (∞) − Tp1 (t) e2 (t) = Tp2 (∞) − Tp2 (t) where u1 (t), u2 (t)... reported in [11]–[ 12] The resists quoted are used in the DUV process and the nominal CD is 20 0 nm The high sensitivity of CD variation to temperature implies that CD can be controlled by the temperature control in thermal processing, especially in PEB Zhang et al [13] showed that the implementation of an advanced thermal processing system in PEB could reduce CD variation by 40% Zhang et al [14] and Lee... obtain CD uniformity 1.1 .2 Multiplexed MPC in Lithography Model Predictive Control (MPC) has been widely used in industries It has advantage in multivariate control systems and can deal with constrains by nature Previous study in [ 32] shows that for a 3 × 3 multivariate system, MPC could 5 performs equally with PI control in error tracking, but outperforms in energy consumption However, the on-line . process control for thermal processing in the lithography step to improve lithography performance as the final Critical Dimension (CD) uniformity is sensitive to temperature during thermal processing. Wafer. . . . . 9 2 CD and Real-Time Temperature Control for Warped Wafers 10 2. 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2. 2 Thermal Modeling of the Baking Process. warpage affects the thermal processing in lithography and can result in CD nonuniformity. Real-time temperature control is proposed and demonstrated in the thesis that real-time control of the post-exposure