Multi level phase change random access memory (PCRAM) devices with ultrathin barrier layers

MULTI-LEVEL PHASE CHANGE RANDOM ACCESS MEMORY (PCRAM) DEVICES WITH ULTRATHIN BARRIER LAYERS ASHVINI GYANATHAN (B ENG (HONS.)), NATIONAL UNIVERSITY OF SINGAPORE A THESIS SUBMITTED FOR THE DEGREE OF DOCTOR OF PHILOSOPHY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING NATIONAL UNIVERSITY OF SINGAPORE 2013 Declaration I hereby declare that this thesis is my original work and it has been written by me in its entirety I have duly acknowledged all the sources of information which have been used in the thesis This thesis has also not been submitted for any degree in any university previously Ashvini Gyanathan 1st April 2013 Acknowledgements I would like to express my appreciation to my supervisor Dr Yeo Yee Chia for his invaluable guidance and support throughout my graduate studies I am extremely grateful for the knowledge and expertise he has bestowed upon me and I have benefitted immensely from all the invaluable insights and discussions with him; I know that all he has done will ultimately help me greatly in my future endeavours I would also like to express my appreciation for my co-supervisors Dr Zhao Rong and Dr Shi Luping from Data Storage Institute, A*STAR (DSI), who have facilitated my attachment in DSI and gave me helpful insights for project discussions Since most of my fabrications and characterizations were done in DSI, I would also like to thank Hongxin, Tony, Kian Guan and Chun Chee for their assistance in debugging software problems as well as helping me with the fabrication tools in the cleanroom My SNDL mates, who have graduated and who are still climbing that arduous ladder to reach their goals and dreams, have all helped me one way or the other, be it in academic research or simply emotional support I‟d like to give a huge “THANK YOU!” to each and every one of them: Sujith, Kain Lu, Teddy, Samuel, Guo Cheng, Ivana, Eugene, Chunlei, Maruf, Yang Yue, Pengfei, Xingui, Cheng Ran, Yinjie, Gong Xiao, Lanxiang, Liu Bin, Zhou Qian, Xinke, Zhu Zhu, Kien Mun, Phyllis, Shao Ming, Lina, Tong Xin, and Wenjuan I will never forget our bonds of friendship I‟d also like to express my gratitude to the technical staff i in SNDL (past and present), Mr O Yan, Patrick Tang, Lau Boon Teck and Mr Yong Last, but definitely not the least, I would like to extend the deepest gratitude to my brother Amresh, my mom and my dad, for always being there when I needed them most They‟ve helped me in so many ways I can‟t even begin to list them down I‟ve achieved everything that I have today because your love and support motivates me to accomplish things I never thought I knew I could in the first place Words cannot express how much your support in all that I means to me; but I guess I‟ll just have to settle for this: Thank you and I love you ii Table of Contents Acknowledgements ………………………………………………………………i Table of Contents ……………………………………………………………….iii Abstract ……………………………………………………………………… vii List of Tables ……………………………………………………………………ix List of Figures ………………………………………………………………… x List of Symbols ……………………………………………………….…… xxiii Chapter Introduction 1.1 Non-volatile Memory Technology ……………………………….1 1.2 Phase Change Random Access Memory Technology ……………3 1.2.1 Phase change materials and device structures ……………3 1.2.2 Basic operational principles of phase change memory … 1.2.3 Resistance drifting phenomenon in phase change memory devices ………………………………………………… 10 1.3 Aims and Objectives of Research ……………………………….12 1.4 Thesis Organization …………………………………………… 12 Chapter Multi-level dual layered Phase Change Memory Devices with a NGST/Ta2O5/GST Stack 2.1 Introduction …………………………………………………… 16 iii 2.2 Device fabrication ……………………………… …………… 18 2.3 Results and Discussion ………………………………………….20 2.3.1 Electrical characterization ……………………………….20 2.3.2 Thermal simulation analysis …………………………….29 2.4 Chapter Summary ……………………………………………………… 40 Multi-level Phase Change Memory Devices with Si3N4 or Ta2O5 Barrier Layers 3.1 Introduction …………………………………………………… 41 3.2 Device fabrication ……………………………………………….43 3.3 Results and Discussion ………………………………………….45 3.3.1 Electrical characterization ……………………………….47 3.3.2 Thermal simulation analysis …………………………….53 3.4 Chapter Summary ……………………………………………………… 58 Effect of Top Stack Materials on the Performance of Dual Layered Multi-level PCRAM Devices 4.1 Introduction ……………………………………… ……………59 4.2 Device fabrication ……………………………………………….60 4.3 Results and Discussion ………………………………………….63 4.3.1 Electrical characterization ……………………………….63 iv 4.3.2 Selection of phase change materials for two-bit multi-level devices ………………………………………………… 78 4.4 Chapter Summary ……………………………………………………… 78 Two-bit Multi-level Phase Change Memory Devices with a Triple Phase Change Material Stack 5.1 Introduction …………………………………………………… 79 5.2 Device fabrication ……………………………………………….80 5.3 Electrical Characterization ………………………………………82 5.4 Thermal Simulation and Analysis ……………………………….89 5.5 Summary ……………………………………………………….103 Chapter Suppression of Resistance Drift Phenomenon in Multi-level Phase Change Memory Devices 6.1 Introduction …………………………………………………….104 6.2 Resistance Drifting Phenomenon in PCRAM Devices ……… 105 6.3 Experiment …………………………………………………… 109 6.4 Results and Discussion ……………………………………… 113 6.5 Summary ……………………………………………………….121 Chapter 7.1 Conclusion and Future Work Conclusion …………………………………………………… 122 v 7.1.1 Multi-level dual layered Phase Change Memory Devices with a NGST/Ta2O5/GST Stack …………………… …122 7.1.2 Multi-level phase change memory devices with Si3 N4 or Ta2O5 barrier layers …………………………………….123 7.1.3 Effect of Top Stack Materials on the Performance of a Dual Layer Multi-level PCRAM ………….…………………124 7.1.4 Two-bit multi-level phase change memory devices with a triple phase change material stack …………………… 125 7.1.5 Suppression of Resistance Drift Phenomenon in Multi-level Phase Change Memory Devices ……………………….125 7.2 Future Implementation of the Multi-level PCRAM Device … 126 References …………………………………………………………………… 128 Appendix A List of Publications ……………………………………………… 143 vi Abstract Phase change random access memory (PCRAM) is one of the most promising contender to replace FLASH memory PCRAM‟s ability to undergo reversible phase switching serves as its basic operational mechanism PCRAM also exhibits multi-level programming capabilities However, the problem of resistance drifting has impeded the advancement in multi-level programming of PCRAM devices This thesis summarizes work on the device engineering of multi-level PCRAM devices to eliminate the problem of resistance drifting A novel PCRAM device structure was fabricated and characterized Multilevel PCRAM devices comprising two Ge2Sb2Te5 (GST) layers sandwiching a thermal insulating Ta2O5 barrier layer were first fabricated The PCRAM cell comprises a phase change material stack between a top and a bottom electrode The phase change material stack (or the GST stack) comprises a nitrogen doped GST (NGST) layer on a thin Ta2O5 barrier layer on an undoped GST layer It is demonstrated that each of the phase change layers in the GST stack can be selectively amorphized in using a voltage pulse The differences in resistivities, as well as the different melting and crystallization temperatures of both the NGST and GST layers, contribute to the multi-level switching dynamics of the PCRAM device This enables multi-level resistance switching The thermal conductivity of Ta2O5 with respect to GST is also another factor influencing the multi-level switching Thermal analysis was used to examine the physics behind the multilevel switching mechanism of these devices vii The thermal conductivity and electrical resistivity of the barrier layer affect multi-level switching performance in terms of endurance as well as power consumption A comparison study of SiN and Ta2 O5 dielectric materials was then performed SiN was determined to have better device performance than the Ta2O5 barrier layer and was used in subsequent multi-level PCRAM device fabrications To further improve the performance of the dual layered phase change material (PCM) multi-level device, the top PCM layer was varied in three different splits: Ag0.5In0.5Sb3Te6 (AIST), Ge1Sb4Te7 (GST147), and NGST The intrinsic properties of AIST, GST147 and NGST were used to explain the differences in electrical performance of the three multi-level device splits The AIST/SiN/GST device split was found to have had the best electrical performance The difference in electrical resistivities and thermal conductivities played a major role in the power consumption as well as the resistance values of the three multi-level states in these dual PCM multi-level devices Novel two-bit triple layered PCM multi-level devices comprising of AIST, NGST and GST was then demonstrated The melting and crystallization temperatures of the PCMs play important roles in the power consumption of the multi-level devices The electrical resistivities and thermal conductivities of the PCMs and the SiN thermal barrier are also crucial factors contributing to the phase changing behaviour of the PCMs in the two-bit multi-level PCRAM device The retention characteristics of this two-bit PCRAM device was also discussed viii [13] G Panagopoulos, C Augustine, X Fong, and K Roy, “Exploring Variability and Reliability of Multi-Level STT-MRAM Cells,” 70th Annual Device Research Conference, pp 139-140, 2012 [14] L Jiang, B Zhao, Y Zhang, and J Yang, “Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors,” Proceedings of the 49th Annual Design Automation Conference, pp 907912, 2012 [15] R Leuschner, U K Kolstermann, H Park, F Dahmani, R Dittrich, C Grigis, K Hernan, S Mege, C Park, M C Clech, G Y Lee, S Bournat, L Altimime, and G Mueller, “Thermal select MRAM with a 2-bit cell capability for beyond 65 nm technology node,” IEEE International Electron Devices Meeting, pp 4-7, 2006 [16] S A Wolf, A Y Chtchelkanova, and D M Treger, “Spintronics - A retrospective and perspective,” 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Ge1Sb4Te7-based phase-change memory devices,” IEEE Trans Elect Dev., vol 58, pp 782-791, 2011 [78] X S Miao, L P Shi, H K Lee, J M Li, R Zhai, P K Tan, K G Lim, H X Yang, and T C Chong, “Temperature dependence of phase-change random access memory cell,” Japanese J Appl Phys., vol 45, pp 39553958, 2006 [79] C.-C Chou, F.-Y Hung, and T.-S Lui, “Variation of microstructure and electrical conductivity of amorphous AgInSbTe and SbTe films during crystallization,” Mater Trans., vol 48, pp 610-617, 2007 [80] M Rizzi, A Spessot, P Fantini, and D Ielmini, “Role of mechanical stress in the resistance drift of Ge2Sb2Te5 films and phase change memories,” App Phys Lett., vol 99, 223513, 2011 140 [81] P Fantini, S Brazzelli, E Cazzini, and A Mani, “Band gap widening with time induced by structural relaxation in amorphous Ge2Sb2Te5 films,” App Phys Lett., vol 100, 13505, 2012 [82] D Ielmini, M Boniardi, A L Lacaita, A Redaelli, and A Pirovano, “Unified mechanisms for structural relaxation and crystallization in phasechange memory devices,” Microelectronic Engineering, vol 86, pp 19421945, 2009 [83] T P Leervad Pedersen, J Kalb, W K Njoroge, D Wamwangi, M Wuttig, and F Spaepen, “Mechanical stresses upon crystallization in phase change materials,” Applied Physics Letters, vol 79, pp 3597-3599, 2001 [84] A Gyanathan and Y.-C Yeo, "Phase change random access memory with multi-level resistances implemented using a dual phase change material stack," IEEE Trans Electron Devices, vol 59, no 11, pp 2910 - 2916, 2012 [85] A Gyanathan and Y.-C Yeo, "Two-bit multi-level phase change random access memory with a triple phase-change material stack structure," J Applied Physics, vol 112, no 10, 104504, 2012 [86] A Gyanathan and Y.-C Yeo, "Multi-level phase-change memory cells with SiN or Ta2O5 barrier layers," Extended Abstracts of the 2011 International Conference on Solid State Devices and Materials, pp 146 – 147, 2011 141 [87] A Gyanathan and Y.-C Yeo, "Novel 2-bit multi-level PCRAM structure with a triple-layered phase change material stack for high-density storage applications," International Conference on Solid-State Devices and Materials, pp 604-605, 2012 [88] A Gyanathan and Y.-C Yeo, " Suppression of Resistance Drift in Phase Change Memory using Barrier Layers: Multi-Domain Phase Change Materials,” IEEE Trans Electron Devices – Submitted 142 APPENDIX A List of Publications Journal Publications [51] A Gyanathan, and Y.-C Yeo, “Multi-level phase change memory devices with Ge2Sb2Te5 layers separated by a thermal insulating Ta2O5 barrier layer,” J Applied Physics, vol 110, 124517, 2011 [70] A Gyanathan, and Y.-C Yeo, “Multi-level phase change memory cells with SiN or Ta2O5 barrier layers,” Japanese J Applied Physics, vol 51, 02BD08, 2012 [84] A Gyanathan and Y.-C Yeo, "Phase change random access memory with multi-level resistances implemented using a dual phase change material stack," IEEE Trans Electron Devices, vol 59, no 11, pp 2910 - 2916, 2012 [85] A Gyanathan and Y.-C Yeo, "Two-bit multi-level phase change random access memory with a triple phase-change material stack structure," J Applied Physics, vol 112, no 10, 104504, 2012 [88] A Gyanathan and Y.-C Yeo, " Suppression of Resistance Drift in Phase Change Memory using Barrier Layers: Multi-Domain Phase Change Materials,” IEEE Trans Electron Devices – Submitted 143 Conference Publications [61] A Gyanathan, and Y.-C Yeo, “Novel multi-level PCRAM cell with Ta2O5 barrier layer in between a graded Ge2Sb2Te5 stack,” VLSI-TSA, pp 62-63, 2011 [86] A Gyanathan and Y.-C Yeo, "Multi-level phase-change memory cells with SiN or Ta2O5 barrier layers," Extended Abstracts of the 2011 International Conference on Solid State Devices and Materials, pp 146 – 147, 2011 [87] A Gyanathan and Y.-C Yeo, "Novel 2-bit multi-level PCRAM structure with a triple-layered phase change material stack for high-density storage applications," International Conference on Solid-State Devices and Materials, pp 604-605, 2012 144 ... 122 v 7.1.1 Multi- level dual layered Phase Change Memory Devices with a NGST/Ta2O5/GST Stack …………………… …122 7.1.2 Multi- level phase change memory devices with Si3 N4 or Ta2O5 barrier layers …………………………………….123... of phase change materials for two-bit multi- level devices ………………………………………………… 78 4.4 Chapter Summary ……………………………………………………… 78 Two-bit Multi- level Phase Change Memory Devices with a Triple Phase. .. Materials on the Performance of a Dual Layer Multi- level PCRAM ………….…………………124 7.1.4 Two-bit multi- level phase change memory devices with a triple phase change material stack …………………… 125 7.1.5 Suppression