1. Trang chủ
  2. » Luận Văn - Báo Cáo

Hướng dẫn sử dụng phần mềm Modelsim

44 632 6

Đang tải... (xem toàn văn)

Tài liệu hạn chế xem trước, để xem đầy đủ mời bạn chọn Tải xuống

THÔNG TIN TÀI LIỆU

Thông tin cơ bản

Định dạng
Số trang 44
Dung lượng 3,83 MB

Nội dung

Hướng dẫn sử dụng phần mềm modelsim với hướng dẫn chi tiết cách tạo 1 project với modelsim cách thiêt kế hệ thống số cách mô phỏng thiết kế với modelsim 1.1 Modelsim ModelSim is a verification and simulation tool for VHDL, Verilog, SystemVerilog, and mixedlanguage designs. Software : ModelSimAltera 6.6d Starter Edition References : Introduction to Simulation of Verilog Designs Using ModelSim Graphical Waveform Editor (Altera). ModelSim Tutorial (Mentor Graphics). http:www.altera.com

Trang 1

IC Design Lab

Introduction

Trang 3

1 Introduction

Modelsim Quartus

Trang 4

1 Introduction

1.1 Modelsim

 ModelSim is a verification and simulation tool for

VHDL, Verilog, SystemVerilog, and mixed-language designs.

 Software : ModelSim-Altera 6.6d Starter Edition

Trang 8

2 Design Project

Open the ModelSim simulator In the displayed window select File > New > Project

Trang 9

2 Design Project

A Create Project pop-up box will appear…

1.Enter the name of the project

Choose Project Location

Trang 11

2 Design Project

Double click

Text Editor

Trang 12

2 Design Project

Or add existing file…

Trang 13

2 Design Project

After completed coding, select Compile > Compile all

Compile of majority.v was successfull

Trang 15

3 Simulation

3.1 Simulate without testbench 3.2 Simulate with testbench

Trang 16

3 Simulation

3.1 Simulate without testbench

Select Simulate > Start simulation…, Start Simulation window will appear…

Trang 17

3 Simulation

Simulation window…

Trang 18

3 Simulation

Create waveforms for Simulation…

Trang 19

3 Simulation

Modify waveforms for Simulation…

Trang 20

3 Simulation

Waveform window…

Trang 21

3 Simulation

Waveform window…

Trang 22

3 Simulation

With output signal…

Trang 23

3 Simulation

Simulate…Select Run all

Trang 24

3 Simulation

Result…

To stop simulation, slect Simulate -> End simulation

Trang 25

3 Simulation

3.2 Simulate with testbenchCreate testbench file to project

Trang 26

3 Simulation

After completed coding, select Compile > Compile all

Trang 27

3 Simulation

Add signal to waveform…

Trang 28

3 Simulation

Add signal to waveform…

Trang 29

3 Simulation

Simulate…

Trang 30

3 Simulation

Zoom in, zoom out…

Trang 32

4 Synthesize the design

Open the Quartus In the displayed window select File

> New Project Wizard…

Trang 33

A New Project Wizard box will appear…

1 Directory

2 Name

Trang 34

4 Synthesize the design

Family & Device Settings will appear …

Trang 35

4 Synthesize the design

Trang 36

4 Synthesize the design

Trang 37

4 Synthesize the design

Ctrl + S … save…

Trang 38

4 Synthesize the design

Or add file …

Trang 39

4 Synthesize the design

After coding, select Processing > Start Complation…

Trang 40

4 Synthesize the design

RTL viewer select Tool > Netlist Viewers > RTL

Viewer …

Trang 41

4 Synthesize the design

Assign select Assignments > Pin Planner …

Build

Trang 42

4 Synthesize the design

After Assign, select Toll > Programmer …

Trang 44

Thank You !

Ngày đăng: 28/01/2015, 11:01

TỪ KHÓA LIÊN QUAN

TÀI LIỆU CÙNG NGƯỜI DÙNG

TÀI LIỆU LIÊN QUAN

w