Hướng dẫn sử dụng phần mềm modelsim với hướng dẫn chi tiết cách tạo 1 project với modelsim cách thiêt kế hệ thống số cách mô phỏng thiết kế với modelsim 1.1 Modelsim ModelSim is a verification and simulation tool for VHDL, Verilog, SystemVerilog, and mixedlanguage designs. Software : ModelSimAltera 6.6d Starter Edition References : Introduction to Simulation of Verilog Designs Using ModelSim Graphical Waveform Editor (Altera). ModelSim Tutorial (Mentor Graphics). http:www.altera.com
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Introduction
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Modelsim Quartus
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1.1 Modelsim
ModelSim is a verification and simulation tool for
VHDL, Verilog, SystemVerilog, and mixed-language designs.
Software : ModelSim-Altera 6.6d Starter Edition
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Open the ModelSim simulator In the displayed window select File > New > Project
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A Create Project pop-up box will appear…
1.Enter the name of the project
Choose Project Location
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Double click
Text Editor
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Or add existing file…
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After completed coding, select Compile > Compile all
Compile of majority.v was successfull
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3.1 Simulate without testbench 3.2 Simulate with testbench
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3.1 Simulate without testbench
Select Simulate > Start simulation…, Start Simulation window will appear…
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Simulation window…
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Create waveforms for Simulation…
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Modify waveforms for Simulation…
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Waveform window…
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Waveform window…
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With output signal…
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Simulate…Select Run all
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Result…
To stop simulation, slect Simulate -> End simulation
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3.2 Simulate with testbenchCreate testbench file to project
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After completed coding, select Compile > Compile all
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Add signal to waveform…
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Add signal to waveform…
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Simulate…
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Zoom in, zoom out…
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Open the Quartus In the displayed window select File
> New Project Wizard…
Trang 33A New Project Wizard box will appear…
1 Directory
2 Name
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Family & Device Settings will appear …
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Ctrl + S … save…
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Or add file …
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After coding, select Processing > Start Complation…
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RTL viewer select Tool > Netlist Viewers > RTL
Viewer …
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Assign select Assignments > Pin Planner …
Build
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After Assign, select Toll > Programmer …
Trang 44Thank You !