PHẦN 1: TÍNH TOÁN SONG SONG Chƣơng 1 KIẾN TRÚC VÀ CÁC LOẠI MÁY TINH SONG SONG Chƣơng 2 CÁC THÀNH PHẦN CỦA MÁY TINH SONG SONG Chƣơng 3 GIỚI THIỆU VỀ LẬP TRÌNH SONG SONG Chƣơng 4 CÁC MÔ HÌNH LẬP TRÌNH SONG SONG Chƣơng 5 THUẬT TOÁN SONG SONG PHẦN 2: XỬ LÝ SONG SONG CÁC CƠ SỞ DỮ LIỆU (Đọc thêm) Chƣơng 6 TỔNG QUAN VỀ CƠ SỞ DỮ LIỆU SONG SONG Chƣơng 7 TỐI ƢU HÓA TRUY VẤN SONG SONG Chƣơng 8 LẬP LỊCH TỐI ƢU CHO CÂU TRUY VẤN SONG SONG
Thoai Nam Khoa Coõng Ngheọ Thoõng Tin ẹaùi Hoùc Baựch Khoa Tp.HCM Abstract Machine Models: PRAM, BSP, Phase Parallel Pipeline, Processor Array, Multiprocessor, Data Flow Computer Flynn Classification: SISD, SIMD, MISD, MIMD Pipeline Computer Thoai Nam Khoa Coõng Ngheọ Thoõng Tin ẹaùi Hoùc Baựch Khoa Tp.HCM An abstract machine model is mainly used in the design and analysis of parallel algorithms without worry about the details of physics machines. Three abstract machine models: PRAM BSP Phase Parallel Khoa Coõng Ngheọ Thoõng Tin ẹaùi Hoùc Baựch Khoa Tp.HCM RAM (random access machine) Memory Program Location counter r 0 r 1 r 2 r 3 x 2 x 1 x n x 2 x 1 Write-only output tape Read-only input tape Khoa Coõng Ngheọ Thoõng Tin ẹaùi Hoùc Baựch Khoa Tp.HCM Global memory Private memory Private memory Private memory Parallel random-access machine P 1 P 2 P n Interconnection network Control Khoa Coõng Ngheọ Thoõng Tin ẹaùi Hoùc Baựch Khoa Tp.HCM A control unit An unbounded set of processors, each with its own private memory and an unique index Input stored in global memory or a single active processing element Step: (1) read a value from a single private/global memory location (2) perform a RAM operation (3) write into a single private/global memory location During a computation step: a processor may activate another processor All active, enable processors must execute the same instruction (albeit on different memory location) Computation terminates when the last processor halts Khoa Coõng Ngheọ Thoõng Tin ẹaùi Hoùc Baựch Khoa Tp.HCM Definition: The cost of a PRAM computation is the product of the parallel time complexity and the number of processors used. Ex: a PRAM algorithm that has time complexity O(log p) using p processors has cost O(p log p) Khoa Coõng Ngheọ Thoõng Tin ẹaùi Hoùc Baựch Khoa Tp.HCM Time complexity of a PRAM algorithm is often expressed in the big-O notation Machine size n is usually small in existing parallel computers Ex: Three PRAM algorithms A, B and C have time complexities if 7n, (n log n)/4, n log log n. Big-O notation: A(O(n)) < C(O(n log log n)) < B(O(n log n)) Machines with no more than 1024 processors: log n log 1024 = 10 and log log n log log 1024 < 4 and thus: B < C < A Khoa Coõng Ngheọ Thoõng Tin ẹaùi Hoùc Baựch Khoa Tp.HCM PRAM execution can result in simultaneous access to the same location in shared memory. Exclusive Read (ER) ằ No two processors can simultaneously read the same memory location. Exclusive Write (EW) ằ No two processors can simultaneously write to the same memory location. Concurrent Read (CR) ằ Processors can simultaneously read the same memory location. Concurrent Write (CW) ằ Processors can simultaneously write to the same memory location, using some conflict resolution scheme. [...]... condition: Sum of elements stored in A[0] Global variables: n, A[0 (n-1)], j begin spawn (P0, P1,, Pn /2 -1) for all Pi where 0 i n /2 -1 do for j 0 to log n 1 do if i modulo 2j = 0 and 2i+2j < n the A[2i] A[2i] + A[2i+2j] endif endfor endfor end Khoa Coõng Ngheọ Thoõng Tin ẹaùi Hoùc Baựch Khoa Tp.HCM BSP Bulk Synchronous Parallel BSP Model Proposed by Leslie Valiant of Harvard University Developed... Khoa Tp.HCM 4 7 17 32 3 8 10 2 9 10 15 1 0 5 5 6 3 9 9 9 41 Khoa Coõng Ngheọ Thoõng Tin ẹaùi Hoùc Baựch Khoa Tp.HCM (EREW PRAM Algorithm in Figure2-7, page 32, book [1]) Ex: SUM(EREW) Initial condition: List of n 1 elements stored in A[0 (n-1)] Final condition: Sum of elements stored in A[0] Global variables: n, A[0 (n-1)], j begin spawn (P0, P1,, Pn /2 -1) for all Pi where 0 i n /2 -1 do for j 0... Thoõng Tin ẹaùi Hoùc Baựch Khoa Tp.HCM P1 P2 P3 Superstep 1 Computation Communication Barrier Superstep 2 Computation Communication Barrier Khoa Coõng Ngheọ Thoõng Tin ẹaùi Hoùc Baựch Khoa Tp.HCM P4 Time Complexity of BSP Algorithms Execution time of a superstep: Sequence of the computation, the communication, and the synchronization operations: w + gh + l Overlapping the computation, the communication, . j begin spawn (P 0 , P 1 ,, P n /2 -1 ) for all P i where 0 i n /2 -1 do for j 0 to log n 1 do if i modulo 2 j = 0 and 2i +2 j < n the A[2i] A[2i] + A[2i +2 j ] endif endfor endfor end Khoa. ẹaùi Hoùc Baựch Khoa Tp.HCM 36501 928 34 9510107 91517 9 32 41 Khoa Coõng Ngheọ Thoõng Tin ẹaùi Hoùc Baựch Khoa Tp.HCM (EREW PRAM Algorithm in Figure2-7, page 32, book [1]) Ex: SUM(EREW) Initial. Baựch Khoa Tp.HCM RAM (random access machine) Memory Program Location counter r 0 r 1 r 2 r 3 x 2 x 1 x n x 2 x 1 Write-only output tape Read-only input tape Khoa Coõng Ngheọ Thoõng Tin ẹaùi Hoùc