MANAGING POWER ELECTRONICS VLSl and DSP-Driven Computer Systems phần 3 docx

Buck Converters 61 A, = 6.28 x 30 kHz x 3.6 pH13 mQ = 226 Eq. 3-80 We know the ESR zero to be at 1 kHz fZESR = kHz Eq. 3-81 and fpLc= 1/27~(LC)”* = 116.28 x 4.3 x lo4 = 10000127 = 370 Hz Eq. 3-82 and given VIN= 12 V, VCT= 1 V, a= 1, andGM= 26pN26 mV = 111 kQ we have Rc= 226 x 1 kQ112 = 19 kR Eq. 3-84 Now from fzc = 1 127~RCCc Eq. 3-85 settingfic at 37 Hz ( 1 Ox below the LC double pole) we have C, = 116.28 x 19 kR x 37 = 0.22 pF = 220 nF Eq. 3-86 And so all the main parameters of the control loop are set. Input Filter The input current is chopped as indicated in Figure 3-29 so it will need some input filtering. Input Inductor LIN Assuming that at the input we need a current smoothed down to 0.1 Alps with an input voltage ripple of 0.5 V, we have dV = 0.5 V Eq. 3-87 dlldt = 0.1 Alps Eq. 3-88 62 Chapter 3 Circuits Figure 3-29 Input filter. and from LIN x dlldt = dV 'OUT Eq. 3-89 LIN = 0.5 Vl(0.1 Alps) = 5 pH Eq. 3-90 Input Capacitor 1=20A Eq. 3-91 Eq. 3-92 dlldt = 0.1 Alps hence the time to build up 20 A in the inductor is, from Eq. 3-89 dT = 20 Al(0. 1 Alp) = 200 ps Eq. 3-93 From the formula CIN x dVldt = I Eq. 3-94 Knowing that dVldt = 0.5 Vl200 ps = 2.5 Vlms C = 20 Al(2.5 Vlms) = 8 mF Eq. 3-95 Eq. 3-96 This capacitor has to sustain an RMS current defined as a function of the DC and peak current as follows: IRMs = I(DC - DC2)'12 Eq. 3-97 from which IRMs = 20(0.1 - 0.01)1/2 = 20 x 0.091/2 = 20 x 0.3 = 6 A Eq. 3-98 It is important to select the input capacitor capable of carrying the cal- culated RMS current. Buck Converters 63 Current Mode So far we have analyzed control schemes based on a single control loop, the voltage control loop setting the output voltage. In any regulator when the output is low-say at start-up-the pass transistor will keep charging the output capacitor via the inductor until the output reaches final value. Dur- ing this phase the voltage across the inductor is VIN - VoUr and the current is building in the inductor at a rate [(VIN - VoUT)/L] x t. If this phase lasts too long, the current build up inside the inductor can be excessive. One way to control such build up is cycle-by-cycle current control using a secondary current control loop nested inside the primary voltage control loop. In the current control loop illustration in Figure 3-30 the current in the inductor is limited to VIRDsop Peak Current Control Figure 3-30 Current mode illustration. Another interesting outcome is that now the entire block from the V voltage node to the I, current node (inductor current) becomes a simple trans-conductance block with a transfer function that is simply ~/RD,,N It follows that from a small signal analysis stand point, the inductor effect in the loop is effectively bypassed; the open loop gain loses the LC double pole and is left with only the COuT single pole. In this case the expression of the open loop gain becomes AOL = A"/@C X RDSoN) Eq. 3-100 This is a very simple expression compared to Eq. 3-77. A more com- plicated circuit yields a simpler transfer function! It follows that in princi- ple a current mode regulator should be easier to compensate compared to a plain voltage mode control loop. 64 Chapter 3 Circuits In this section we have covered some fundamental aspects of switching regulators and some general techniques for their analysis. With the tools provided we should be able to pick a PWM controller and match it to the power train and compensation elements. With this foundation the reader can venture into more complex aspects of circuital architecture including leading and trailing edge modulation valley and peak current control PWM versus PFM versus hysteretic control Some of these aspects are discussed in the following chapters. For other aspects not covered here the reader should refer to the references in the further reading section at the end of this book. 3.9 Flyback Converters Figure 3-3 1 shows a simplified block diagram of a flyback converter power train. In this voltage mode flyback architecture the energy is stored in the transformer when the switch SW is on and transferred to the load when the switch is off. The use of a transformer with a turns ration of n: 1 allows a lot of free- dom as far as input versus output value setting. In a flyback converter the transformer stores energy during the on time of the SW 1 transistor. The inductor windings are coupled in such a way (opposite windings as indi- cated by the dots on each transformer winding) that voltage on the two windings are of the opposite sign. This arrangement, coupled with the placement of diode D (we will approximate the forward drop of the diode to zero), is such that when current flows in the primary winding, it cannot flow in the secondary. Accordingly the energy associated with the primary current cannot be transferred to the secondary and it is stored in the trans- former air gap. When the switch is open, the current ceases to circulate in the primary and the energy stored in the transformer gap releases via a cur- rent in the secondary. If the voltage on the secondary is VouT (assured by the control loop not shown here) then this voltage will reflect back on the primary via the turns ration, hence the voltage across the transformer pri- mary will be -nVo. This voltage subtracts to VfN so that the final voltage across the open switch SW during the off phase is Vsw = VfN - (-nVo) = VIN + nVo Eq. 3-101 This observation is important because the switch SW is most likely going to be a DMOS transistor and its voltage rating will have to be Flyback Converters 65 ‘sw ‘R drk VS “IN,, Figure 3-31 Flyback converter simplified block diagram and waveforms. selected to be safely above VIN + nVo. On the secondary side, the average of the secondary current waveform I, is the load current. The picture shows the case of light load, with secondary current reaching zero when the primary switch SW is still off. In the absence of current on the second- ary there is no voltage on the secondary and no reflected voltage on the primary side, hence during this time interval the voltage across the pri- mary winding is zero and the voltage across the switch SW is simply VIM The control loop and its analysis techniques are similar to the one dis- cussed for the buck converter and will not be repeated here. The other advantage of the transformer, besides input-to-output volt- age ratioing, is isolation. In high voltage applications isolation is mandatory not only in the forward path, but also in the feedback path. For this reason transformers in the forward path are a must in offline applica- tions, while in the feedback path often opto-couplers (Figure 3-32) are uti- lized for signal isolation. In an opto-coupler the photo-diode emits light proportionally to its bias current. A portion of this light hits the corre- sponding phototransistor which in turn produces a current variation pro- portional to the incoming light. Since the coupling mechanism is based on light, the opto-coupler works with AC as well as DC feedback signals. In the following chapters we will encounter a few examples of such isolated architectures. A conventional transformer is called to transfer energy, not store it, so it does not normally have an air gap, which is the place where energy is stored. In the flyback configuration, the transformer is hybridized to have an air gap and store energy as discussed earlier. For this reason this “transformer” is also referred to as a “coupled inductor” since the two windings, due to the energy storage twist, act essentially like inductors. Figure 3-33 is a nice illustration of the transformer femte core and its energy storage air gap. 66 Chapter 3 Circuits Figure 3-32 Symbol of opto-coupler. Figure 3-33 Gapped transformer illustration. As with non-isolated converters, there is a long list of isolated con- verter architectures as well. We will encounter some of these architectures in the next chapters. For a more systematic treatment of these architectures the reader can refer to the provided references. Part II Digital Circuits In this section we will discuss some fundamental digital building blocks for power management. We will quickly review the main properties of the elementary components, the logic gates, so that we can use them to build higher level functions like flip-flops, shift registers, and communications input and output functions. There are many good reasons to mix analog and digital circuits. Soon we will see an example where adding a flip-flop to an analog regulation loop improves the noise insensitivity of the circuit. Logic Functions 67 Today's power management devices are often externally driven by a central processing unit. In order to interface with such CPUs, power man- agement chips may include on board some or all of the logic elements mentioned above in the form of input-output communications cells. Finally digitalization of power, as will be discussed in detail later, is another reason for a mixed analog and digital approach to power management. 3.1 0 Logic Functions NAND Gate In Figure 3-34 we have a fundamental logic block, the NAND gate with its symbol, CMOS implementation, and truth table, the equivalent of the input to output transfer function we have for an analog block. The truth table can be easily proven by exercising it on the CMOS implementation schematic. "cc TI ? T2 - C=A’B I 0- * T3 __c_( T4 Figure 3-34 Logic NAND gate (a) symbol, (b) CMOS implementation, and (c) truth table. 68 Chapter 3 Circuits Set-Reset R Flip-Flop In Figure 3-35 we have put to use the NAND gates to build a Set-Reset Flip-Flop, or to be more precise, a Set#-Reset# one (# stands for the nega- tion bar), the most elementary memory cell. In the truth table M stands for the memory state; when Set# = Reset# = 1 the output stays in the previous state. Naturally one inverter in front of each input will produce a Set-Reset Flip-Flop with the table shown in Figure 3-36. (a) (b) Figure 3-35 Set#-Reset# Flip-Flop (a) logic schematic and (b) truth table. (a) (b) Figure 3-36 Set-Reset Flip-Flop (a) symbol and (b) truth table. Current Mode with Anti-Bouncing Flip-Flop In Figure 3-37 we have put to use the Set-Reset Flip-Flop by inserting it into the current mode voltage control loop from Figure 3-30. The circuit in Figure 3-30 is subject to noise as the comparator can be triggered by any noise spike at any time. By inserting the flip-flop in the loop we create Logic Functions 69 a synchronous system that is insensitive to noise. In fact, from Figure 3-37 and the table in Figure 3-36(b) we see that once reset is triggered (a spike to one and back to zero) the flip-flop is in a memory state until the next set spike. Hence a new charging cycle cannot be initiated by false triggering of the comparator. Peak Current Control LRIPPLE V, IL.RDSON CLOCK = SET COMPO = RESET PWM Figure 3-37 Current control with anti-bounce Set-Reset Flip-Flop. This Page Intentionally Left Blank [...]... switching node of Phase I Bottom waveform: Phase 1 current I FAN50 93 f R16 Monolithic Buck Converter 79 to handle 30 A with 3. 3 V For further details, a f u l l data sheet of the FAN50 93 is provided in Appendix A The IC is built in a 30 V, 0.8 pm BiCMOS mixed signal process with excellent Bipolar and C M O S performance Figure 4-8 FAN50 93 die picture Conclusion We have shown that the valley current-mode... iterations at the full chip level and gave the customer preliminary results six months ahead of functional silicon Conclusion Behavioral models of voltage regulators and power management subsystems already are a reality These models increase productivity, reduce the number of simulations and silicon and system iterations, and require less time to design Finally, the speed and simplicity inherent in the... fifth section we will cover the subject of digital power, a new trend of implementing power with digital techniques in place of traditional analog ones 4.1 Valley Control Architecture Modern CPUs require very low voltage of operation (1.5 V and below) and very high currents (up to 100 A) Such power comes more and more frequently from the silver box, a power supply device typically used inside a desktop... tolerance band, the clamp activates to hold the output voltage within this specified band As such, the active clamp must be designed to handle the full load current, but only for short intervals on the order of tens of microseconds Hence, the active clamp circuit must be designed for high peak current and high peak power capability but need not handle significant continuous steady state power In order... waveform: switching node of Phase 1 Bottom waveform: Phase 1 current wanted to parallel and operate them out of phase Now we have reduced input and output ripple, and hence we can get by with smaller input and output passives The IC whose die layout is shown in Figure 4-8 incorporates the controller and the drivers and works in conjunction with an external DMOS transistor 78 Chapter 4 DC-DC Conversion... case is a high current buck converter for desktop, handling high current and thus requiring external power MOSFET transistors The emphasis here will be on the advantages of a specific architecture for this application, called vulley control The second case is a low current buck converter for ultraportable applications For such low power applications, the power transistors are integrated on board In this... scenario in which duty cycle saturation does not play a role With an aggressive crossover frequency of 100 kHz, Co = 20 pF, and a load step of 10 A, the peak voltage transient is 800 mV With a +5 percent tolerance band of about 3. 3 V, this peak voltage is unacceptable since the tolerance band amounts to only +165 mV With the same conditions, except for an output capacitance Co = 200 pF, we see a voltage peak... is running at about its nominal output of 3. 3 V with an output ripple of about 50 mV peak-peak and an approximate frequency of 30 0 kHz A time-scale blowup of this transient is shown in Figure 4-24(b), where the scale is 200 ns/division In this figure, we can see the voltage spike due to the parasitic inductance (ESL) associated with the output capacitance and layout As evidenced by the waveform for... 4-24(a) and (b) are shown i n Figure 4-24(c) and( d) For the latter two photos, the DC-DC converter supports a 3 A steady state load, which is interrupted The upper clamp function behaves analogously to the lower clamp function Figure 4-24(a) illustrates the clamp function under 3 A step load The upper waveform is the output node The dashed horizontal trace depicts the upper clamp reference level of 3. 45... between inactive and active modes, or vice versa We will discuss some of the ramifications for the design of the power supply required to supply these microprocessor loads We focus on the use of a paralleled active circuit, which can be thought of as an active clamp, the details of which are explained in the next paragraph Breadboards of these circuits have been built and tested, and a prototype IC . inductors. Figure 3- 33 is a nice illustration of the transformer femte core and its energy storage air gap. 66 Chapter 3 Circuits Figure 3- 32 Symbol of opto-coupler. Figure 3- 33 Gapped transformer. 6.28 x 30 kHz x 3. 6 pH 13 mQ = 226 Eq. 3- 80 We know the ESR zero to be at 1 kHz fZESR = kHz Eq. 3- 81 and fpLc= 1/27~(LC)”* = 116.28 x 4 .3 x lo4 = 10000127 = 37 0 Hz. 0- * T3 __c_( T4 Figure 3- 34 Logic NAND gate (a) symbol, (b) CMOS implementation, and (c) truth table. 68 Chapter 3 Circuits Set-Reset R Flip-Flop In Figure 3- 35 we have