Introduction to Electronics - Part 5 pot

Introduction to Electronics 99 Other FET Considerations D G B S Fig. 151. Zener-diode gate protection of a MOSFET. D G S Fig. 152. Normal MOSFET body- source connection. Other FET Considerations FET Gate Protection The gate-to-channel impedance (especially in MOSFETs) can exceed 1 G Ω !!! To protect the thin gate oxide layer, zeners are often used: Zeners can be used externally, but are usually incorporated right inside the FET case. Many FET device types available with or without zener protection. Zener protection adds capacitance, which reduces FET performance at high frequencies. The Body Terminal In some (rare) applications the body terminal of MOSFETs is used to influence the drain current. Usually the body is connected to the source terminal or a more negative voltage (to prevent inadvertently forward-biasing the channel-body parasitic diode). Introduction to Electronics 100 Basic BJT Amplifier Structure + + + + - - R B R C V CC V BB v in + - + - + - v CE v BE i C i B Fig. 153. Basic BJT amplifier structure. VviRv BB in B B BE += + (122) i B v BE V BB V BB / R B V BB + v in max V BB - v in max i B max I BQ i B min Q Fig. 154. Load-line analysis around base-emitter loop. ViRv CC C C CE =+ (123) Basic BJT Amplifier Structure Circuit Diagram and Equations The basic BJT amplifier takes the form shown: KVL equation around B-E loop: KVL equation around C-E loop: Load-Line Analysis - Input Side Remember that the base-emitter is a diode . The Thevenin resistance is constant , voltage varies with time, but the Thevenin. Thus, the load line has constant slope (-1/ R B ), and moves with time . Introduction to Electronics 101 Basic BJT Amplifier Structure i B v BE V BB V BB / R B V BB + v in max V BB - v in max i B max I BQ i B min Q Fig. 155. Load-line analysis around base-emitter loop (Fig. 154 repeated). ● The load line shown in red for v in = 0. When v in = 0, only dc remains in the circuit. This i B , v BE operating pt. is called the quiescent pt . The Q-point is given special notation: I BQ , V BEQ ● Maximum excursion of load line with v in is shown in blue. ● Minimum excursion of load line with v in is shown in green. ● Thus, as v in varies through its cycle, base current varies from i B max to i B min . The base-emitter voltage varies also, from v BE max to v BE min , though we are less interested in v BE at the moment. Introduction to Electronics 102 Basic BJT Amplifier Structure + + + + - - R B R C V CC V BB v in + - + - + - v CE v BE i C i B Fig. 156. Basic BJT amplifier structure (Fig. 153 repeated). Fig. 157. Amplifier load line on BJT output characteristics. Load-Line Analysis - Output Side Returning to the circuit, observe that V CC and R C form a Thevenin equivalent, with output variables i C and v CE . Thus we can plot this load line on the transistor output characteristics!!! Because neither V CC nor R C are time-varying, this load line is fixed !!! Introduction to Electronics 103 Basic BJT Amplifier Structure Fig. 158. Amplifier load line on BJT output characteristics (Fig. 157 repeated). ● The collector-emitter operating point is given by the intersection of the load line and the appropriate base current curve . . . when v in = 0, i B = I BQ , and the quiescent pt. is I CQ , V CEQ at v in max , i B = i B max , and the operating pt. is i C max , v CE min at v in min , i B = i B min , and the operating pt. is i C min , v CE max ● If the total change in v CE is greater than total change in v in , we have an amplifier !!! Introduction to Electronics 104 Basic BJT Amplifier Structure + + + + - - R B = 10 k Ω V CC = 10 V V BB = 1 V v in = 0.1 sin ω t V + - + - + - v CE v BE i C i B R C = 1 k Ω Q 1 2N2222 Fig. 159. Example circuit illustrating basic amplifier structure. Fig. 160. PSpice-simulated 2N2222 input characteristic. A Numerical Example Let’s look at a PSpice simulation of realistic circuit: First we generate the input characteristic and draw the appropriate base-emitter circuit load lines: Introduction to Electronics 105 Basic BJT Amplifier Structure Fig. 161. 2N2222 output characteristics, with curves for base currents of (from bottom to top) 4 µA, 13 µA, 22 µA, 31 µA, 40 µA, and 49 µA. A v v !!! v CE in == =− ∆ ∆ 2.95 V - 6.11V V02 15 8 . . (124) Using the cursor tool in the PSpice software plotting package, we determine: i B min = 22 µA I BQ = 31 µA i B max = 40 µA Next we generate the output characteristics and superimpose the collector-emitter circuit load line: The resulting collector-emitter voltages are: v CE min = 2.95 V V CEQ = 4.50 V v CE max = 6.11 V Finally, using peak-to-peak values we have a voltage gain of: Introduction to Electronics 106 Basic BJT Amplifier Structure Fig. 162. Input waveform for the circuit of Fig. 159. Fig. 163. Output (collector) waveform for the circuit of Fig. 159. Of course, PSpice can give us the waveforms directly (and can even give us gain, if we desire): Introduction to Electronics 107 Basic FET Amplifier Structure + + - V DD = 15 V V BB = -1 V v in = 0.5 sin ω t V + - + - + - v DS v GS i D R D = 1 k Ω J 1 2N3819 Fig. 164. Basic FET amplifier structure. Vvv GG in GS += (125) ViRv DD D D DS =+ (126) Basic FET Amplifier Structure The basic FET amplifier takes the same form as the BJT amplifier. Let’s go right to a PSpice simulation example using a 2N3819 n - channel JFET: Now, KVL around the gate-source loop gives: while KVL around the drain-source loop gives the familiar result: Because i G = 0, the FET has no input characteristic, but we can plot the transfer characteristic , and use eq. (125) to add the appropriate load lines. In this case, the load line locating the Q point, i.e., the line for v in = 0, is called the bias line : Introduction to Electronics 108 Basic FET Amplifier Structure Fig. 165. PSpice-generated 2N3819 transfer characteristic showing the bias line, and lines for v GS min and v GS max . vi GS D min min =− ⇒ = 15 3 00VmA (127) VI GSQ DQ =− ⇒ = 10 5 30 VmA (128) vi GS D max max =− ⇒ = 05 822VmA (129) From the transfer characteristic, the indicated gate-source voltages correspond to the following drain current values: Note, however, that we could have gone directly to the output characteristics, as the parameter for the family of output curves is v GS : [...]... Structure Introduction to Electronics 109 Fig 166 2N3819 output characteristics, with curves for gate-source voltages of (from bottom to top) -3 V, -2 .5 V, -2 V, -1 .5 V, -1 V, -0 .5 V, and 0 V From the output characteristics and the drain-source load line, the indicated gate-source voltages correspond to the following drain-source voltage values: v GS min = − 15 V VGSQ = −10 V v GS max = −0 .5 V ⇒ = 12.0... BJTs - The Four-Resistor Bias Circuit 1 15 Introduction to Electronics Biasing BJTs - The Four-Resistor Bias Circuit Introduction This combines features of fixed bias and constant base bias, but it takes a circuit-analysis “trick” to see that: VCC R1 RC R1 RC + VCC - - VCC RE R2 RE R2 + Fig 173 Equivalent after “trick” with supply voltage Fig 172 The four-resistor bias circuit RC RB VBB + - + - VCC... point along the output-side load line ventures too close to the saturation or cutoff regions for the BJT (the triode or cutoff regions for the FET), as the following example illustrates: RD = 1.3 kΩ iD vin = 1 .5 sin ωt V + + VBB = -1 .5 V + vDS + vGS - J1 2N3819 + - VDD = 15 V - Fig 168 Slight changes to the FET amplifier example to illustrate nonlinear distortion Fig 169 Severely distorted output waveform... divider A KVL equation around gate-source loop provides the bias line: v GS = VG − i DRS ( 154 ) And, as usual, assuming operation in the pinch-off region: i D = K (v GS − VP ) 2 Simultaneous solution provides Q-point - see next page ( 155 ) Biasing FETs - The Fixed + Self Bias Circuit 122 Introduction to Electronics iD High-current device Bias line vGS = VG - RS iD IDQ IDQ Low-current device vGS Intercept... BJTs - The Fixed Bias Circuit Introduction to Electronics 113 Biasing BJTs - The Fixed Bias Circuit VCC RB RC iC + vCE - Example We let VCC = 15 V, RB = 200 kΩ, and RC = 1 kΩ β varies from 100 to 300 To perform the analysis, we assume that operation is in the active region, and that VBE = 0.7 V Fig 170 BJT fixed bias circuit For β = 100: IB = VCC − VBE 15 V - 0.7 V = = 7 15 µA RB 200 kΩ IC = βIB = 7. 15. .. - + - VCC RE Fig 174 Final equivalent after using Thevenin’s Theorem on base divider Biasing BJTs - The Four-Resistor Bias Circuit Introduction to Electronics 116 Circuit Analysis RC RB VBB + VCC - + RE - Fig 1 75 Four-resistor bias circuit equivalent (Fig 174 repeated) Analysis begins with KVL around b-e loop: VBB = IBRB + VBE + IE RE (142) But in the active region IE = (β + 1)IB : VBB = IBRB + VBE... VBE By letting VBB >> VBE Rule of Thumb: 1 let VRC ≈ VCE ≈ VRE ≈ VCC 3 Because VR ≈ VBB if VBE and IB are small E Biasing BJTs - The Four-Resistor Bias Circuit Introduction to Electronics 118 Example 15 V R1 10 kΩ RC RC 1 kΩ R B = 3.3 kΩ + RE R2 5 kΩ 1 kΩ - 1 kΩ 15 V + - 5 V RE 1 kΩ Fig 176 Example circuit Fig 177 Equivalent circuit For β = 100 (and VBE = 0.7 V): IB = VBB − VBE = 412 µA RB + (β +... 141 µA RB + (β + 1)RE ⇒ IE = IC = 4. 25 mA α ⇒ IC = βIB = 4.24 mA ⇒ VCE = VCC − IC RC − IE RE = 6 .50 V Thus we have achieved a reasonable degree of bias stability ( 150 ) ( 151 ) Biasing FETs - The Fixed Bias Circuit Introduction to Electronics 119 Biasing FETs - The Fixed Bias Circuit VDD RD + vGS RG iD + vDS - - + Just as the BJT parameters b and VBE vary from device to device, so do the FET parameters... Thus, using peak -to- peak values, we have a voltage gain of: Av = ∆v DS 6.78 V - 12.0 V = = 5. 22 ∆v GS 1V !!! (133) Amplifier Distortion Introduction to Electronics 110 Amplifier Distortion Let’s look at the output waveform (vDS ) of the previous example: Fig 167 Output (drain) waveform for the FET amplifier example Can you discern that the output sinusoid is distorted ? The positive half-cycle has an... formula (though a good guess often works) - the higher current solution is invalid (why?) Biasing FETs - The Fixed + Self Bias Circuit 121 Introduction to Electronics Biasing FETs - The Fixed + Self Bias Circuit This is just the four-resistor bias circuit with a different name!!! V DD R1 V DD RD RD RG R2 RS Fig 182 Fixed + self-bias circuit for FETs VG iD + v DS - + - RS Fig 183 Equivalent circuit after . : Introduction to Electronics 109 Basic FET Amplifier Structure Fig. 166. 2N3819 output characteristics, with curves for gate-source voltages of (from bottom to top) -3 V, -2 .5 V, -2 V, -1 .5. though less prominently so . . . Introduction to Electronics 111 Amplifier Distortion + + - V DD = 15 V V BB = -1 .5 V v in = 1 .5 sin ω t V + - + - + - v DS v GS i D R D = 1.3 k Ω J 1 2N3819 Fig drain-source load line, the indicated gate-source voltages correspond to the following drain-source voltage values: Thus, using peak -to- peak values, we have a voltage gain of: Introduction to Electronics