Micro Electro Mechanical System Design - James J. Allen Part 3 docx

40 Micro Electro Mechanical System Design • Easy to start and stop the etch process • Repeatable etch process • Anisotropic etches • Few particulates Plasma etching includes a large variety of etch processes and associated chemistries that involve varying amounts of physical and chemical attack. The plasma provides a flux of ions, radicals, electrons, and neutral particles to the surface to be etched. Ions produce physical and chemical attack of the surface, FIGURE 2.21 Directional etching of crystalline silicon. TABLE 2.6 Common Crystalline Silicon Etchant Selectivity and Etch Rates Etchant Etch rate 18HF + 4HNO 3 + 3Si → 2H 2 SiF 6 + 4NO + 8H 2 O Nonselective Si +H 2 O 2 + 2KOH → K 2 SiO 3 + 2H 2 {100} 0.14 µm/min {111} 0.0035 µm/min SiO 2 0.0014 µm/min SiN 4 not etched Ethylene diamine pyrocatechol (EDP) {100} 0.75 µm/min {111} 0.021 µm/min SiO 2 0.0002 µm/min SiN 4 0.0001 µm/min Tetramethylammonium hydroxide (TMAH) {100} 1.0 µm/min {111} 0.029 µm/min SiO 2 0.0002 µm/min SiN 4 0.0001 µm/min φ=54.7° φ [111] [100] SiO 2 mask © 2005 by Taylor & Francis Group, LLC Fabrication Processes 41 and the radicals contribute to chemical attack. The sequence of events that occur in a plasma etch chamber ( Figure 2.23) are listed below: • Plasma breaks down the feed gases into chemically reactive species. • Reactive species diffuse to the wafer surface and are adsorbed. • Surface diffusion of reactive species takes place until they chemically react. • Reaction product desorption occurs. • Reaction products diffuse away from the surface. • Reaction products are transported out of the chamber The details and types of etch chemistries involved in plasma etching are varied and quite complex. This topic is too voluminous to be discussed in detail here, but a number of excellent references on this subject are available [3,4]. The proper choice of these chemistries produces various etch rates and selectivity of material etch rates, which is essential to the integration of processes to produce micro- FIGURE 2.22 Boron-doped silicon used to form features or an etch stop. B B B B B B B B B B B B B B B B B B B B B B B B Single Crystal Silicon a. Implant Boron in Single Crystal Silicon wafer [100] b. Deposit and Pattern Silicon Dioxide Etch Mask SiO 2 mask B B B B B B B B B B B B B B B B B B B B B B B B [111] B B B B B B B B B B B B B B B B B B B B B B B B c. KOH etch © 2005 by Taylor & Francis Group, LLC 42 Micro Electro Mechanical System Design electronics or MEMS devices. Fluoride etch chemistries are one of the most widely studied for silicon etches. Equation 2.6 through Equation 2.8 illustrate some of the fluoride reactions involved in the etching of silicon, silicon dioxide, and silicon nitride, respectively. A number of feed gases can produce the free radicals involved in these reactions. (2.6) (2.7) (2.8) The anisotropy of the plasma etch can be increased by the formation of nonvolatile fluorocarbons that deposit on the sidewalls. This process is called polymerization and is controlled by the ratio of fluoride to carbon in the reactants. The side wall deposits produced by polymerization can only be removed by physical ion collisions. Etch products from the resist masking are also involved in the polymerization. End point detection of an etch is important in controlling the etch depth or minimizing the damage to underlying films. This detection is accomplished by analysis of the etch effluents or spectral analysis of the plasma glow discharge. Types of plasma etches include reactive ion etching (RIE) and high-density plasma etching (HDP). RIE etching utilizes a low-pressure plasma. Chlorine (Cl)- based plasmas are commonly used to etch silicon, GaAs, and Al. RIE etching may damage the material due to the impacts of the ions; this can be removed by annealing at high temperatures. HDP etches utilize magnetic and electric fields FIGURE 2.23 Schematic of a plasma etch chamber. Si F SiF+ →4 4 * 3 4 2 2 3 2 3 2 4 SiO CF CO CO SiF+ → + + + Si N F SiF N 3 4 4 2 12 3 2+ → +* © 2005 by Taylor & Francis Group, LLC Fabrication Processes 43 to increase dramatically the distance that free electrons can travel in the plasma. HDP etches have good selectivity of Si to SiO 2 and resist. 2.5.3 ION MILLING Ion milling is a purely physical etching process; no chemical reactions are involved. Ion milling uses noble gases with significant mass such as argon in a process analogous to sputtering. This process is very isotropic because the ion impinges the surface nearly vertically. However, the process has an etch rate selectivity of the material to be etched to the mask material of nearly 1:1 because the process is purely physical. Ion milling is not widely used for production applications, and it is generally limited to the smaller wafer sizes (<200 mm). The etch rates can be increased by increasing the ion densities impacting the surface through the use of magnetic fields. 2.6 PATTERNING The ability to pattern deposited layers is an essential capability required in microelectronics and MEMS processing. Three widely utilized methods of pat- terning will be discussed: lithography, the lift-off process, and the damascene process. Lithography is the mainstream process utilized for patterning in MEMS processes. Lift-off and damascene are processes used for patterning materials in which a reliable etch process such as metallization layers or optical coating layers does not exist. These are frequently required in the postprocessing of MEMS devices. The current research and development in patterning for very fine line widths (<0.35 µm) involve the development of sophisticated tools such as x-ray lithog- raphy [7] or direct-write E-beam lithography [8]. Microelectronics will need the capability to pattern features (line widths) of this size in the future in order to continue development of microelectronic devices of increasing speed and capa- bility. However, mainstream MEMS technology does not currently require such fine features, so these methods will not be discussed here. 2.6.1 LITHOGRAPHY Lithography is the most widely used method to pattern layers in microelectronic and MEMS processing. Figure 2.24 is a schematic of a basic lithography system. The basic components of a photolithographic system include: • Illumination source • Shutter • Mask • Wafer alignment/support system • Photosensitive layer (photoresist or “resist”) on a wafer © 2005 by Taylor & Francis Group, LLC 44 Micro Electro Mechanical System Design Lithography is the most critical process in microelectronics and MEMS processes, and the equipment is generally the most costly in a microelectronics or a MEMS fabrication facility. For example, a microelectronic process will require 20 or more lithography steps, and a surface micromachine process will require 10 or more lithography steps. A lithography process step will generally require application and prebaking of the photoresist to harden the resist; the exposure of the photoresist in the lithography tool; development of the photoresist; and a postbake of the photoresist to fully harden the resist to define the feature accurately. Thus, a lithography step requires several subprocesses that are repeat- edly performed to fabricate a MEMS or microelectronic device. The other pro- cessing steps required in a MEMS or microelectonic fabrication may go through different tools for a specific deposition or a particular type of etch, but lithography is the common tool that will always be used. Therefore, lithography is the critical path in the fabrication facility and much attention is paid to the development of technology and enhancements that can speed this process step. The performance metrics most important to lithographic processing are res- olution, registration, and processing throughput. The resolution for optical lithog- raphy is very closely tied to the wavelength of the illumination source. The development of lithographic equipment has used ever decreasing wavelength illumination from the visible spectrum to ultraviolet (UV) and on to the research and development use of extreme ultraviolet (EUV). The design of the optical system of the lithographic equipment is very com- plex, as can be illustrated by the discussion of a few key parameters of the optical system. The minimum line width, W min , capability of the lithographic system can be expressed by Equation 2.9, which is very similar to the Raleigh criteria [9] for optical resolution: FIGURE 2.24 Lithography system schematic. resist optical system mask shutter illumination source alignment stage wafer © 2005 by Taylor & Francis Group, LLC Fabrication Processes 45 (2.9) where W min = minimum line width K = a measure of the ability of the photoresist to distinguish changes in intensity λ = illumination source wavelength NA = numerical aperture The numerical aperture defined by Equation 2.10 is a function of the refractive index, n, of the medium between the objective and wafer and the half angle of the image, α: (2.10) Another optical parameter of interest in the design of the lithographic system is the depth of focus, σ (Equation 2.11). The depth of focus is an issue in MEMS fabrication due to the thickness of the films involved and the possible wafer warpage due to residual stress of the deposited films. Films involved in MEMS processes can be several microns thick. Patterning of the various layers will give rise to topographic features on the wafers. When photoresist is spread on a wafer containing these topographical features or the wafer is warped due to film residual stress, the lithographic process will attempt to expose the photoresist at various heights, thus making the depth of focus capability a critical issue. (2.11) As can be seen from this limited subset of the optical design parameters, the optical design is complex and the design parameters interrelated. For example, to make W min smaller, utilizing a smaller wavelength source, λ, and a larger NA would be beneficial; however, the depth of focus, σ, will be reduced as a result. Masks contain the patterns that need to be etched into the material to imple- ment the MEMS design. The masks can be the same size (1:1) as the patterns to be transferred and etched into the MEMS material. Depending on the lithographic system, the masks may be larger than the patterns to be etched into the material. Masks are typically 1×, 5×, or 10× larger than the patterns to be imaged and etched. The mask is made of materials (e.g., fused silica) that are transparent at the illumination wavelength, with the patterns defined by an opaque material (e.g., chromium) at the illumination wavelength. The mask will need to be very flat and insensitive to changes in temperature (e.g., small coefficient of thermal W K NA min ≈ λ NA n= sin α σ λ = NA 2 © 2005 by Taylor & Francis Group, LLC 46 Micro Electro Mechanical System Design expansion, α T ). Contamination control is also an issue in the lithography process. For example, masks may have a pellicle membrane (Figure 2.25) held above the patterned area to keep particles off the mask surface and out of the image plane of the mask to prevent degradation of the lithographic image. Photoresist is a photosensitive organic compound applied to the wafer surface. The photoresist consists of three components: • Resin material is organic material that forms the bulk material of the photoresist that will affect the durability during subsequent processing and resolution of the photoresist. • Photoactive compound is the photosensitive material that determines the sensitivity of the photoresist (mJ/cm 2 ) to the illumination needed to produce a chemical change. • Solvent is the component affecting the viscosity of the resist that affects the application of photoresist, which is generally done by spinning the wafer and using centrifugal force to spread the photoresist to a uniform thickness. The solvent in the resist is then removed during the baking steps to make the material structurally rigid. FIGURE 2.25 Photomask with pellicle. © 2005 by Taylor & Francis Group, LLC Fabrication Processes 47 The lithographic process will transfer the image from the mask to photoresist on the wafer surface. Two types of photoresist can be used: • Negative resist. The region of photoresist that has not been exposed to the illumination will dissolve during the development process and be removed. • Positive resist. The region of photoresist that has been exposed to the illumination will dissolve during the development process and be removed. Positive resist has the best resolution and is more widely used. After it is exposed and developed, the photoresist will be used as a physical mask during subsequent etching processes to transfer the pattern in photoresist on to the thin film of MEMS material beneath the photoresist. Photoresist is a key material in the lithographic processing sequence as well as the subsequent etch steps. It must have a diverse set of properties to enable the definition of the pattern and also maintain physical integrity during subsequent etching processes. The aligner is the piece of mechanical equipment that supports the litho- graphic optical system and mask. It will align the masks relative to target patterns on the wafer; this will have the effect of aligning the masks and their subsequently etched patterns on the wafer with the mask and patterns utilized later in the fabrication sequence. Figure 2.26 shows a typical alignment target, which is typically specified by the lithographic system manufacturer. Two general types of aligners will be considered here: • Contact/proximity aligner. The mask is held in contact or close prox- imity (a few microns) of the photoresist surface. These aligners utilize 1× masks and do not have pellicles due to the lack of available clear- ance between the mask and photoresist. The contact aligner actually FIGURE 2.26 Example of a lithographic alignment target. © 2005 by Taylor & Francis Group, LLC 48 Micro Electro Mechanical System Design presses the mask under pressure against the photoresist, which will have the effect of degrading the mask under repeated use. This category of aligner is the least expensive, and has the lowest resolution capa- bility. These aligners are generally used for research or limited pro- duction applications. • Projection aligner. The mask and wafer are separated as dictated by the design of the optical system. This class of aligner can have high resolution that is only limited by optical system performance. These systems can be very expensive and are utilized in high-volume manufacturing. 2.6.2 LIFT-OFF PROCESS Lift-off is a patterning process frequently used in MEMS for patterning materials that do not possess a reliable process to etch them (e.g., noble metals). The lift- off process is accomplished via the use of an intermediate layer and deposition process, which has poor step coverage. Figure 2.27 is a schematic of a lift-off process that will deposit and pattern a material on a substrate or underlying layer. This process involves the following steps: • Deposit and pattern a thick intermediate layer of a material that is easy to remove (e.g., SiO 2 or photoresist) and that will have a slightly reentrant profile. • Deposit a layer of the material to be patterned utilizing a process that has poor step coverage (e.g., evaporation). The material thickness should be a fraction of the intermediate layer thickness. FIGURE 2.27 Lift-off process schematic. patterned SiO 2 /resist evaporated metal layer substrate a. Evaporated metal layer on a patterned SiO 2 or resist layer b. Strip the SiO 2 or resist layer leaving the metal on the substrate © 2005 by Taylor & Francis Group, LLC Fabrication Processes 49 • Removal of the intermediate layer will cause the metal layer to fracture due to the stress concentration in the region of poor step coverage. Alternatively, the lift-off process can involve a process that will explicitly form an undercut metal layer and not rely on the metal layer to fracture at the step. Figure 2.28 is a schematic of a process that will involve the explicit devel- opment of an undercut region: • Deposit thick intermediate layer of a material (e.g., SiO 2 ). • Deposit and pattern a layer of photoresist. • Undercut the photoresist with a process such as wet chemical etching. • Deposit a layer of the material to be patterned utilizing a process that has poor step coverage (e.g., evaporation). The material thickness should be a fraction of the photoresist and oxide layers. • Remove the SiO 2 and photoresist, which will leave only the patterned metal layer. FIGURE 2.28 Lift-off process schematic with undercut metal layer. resist substrate (a) Substrate with an oxide layer and patterned resis t (b) Wet etch oxide layer to undercut the resist layer (c) Evaporate metal layer metal (d) Strip resist (e) Remove oxide SiO 2 © 2005 by Taylor & Francis Group, LLC [...]... for Diffusion Sources Dopant Gaseous Liquid Solid Arsenic Phosphorus Boron AsH3.AsF3 PH3,PF3 B2H6, BF3, BCl3 Arsenosilica POCl3, phosphosilica BBr3, (CH3O)3B, borosilica AlAsO4 NH4H2PO4, (NH4)2H2PO4 BN FIGURE 2 .37 Diffusion with a silicon dioxide mask © 2005 by Taylor & Francis Group, LLC 60 Micro Electro Mechanical System Design TABLE 2.9 Phosphorus and Boron Diffusion Coefficients in Silicon and Silicon... (2.20) Concentration/Surface Concentration 0 0.5 (a) Case 1 1.5 1 Depth–micron 2 Dt = 0.1 Dt = 0.2 Dt = 0 .3 2.5 © 2005 by Taylor & Francis Group, LLC FIGURE 2 .36 Solution of Frick’s equation solutions for case 1 and case 2 100 100 101 0 0.5 (b) Case 2 1 1.5 Depth–micron 2 Dt = 0.1 Dt = 0.2 Dt = 0 .3 2.5 58 Micro Electro Mechanical System Design Concentration/Initial Fixed Impurity Concentration 59 Fabrication... Abformung) Bulk micromachining Sacrificial surface micromachining Figure 3. 1 illustrates the basic concepts of each of the three fabrication approaches Bulk micromachining and sacrificial surface micromachining are most frequently silicon based and are generally very synergistic to the microelectronics industry because they tend to use common tool sets Bulk micromachining (BMM) utilizes wet- or dry-etch processes... two-dimensional Very limited material suite 1 µm 13 µm 2 mm ~10–1 Surface micromachining TABLE 3. 1 Comparison of the Capabilities of MEMS Fabrication Technologies and Conventional Machining Serial processing Assembly required Yes No Very flexible three-dimensional Extremely large material suite ~10–25 µm Very large >10 m >10 3 Conventional machining MEMS Technologies 69 70 Micro Electro Mechanical System. .. Technologies 69 70 Micro Electro Mechanical System Design TABLE 3. 2 Comparison of MEMS Device Capabilities within the Three Types of MEMS Fabrication Technologies Bulk micromachining Device capability Type of actuation Mass Capacitance Out-of-plane stiffness Range of motion Large arrays of devices Integral on-chip microelectronics Surface micromachining Electrostatic Large >1 pF Large Restricted to the... Fabrication Processes ( ) () FIGURE 2 .34 A two-dimensional schematic of a silicon lattice doped with phosphorous and boron to produce an n-type and a p-type semiconductor, respectively TABLE 2.7 Group III, IV, and V Elements Commonly Used in Semiconductors Group III (three valance electrons-acceptors) Group IV (four valance electrons) Group III (five valance electrons-donors) Boron (B) Aluminum (Al) Gallium... structural thin films Silicon Substrate LIGA Bulk Micromachining Surface Micromachining 66 Micro Electro Mechanical System Design Yoke Landing tip CMOS substrate Mirror +10 degrees © 2005 by Taylor & Francis Group, LLC FIGURE 3. 2 Surface micromachining commercial applications (Courtesy Texas Instruments.) Hinge Mirror–10 degrees Digital Micromirror Device Texas Instruments (Copyright Analog Devices Inc All... in Table 3. 1 The impacts of the fabrication process capabilities on the capabilities of a MEMS device are summarized in Table 3. 2 MEMS device capabilities include actuation method, mass, capacitance, out-of-plane stiffness, etc These are the issues through which the MEMS design engineer must sort to select a fabrication process suitable for the device of interest 3. 1 BULK MICROMACHINING Bulk micromachining... Micro Electro Mechanical System Design 20 µm Linkage arm Overhang Planarized linkage arm Gear Hub Gear (a) Example of a conformable Layer (b) Example of topography removed by Chemical Mechanical Polishing FIGURE 2 .32 SUMMiT ™ (Sandia ultraplanar multilevel MEMS technology) polysilicon layer with and without CMP processing Down Force Rotation Carrier Slurry Carrier Insert Wafer Pad Platen FIGURE 2 .33 ... M.A Michalicek, V.M Bright, Flip-chip fabrication of advanced micromirror arrays, Sensors Actuators A, 95, 152–157, 2002 7 S Ohki, S Ishihara, An overview of x-ray lithography, Microelectron Eng., 30 (1–4), 171–178, January 1996 8 R DeJule, E-beam lithography, the debate continues, Semiconductor Int., 19, 85, 1996 9 M.V Klein, Optics, John Wiley & Sons, New York, 1970 10 J.D Verhoeven, The mystery of . AsH 3 .AsF 3 Arsenosilica AlAsO 4 Phosphorus PH 3 ,PF 3 POCl 3 , phosphosilica NH 4 H 2 PO 4 , (NH 4 ) 2 H 2 PO 4 Boron B 2 H 6 , BF 3 , BCl 3 BBr 3 , (CH 3 O) 3 B, borosilica BN FIGURE 2 .37 Diffusion. constant C x t x( , ) ,= = ≠0 0 0 J x t dC x t dx ( , ) ( , ) = = = =0 0 0 © 2005 by Taylor & Francis Group, LLC 58 Micro Electro Mechanical System Design FIGURE 2 .36 Solution of Frick’s equation. for very fine line widths (<0 .35 µm) involve the development of sophisticated tools such as x-ray lithog- raphy [7] or direct-write E-beam lithography [8]. Microelectronics will need the capability