1Background ApplicationReport SPRAAR7–December2007 USB2.0BoardDesignandLayoutGuidelines DSPSApplications ABSTRACT Thisdocumentdiscussesschematicguidelineswhendesigningauniversalserialbus (USB)system. Contents 1Background 1 2USBPHYLayoutGuide 2 3ElectrostaticDischarge(ESD) 8 4References 10 ListofFigures 1SuggestedArrayCapacitorsandaFerriteBeadtoMinimizeEMI 2 2Four-LayerBoardStack-Up 3 3USBConnector 4 43WSpacingRule 4 5PowerSupplyandClockConnectiontotheUSBPHY 5 6USBPHYConnectorandCableConnector 6 7DoNotCrossPlaneBoundaries 7 8DoNotOverlapPlanes 7 9DoNotViolateImagePlanes 8 ClockfrequenciesgeneratethemainsourceofenergyinaUSBdesign.TheUSBdifferentialDP/DMpairs operateinhigh-speedmodeat480Mbps.Systemclockscanoperateat12MHz,48MHz,and60MHz. TheUSBcablecanbehaveasamonopoleantenna;takecaretopreventRFcurrentsfromcouplingonto thecable. WhendesigningaUSBboard,thesignalsofmostinterestare: •Deviceinterfacesignals:Clocksandothersignal/datalinesthatrunbetweendevicesonthePCB. •Powergoingintoandoutofthecable:TheUSBconnectorsocketpin1(VBUS)maybeheavily filteredandneedonlypasslowfrequencysignalsoflessthan~100KHz.TheUSBsocketpin4 (analogground)mustbeabletoreturnthecurrentduringdatatransmission,andmustbefiltered sparingly. •Differentialtwistedpairsignalsgoingoutoncable,DPandDM:Dependinguponthedatatransferrate, thesedeviceterminalscanhavesignalswithfundamentalfrequenciesof240MHz(highspeed),6 MHz(fullspeed),and750kHz(lowspeed). •Externalcrystalcircuit(deviceterminalsXIandX0):12MHz,19.2MHz,24MHz,and48MHz fundamental.Whenusinganexternalcrystalasareferenceclock,a24MHzandhighercrystalis highlyrecommended. Alltrademarksarethepropertyoftheirrespectiveowners. SPRAAR7–December2007USB2.0BoardDesignandLayoutGuidelines1 SubmitDocumentationFeedback www.ti.com 2USBPHYLayoutGuide 2.1GeneralRoutingandPlacement 2.2SpecificGuidelinesforUSBPHYLayout 2.2.1Analog,PLL,andDigitalPowerSupplyFiltering Analog PowerSupply SoCBoard FerriteBead Digital PowerSupply FerriteBead 0.1µF 0.01µF 0.001µF 10µF 0.1µF 0.01µF 0.001µF 10µF USBPHYLayoutGuide ThefollowingsectionsdescribeindetailthespecificguidelinesforUSBPHYLayout. UsethefollowingroutingandplacementguidelineswhenlayingoutanewdesignfortheUSBphysical layer(PHY).Theseguidelineshelpminimizesignalqualityandelectromagneticinterference(EMI) problemsonafour-or-morelayerevaluationmodule(EVM). •PlacetheUSBPHYandmajorcomponentsontheun-routedboardfirst.Formoredetails,see Section2.2.3. •Routethehigh-speedclockandhigh-speedUSBdifferentialsignalswithminimumtracelengths. •Routethehigh-speedUSBsignalsontheplaneclosesttothegroundplane,wheneverpossible. •Routethehigh-speedUSBsignalsusingaminimumofviasandcorners.Thisreducessignal reflectionsandimpedancechanges. •Whenitbecomesnecessarytoturn90°,usetwo45°turnsoranarcinsteadofmakingasingle90° turn.Thisreducesreflectionsonthesignaltracesbyminimizingimpedancediscontinuities. •DonotrouteUSBtracesunderornearcrystals,oscillators,clocksignalgenerators,switching regulators,mountingholes,magneticdevicesorIC’sthatuseorduplicateclocksignals. •Avoidstubsonthehigh-speedUSBsignalsbecausetheycausesignalreflections.Ifastubis unavoidable,thenthestubshouldbelessthan200mils. •Routeallhigh-speedUSBsignaltracesovercontinuousplanes(V CC orGND),withnointerruptions. Avoidcrossingoveranti-etch,commonlyfoundwithplanesplits. ThefollowingsectionsdescribeindetailthespecificguidelinesforUSBPHYLayout. TominimizeEMIemissions,adddecouplingcapacitorswithaferritebeadatpowersupplyterminalsfor theanalog,phase-lockedloop(PLL),anddigitalportionsofthechip.Placethisarrayasclosetothechip aspossibletominimizetheinductanceofthelineandnoisecontributionstothesystem.Ananalogand digitalsupplyexampleisshowninFigure1.Incaseofmultiplepowersupplypinswiththesamefunction, tiethemuptoasinglelow-impedancepointintheboardandthenaddthedecouplingcapacitors,in additiontotheferritebead.ThisarrayofcapsandferritebeadimproveEMIandjitterperformance.Take bothEMIandjitterintoaccountbeforealteringtheconfiguration. Figure1.SuggestedArrayCapacitorsandaFerriteBeadtoMinimizeEMI 2USB2.0BoardDesignandLayoutGuidelinesSPRAAR7–December2007 SubmitDocumentationFeedback www.ti.com 2.2.2Analog,Digital,andPLLPartitioning 2.2.3BoardStackup Signal1 PowerPlane GNDPlane Signal2 2.2.4CableConnectorSocket USBPHYLayoutGuide ConsidertherecommendationslistedbelowtoachieveproperESD/EMIperformance: •Usea0.01µFcaponeachcablepowerVBUSlinetochassisGNDclosetotheUSBconnectorpin. •Usea0.01µFcaponeachcablegroundlinetochassisGNDnexttotheUSBconnectorpin. •Ifvoltageregulatorsareused,placea0.01µFcaponbothinputandoutput.Thisistoincreasethe immunitytoESDandreduceEMI.Forotherrequirements,seethedevice-specificdatasheet. Ifseparatepowerplanesareused,theymustbetiedtogetheratonepointthroughalow-impedance bridgeorpreferablythroughaferritebead.Caremustbetakentocapacitivelydecoupleeachpowerrail closetothedevice.Theanalogground,digitalground,andPLLgroundmustbetiedtogethertothe low-impedancecircuitboardgroundplane. BecauseofthehighfrequenciesassociatedwiththeUSB,aprintedcircuitboardwithatleastfourlayers isrecommended;twosignallayersseparatedbyagroundandpowerlayerasshowninFigure2. Figure2.Four-LayerBoardStack-Up Themajorityofsignaltracesshouldrunonasinglelayer,preferablySIGNAL1.Immediatelynexttothis layershouldbetheGNDplane,whichissolidwithnocuts.Avoidrunningsignaltracesacrossasplitin thegroundorpowerplane.Whenrunningacrosssplitplanesisunavoidable,sufficientdecouplingmust beused.MinimizingthenumberofsignalviasreducesEMIbyreducinginductanceathighfrequencies. Shortthecableconnectorsocketsdirectlytoasmallchassisgroundplane(GNDstrap)thatexists immediatelyunderneaththeconnectorsockets.ThisshortsEMI(andESD)directlytothechassisground beforeitgetsontotheUSBcable.Thisetchplaneshouldbeaslargeaspossible,butalltheconductors comingoffconnectorpins1through6musthavetheboardsignalGNDplanerununder.Ifneeded,scoop outthechassisGNDstrapetchtoallowforthesignalgroundtoextendundertheconnectorpins.Note thattheetchescomingfrompins1and4(VBUSpowerandGND)shouldbewideandvia-edtotheir respectiveplanesassoonaspossible,respectingthefilteringthatmaybeinplacebetweentheconnector pinandtheplane.SeeFigure3foraschematicexample. PlaceaferriteinserieswiththecableshieldpinsneartheUSBconnectorsockettokeepEMIfromgetting ontothecableshield.Theferritebeadbetweenthecableshieldandgroundmaybevaluedbetween10Ω and50Ωat100MHz;itshouldberesistivetoapproximately1GHz.TokeepEMIfromgettingontothe cablebuspowerwire(averylargeantenna)aferritemaybeplacedinserieswithcablebuspower, VBUS,neartheUSBconnectorpin1.Theferritebeadbetweenconnectorpin1andbuspowermaybe valuedbetween47Ωandapproximately1000Ωat100MHz.Itshouldcontinuebeingresistiveoutto approximately1GHz,asshowninFigure3. SPRAAR7–December2007USB2.0BoardDesignandLayoutGuidelines3 SubmitDocumentationFeedback www.ti.com U2 FerriteBead VBUS U1 USBSocket 5 4 3 2 1 6 SHIELD_GND GND DP DM +5V SHIELD_GND FerriteBead 2.2.5ClockRoutings Trace 3W 3W W USBPHYLayoutGuide Figure3.USBConnector Toaddressthesystemclockemissionsbetweendevices,placea~10to130Ωresistorinserieswiththe clocksignal.Useatrialanderrormethodoflookingattheshapeoftheclockwaveformonahigh-speed oscilloscopeandoftuningthevalueoftheresistancetominimizewaveformdistortion.Thevalueonthis resistorshouldbeassmallaspossibletogetthedesiredeffect.Placetheresistorclosetothedevice generatingtheclocksignal.Ifanexternalcrystalisused,followtheguidelinesdetailedintheSelection andSpecificationofCrystalsforTexasInstrumentsUSB2.0Devices(SLLA122). Whenroutingtheclocktracesfromonedevicetoanother,trytousethe3Wspacingrule.Thedistance fromthecenteroftheclocktracetothecenterofanyadjacentsignaltraceshouldbeatleastthreetimes thewidthoftheclocktrace.Manyclocks,includingslowfrequencyclocks,canhavefastriseandfall times.Usingthe3Wrulecutsdownoncrosstalkbetweentraces.Ingeneral,leavespacebetweeneachof thetracesrunningparallelbetweenthedevices.Avoidusingrightangleswhenroutingtracestominimize theroutingdistanceandimpedancediscontinuities.Forfurtherprotectionfromcrosstalk,runguardtraces besidetheclocksignals(GNDpintoGNDpin),ifpossible.Thislessensclocksignalcoupling,asshownin Figure4. Figure4.3WSpacingRule USB2.0BoardDesignandLayoutGuidelines 4SPRAAR7–December2007 SubmitDocumentationFeedback www.ti.com 2.2.6Crystals/Oscillator PowerPins USBPHY 0.1µF 0.001µF X1 X0 XTAL 2.2.7DP/DMTrace USBPHYLayoutGuide KeepthecrystalanditsloadcapacitorsclosetotheUSBPHYpins,XIandXO(seeFigure5).Notethat frequenciesfrompowersourcesorlargecapacitorscancausemodulationswithintheclockandshould notbeplacednearthecrystal.Intheseinstances,errorssuchasdroppedpacketsoccur.Aplaceholder foraresistor,inparallelwiththecrystal,canbeincorporatedinthedesigntoassistoscillatorstartup. Powerisproportionaltothecurrentsquared.ThecurrentisI=C*dv/dt,sincedv/dtisafunctionofthe PHY,currentisproportionaltothecapacitiveload.Cuttingtheloadtodecreasesthecurrentbyandthe powerto1/4theoriginalvalue.Formoredetailsoncrystalselection,seetheSelectionandSpecification ofCrystalsforTexasInstrumentsUSB2.0Devices(SLLA122). Figure5.PowerSupplyandClockConnectiontotheUSBPHY PlacetheUSBPHYascloseaspossibletotheUSB2.0connector.Thesignalswingduringhigh-speed operationontheDP/DMlinesisrelativelysmall(400mV±10%),soanydifferentialnoisepickedupon thetwistedpaircanaffectthereceivedsignal.WhentheDP/DMtracesdonothaveanyshielding,the tracestendtobehavelikeanantennaandpicksupnoisegeneratedbythesurroundingcomponentsin theenvironment.Tominimizetheeffectofthisbehavior: •DP/DMtracesshouldalwaysbematchedlengthsandmustbenomorethan4inchesinlength; otherwise,theeyeopeningmaybedegraded(seeFigure6). •RouteDP/DMtracesclosetogetherfornoiserejectionondifferentialsignals,paralleltoeachotherand withintwomilsinlengthofeachother(startthemeasurementatthechippackageboundary,nottothe ballsorpins). •Ahigh-speedUSBconnectionismadethroughashielded,twistedpaircablewithadifferential characteristicimpedanceof90Ω±15%.Inlayout,theimpedanceofDPandDMshouldeachbe45Ω ±10%. •DP/DMtracesshouldnothaveanyextracomponentstomaintainsignalintegrity.Forexample,traces cannotberoutedtotwoUSBconnectors. SPRAAR7–December2007USB2.0BoardDesignandLayoutGuidelines5 SubmitDocumentationFeedback www.ti.com Minimize ThisDistance USBPHY Connector D+ D- VBUS GND D- D+ Cable Connector 2.2.8DP/DMVias 2.2.9ImagePlanes USBPHYLayoutGuide Figure6.USBPHYConnectorandCableConnector Whenaviamustbeused,increasetheclearancesizearoundittominimizeitscapacitance.Eachvia introducesdiscontinuitiesinthesignal’stransmissionlineandincreasesthechanceofpickingup interferencefromtheotherlayersoftheboard.Becarefulwhendesigningtestpointsontwistedpairlines; through-holepinsarenotrecommended. Animageplaneisalayerofcopper(voltageplaneorgroundplane),physicallyadjacenttoasignalrouting plane.Useofimageplanesprovidesalowimpedance,shortestpossiblereturnpathforRFcurrents.Fora USBboard,thebestimageplaneisthegroundplanebecauseitcanbeusedforbothanaloganddigital circuits. •Donotroutetracessotheycrossfromoneplanetotheother.ThiscancauseabrokenRFreturnpath resultinginanEMIradiatingloopasshowninFigure7.Thisisimportantforhigherfrequencyor repetitivesignals.Therefore,onamulti-layerboard,itisbesttorunallclocksignalsonthesignal planeaboveasolidgroundplane. •Avoidcrossingtheimagepowerorgroundplaneboundarieswithhigh-speedclocksignaltraces immediatelyaboveorbelowtheseparatedplanes.Thisalsoholdstrueforthetwistedpairsignals(DP, DM).AnyunusedareaofthetopandbottomsignallayersofthePCBcanbefilledwithcopperthatis connectedtothegroundplanethroughvias. 6USB2.0BoardDesignandLayoutGuidelinesSPRAAR7–December2007 SubmitDocumentationFeedback www.ti.com Don't Do AnalogPowerPlane UnwantedCapacitance DigitalPowerPlane USBPHYLayoutGuide Figure7.DoNotCrossPlaneBoundaries •Donotoverlapplanesthatdonotreferenceeachother.Forexample,donotoverlapadigitalpower planewithananalogpowerplaneasthisproducesacapacitancebetweentheoverlappingareasthat couldpassRFemissionsfromoneplanetotheother,asshowninFigure8. Figure8.DoNotOverlapPlanes SPRAAR7–December2007USB2.0BoardDesignandLayoutGuidelines7 SubmitDocumentationFeedback www.ti.com SlotinImagePlane RFReturn Current Bad SlotinImagePlane RFReturn Current Better 2.2.10JTAGInterface 2.2.11PowerRegulators 3ElectrostaticDischarge(ESD) 3.1IECESDStressingTest ElectrostaticDischarge(ESD) •Avoidimageplaneviolations.TracesthatrouteoveraslotinanimageplaneresultsinapossibleRF returnloop,asshowninFigure9. Figure9.DoNotViolateImagePlanes FortestanddebugoftheUSBPHYonly,anIEEEStandard1149.1-1990,IEEEStandardTestAccess PortandBoundary-ScanArchitecture(JTAG)andSerialTestandConfigurationInterface(STCI)maybe availableontheSystem-on-Chip(SoC).Ifavailable,keeptheUSBPHYJTAGinterfacelessthansix inches;keepingthisdistanceshortreducesnoisecouplingfromotherdevicesandsignallossdueto resistance. Switchingpowerregulatorsareasourceofnoiseandcancausenoisecouplingifplacedclosetosensitive areasonacircuitboard.Therefore,theswitchingpowerregulatorshouldbekeptawayfromtheDP/DM signals,theexternalclockcrystal(orclockoscillator),andtheUSBPHY. InternationalElectronicCommission(IEC)61000-4-xxisasetofabout25testingspecificationsfromthe IEC.IECESDStressingisdonebothun-poweredandwithpowerapplied,andwiththedevicefunctioning. Theremustbenophysicaldamage,andthedevicemustkeepworkingnormallyaftertheconclusionof thestressing.Typically,equipmenthastopassIECstressingat8kVcontactand15kVairdischarge,or higher.Tomarketproducts/systemsintheEuropeancommunity,allproducts/systemsmustbeCE compliantandhavetheCEMark.ToobtaintheCEMark,allproducts/systemsneedtogothroughand passIECstandardrequirements;forESD,itis61000-4-2.61000-4-2requiresthattheproducts/systems passcontactdischargeat8kVandairdischargeat15kV.WhenperforminganIECESDStressing,only pinsaccessibletotheoutsideworldneedtopassthetest.Thesystemintowhichtheintegratedcircuit(IC) isplacedmakesadifferenceinhowwelltheICdoes.Forexample: •CablebetweenthezappointandtheICattenuatethehighfrequenciesinthewaveform. •SeriesinductanceonthePCBboardattenuatesthehighfrequencies. •Unlessthecapacitor’sgroundconnectionisinductive,capacitancetogroundshuntsawayhigh frequencies. ThefollowingsectionsdescribeindetailtheIECESDStressingTestmodesandtesttypes. 8USB2.0BoardDesignandLayoutGuidelinesSPRAAR7–December2007 SubmitDocumentationFeedback www.ti.com 3.1.1TestMode 3.1.2AirDischargeMode 3.1.3TestType 3.2TIComponentLevelIECESDTest 3.3ConstructionofaCustomUSBConnector ElectrostaticDischarge(ESD) TheIECESDStressingtestisdonethroughtwomodes:contactdischargemodeandairdischargemode. Forthecontactdischargetestmode,thepreferredwayisdirectcontactappliedtotheconductivesurfaces oftheequipmentundertest(EUT).InthecaseoftheUSBsystem,theconductivesurfaceistheouter casingoftheUSBconnector.TheelectrodeoftheESDgeneratorisheldincontactwiththeEUTora couplingplanepriortodischarge.Thearcformationiscreatedundercontrolledconditions,insidearelay, resultinginrepeatablewaveforms;however,thisarcdoesnotaccuratelyrecreatethecharacteristicunique tothearcofanactualESDevent. Theairdischargeusuallyappliestoanon-conductivesurfaceoftheEUT.Insteadofadirectcontactwith theEUT,thechargedelectrodeoftheESDgeneratorisbroughtclosetotheEUT,andasparkintheairto theEUTactuatesthedischarge.Comparedtothecontactdischargemode,theairdischargeismore realistictotheactualESDoccurrence.However,duetothevariationsofthearclength,itmaynotbeable toproducerepeatablewaveform. TheIECESDStressingtesthastwotesttypes:directdischargeandindirectdischarge.Directdischarge isappliesdirectlytothesurfaceorthestructureoftheEUT.Itincludesbothcontactdischargeandair dischargemodes.IndirectdischargeappliestoacouplingplaneinthevicinityoftheEUT.Theindirect dischargeisusedtosimulatepersonaldischargetoobjectswhichareadjacenttotheEUT.Itincludes contactdischargemodeonly. TIComponentLevelIECESDTesttestsonlytheICterminalsthatareexposedinsystemlevel applications.Itcanbeusedtodeterminetherobustnessofon-chipprotectionandthelatch-upimmunity. TheICcanonlypasstheTIComponentLevelIECESDtestwhenthereisnolatch-upandICisfully functionalafterthetest. AstandardUSBconnector,eithertypeAortypeB,providesgoodESDprotection.However,ifacustom USBconnectorisdesired,thefollowingguidelinesshouldbeobservedtoensuregoodESDprotection. •Thereshouldbeaneasilyaccessibleshieldplatenexttotheconnectorforair-dischargemode purpose. •TietheoutershieldoftheconnectortoGND.Whenacableisinsertedintotheconnector,theshieldof thecableshouldfirstmakecontactwiththeoutershield. •IftheconnectorincludespowerandGND,theleadofpowerandGNDneedtobelongerthanthe leadsofsignal. •Theconnectorneedstohaveakeytoensureproperinsertionofthecable. •SeethestandardUSBconnectorforreference. SPRAAR7–December2007USB2.0BoardDesignandLayoutGuidelines9 SubmitDocumentationFeedback www.ti.com 3.4ESDProtectionSystemDesignConsideration 4References References ESDprotectionsystemdesignconsiderationiscoveredinSection2ofthisdocument.Thefollowingare additionalconsiderationsforESDprotectioninasystem. •MetallicshieldingforbothESDandEMI •ChassisGNDisolationfromtheboardGND •AirgapdesignedonboardtoabsorbESDenergy •ClampingdiodestoabsorbESDenergy •CapacitorstodivertESDenergy •TheuseofexternalESDcomponentsontheDP/DMlinesmayaffectsignalqualityandarenot recommended. •USB2.0Specification,Intel,2000,http://www.usb.org/developers/docs/ •HighSpeedUSBPlatformDesignGuidelines,Intel,2000, http://www.intel.com/technology/usb/download/usb2dg_R1_0.pdf •SelectionandSpecificationofCrystalsforTexasInstrumentsUSB2.0Devices(SLLA122) 10USB2.0BoardDesignandLayoutGuidelinesSPRAAR7–December2007 SubmitDocumentationFeedback [...]... safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI Further, Buyers must fully indemnify TI and its... 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Whenroutingtheclocktracesfromonedevicetoanother,trytousethe3Wspacingrule.Thedistance fromthecenteroftheclocktracetothecenterofanyadjacentsignaltraceshouldbeatleastthreetimes thewidthoftheclocktrace.Manyclocks,includingslowfrequencyclocks,canhavefastriseandfall times.Usingthe3Wrulecutsdownoncrosstalkbetweentraces.Ingeneral,leavespacebetweeneachof thetracesrunningparallelbetweenthedevices.Avoidusingrightangleswhenroutingtracestominimize theroutingdistanceandimpedancediscontinuities.Forfurtherprotectionfromcrosstalk,runguardtraces besidetheclocksignals(GNDpintoGNDpin),ifpossible.Thislessensclocksignalcoupling,asshownin Figure4. Figure4.3WSpacingRule USB2 .0BoardDesignandLayoutGuidelines 4SPRAAR7–December 200 7 SubmitDocumentationFeedback www.ti.com 2. 2.6Crystals/Oscillator PowerPins USB PHY 0. 1µF 0. 001 µF X1 X0 XTAL 2. 2.7DP/DMTrace USBPHYLayoutGuide KeepthecrystalanditsloadcapacitorsclosetotheUSBPHYpins,XIandXO(seeFigure5).Notethat frequenciesfrompowersourcesorlargecapacitorscancausemodulationswithintheclockandshould notbeplacednearthecrystal.Intheseinstances,errorssuchasdroppedpacketsoccur.Aplaceholder foraresistor,inparallelwiththecrystal,canbeincorporatedinthedesigntoassistoscillatorstartup. Powerisproportionaltothecurrentsquared.ThecurrentisI=C*dv/dt,sincedv/dtisafunctionofthe PHY,currentisproportionaltothecapacitiveload.Cuttingtheloadtodecreasesthecurrentbyandthe powerto1/4theoriginalvalue.Formoredetailsoncrystalselection,seetheSelectionandSpecification ofCrystalsforTexasInstrumentsUSB2.0Devices(SLLA 122 ). Figure5.PowerSupplyandClockConnectiontotheUSBPHY PlacetheUSBPHYascloseaspossibletotheUSB2.0connector.Thesignalswingduringhigh-speed operationontheDP/DMlinesisrelativelysmall( 400 mV± 10% ),soanydifferentialnoisepickedupon thetwistedpaircanaffectthereceivedsignal.WhentheDP/DMtracesdonothaveanyshielding,the tracestendtobehavelikeanantennaandpicksupnoisegeneratedbythesurroundingcomponentsin theenvironment.Tominimizetheeffectofthisbehavior: •DP/DMtracesshouldalwaysbematchedlengthsandmustbenomorethan4inchesinlength; otherwise,theeyeopeningmaybedegraded(seeFigure6). •RouteDP/DMtracesclosetogetherfornoiserejectionondifferentialsignals,paralleltoeachotherand withintwomilsinlengthofeachother(startthemeasurementatthechippackageboundary,nottothe ballsorpins). •Ahigh-speedUSBconnectionismadethroughashielded,twistedpaircablewithadifferential characteristicimpedanceof 90 ±15%.Inlayout,theimpedanceofDPandDMshouldeachbe45Ω ± 10% . •DP/DMtracesshouldnothaveanyextracomponentstomaintainsignalintegrity.Forexample,traces cannotberoutedtotwoUSBconnectors. SPRAAR7–December 200 7USB2 .0BoardDesignandLayoutGuidelines5 SubmitDocumentationFeedback www.ti.com Minimize ThisDistance USB PHY Connector D+ D- VBUS GND D- D+ Cable Connector 2. 2.8DP/DMVias 2. 2.9ImagePlanes USBPHYLayoutGuide Figure6.USBPHYConnectorandCableConnector Whenaviamustbeused,increasetheclearancesizearoundittominimizeitscapacitance.Eachvia introducesdiscontinuitiesinthesignal’stransmissionlineandincreasesthechanceofpickingup interferencefromtheotherlayersoftheboard.Becarefulwhendesigningtestpointsontwistedpairlines; through-holepinsarenotrecommended. Animageplaneisalayerofcopper(voltageplaneorgroundplane),physicallyadjacenttoasignalrouting plane.Useofimageplanesprovidesalowimpedance,shortestpossiblereturnpathforRFcurrents.Fora USBboard,thebestimageplaneisthegroundplanebecauseitcanbeusedforbothanaloganddigital circuits. •Donotroutetracessotheycrossfromoneplanetotheother.ThiscancauseabrokenRFreturnpath resultinginanEMIradiatingloopasshowninFigure7.Thisisimportantforhigherfrequencyor repetitivesignals.Therefore,onamulti-layerboard,itisbesttorunallclocksignalsonthesignal planeaboveasolidgroundplane. •Avoidcrossingtheimagepowerorgroundplaneboundarieswithhigh-speedclocksignaltraces immediatelyaboveorbelowtheseparatedplanes.Thisalsoholdstrueforthetwistedpairsignals(DP, DM).AnyunusedareaofthetopandbottomsignallayersofthePCBcanbefilledwithcopperthatis connectedtothegroundplanethroughvias. 6USB2 .0BoardDesignandLayoutGuidelinesSPRAAR7–December 200 7 SubmitDocumentationFeedback www.ti.com Don't Do AnalogPowerPlane UnwantedCapacitance DigitalPowerPlane USBPHYLayoutGuide Figure7.DoNotCrossPlaneBoundaries •Donotoverlapplanesthatdonotreferenceeachother.Forexample,donotoverlapadigitalpower planewithananalogpowerplaneasthisproducesacapacitancebetweentheoverlappingareasthat couldpassRFemissionsfromoneplanetotheother,asshowninFigure8. Figure8.DoNotOverlapPlanes SPRAAR7–December 200 7USB2 .0BoardDesignandLayoutGuidelines7 SubmitDocumentationFeedback www.ti.com SlotinImagePlane RFReturn Current Bad SlotinImagePlane RFReturn Current Better 2. 2.10JTAGInterface 2. 2.11PowerRegulators 3ElectrostaticDischarge(ESD) 3.1IECESDStressingTest ElectrostaticDischarge(ESD) •Avoidimageplaneviolations.TracesthatrouteoveraslotinanimageplaneresultsinapossibleRF returnloop,asshowninFigure9. Figure9.DoNotViolateImagePlanes FortestanddebugoftheUSBPHYonly,anIEEEStandard1149.1-19 90, IEEEStandardTestAccess PortandBoundary-ScanArchitecture(JTAG)andSerialTestandConfigurationInterface(STCI)maybe availableontheSystem-on-Chip(SoC).Ifavailable,keeptheUSBPHYJTAGinterfacelessthansix inches;keepingthisdistanceshortreducesnoisecouplingfromotherdevicesandsignallossdueto resistance. Switchingpowerregulatorsareasourceofnoiseandcancausenoisecouplingifplacedclosetosensitive areasonacircuitboard.Therefore,theswitchingpowerregulatorshouldbekeptawayfromtheDP/DM signals,theexternalclockcrystal(orclockoscillator),andtheUSBPHY. InternationalElectronicCommission(IEC)6 100 0-4-xxisasetofabout25testingspecificationsfromthe IEC.IECESDStressingisdonebothun-poweredandwithpowerapplied,andwiththedevicefunctioning. Theremustbenophysicaldamage,andthedevicemustkeepworkingnormallyaftertheconclusionof thestressing.Typically,equipmenthastopassIECstressingat8kVcontactand15kVairdischarge,or higher.Tomarketproducts/systemsintheEuropeancommunity,allproducts/systemsmustbeCE compliantandhavetheCEMark.ToobtaintheCEMark,allproducts/systemsneedtogothroughand passIECstandardrequirements;forESD,itis6 100 0-4 -2. 6 100 0-4-2requiresthattheproducts/systems passcontactdischargeat8kVandairdischargeat15kV.WhenperforminganIECESDStressing,only pinsaccessibletotheoutsideworldneedtopassthetest.Thesystemintowhichtheintegratedcircuit(IC) isplacedmakesadifferenceinhowwelltheICdoes.Forexample: •CablebetweenthezappointandtheICattenuatethehighfrequenciesinthewaveform. •SeriesinductanceonthePCBboardattenuatesthehighfrequencies. •Unlessthecapacitor’sgroundconnectionisinductive,capacitancetogroundshuntsawayhigh frequencies. ThefollowingsectionsdescribeindetailtheIECESDStressingTestmodesandtesttypes. 8USB2 .0BoardDesignandLayoutGuidelinesSPRAAR7–December 200 7 SubmitDocumentationFeedback www.ti.com 3.1.1TestMode 3.1.2AirDischargeMode 3.1.3TestType 3.2TIComponentLevelIECESDTest 3.3ConstructionofaCustomUSBConnector ElectrostaticDischarge(ESD) TheIECESDStressingtestisdonethroughtwomodes:contactdischargemodeandairdischargemode. Forthecontactdischargetestmode,thepreferredwayisdirectcontactappliedtotheconductivesurfaces oftheequipmentundertest(EUT).InthecaseoftheUSBsystem,theconductivesurfaceistheouter casingoftheUSBconnector.TheelectrodeoftheESDgeneratorisheldincontactwiththeEUTora couplingplanepriortodischarge.Thearcformationiscreatedundercontrolledconditions,insidearelay, resultinginrepeatablewaveforms;however,thisarcdoesnotaccuratelyrecreatethecharacteristicunique tothearcofanactualESDevent. Theairdischargeusuallyappliestoanon-conductivesurfaceoftheEUT.Insteadofadirectcontactwith theEUT,thechargedelectrodeoftheESDgeneratorisbroughtclosetotheEUT,andasparkintheairto theEUTactuatesthedischarge.Comparedtothecontactdischargemode,theairdischargeismore realistictotheactualESDoccurrence.However,duetothevariationsofthearclength,itmaynotbeable toproducerepeatablewaveform. TheIECESDStressingtesthastwotesttypes:directdischargeandindirectdischarge.Directdischarge isappliesdirectlytothesurfaceorthestructureoftheEUT.Itincludesbothcontactdischargeandair dischargemodes.IndirectdischargeappliestoacouplingplaneinthevicinityoftheEUT.Theindirect dischargeisusedtosimulatepersonaldischargetoobjectswhichareadjacenttotheEUT.Itincludes contactdischargemodeonly. TIComponentLevelIECESDTesttestsonlytheICterminalsthatareexposedinsystemlevel applications.Itcanbeusedtodeterminetherobustnessofon-chipprotectionandthelatch-upimmunity. TheICcanonlypasstheTIComponentLevelIECESDtestwhenthereisnolatch-upandICisfully functionalafterthetest. AstandardUSBconnector,eithertypeAortypeB,providesgoodESDprotection.However,ifacustom USBconnectorisdesired,thefollowingguidelinesshouldbeobservedtoensuregoodESDprotection. •Thereshouldbeaneasilyaccessibleshieldplatenexttotheconnectorforair-dischargemode purpose. •TietheoutershieldoftheconnectortoGND.Whenacableisinsertedintotheconnector,theshieldof thecableshouldfirstmakecontactwiththeoutershield. •IftheconnectorincludespowerandGND,theleadofpowerandGNDneedtobelongerthanthe leadsofsignal. •Theconnectorneedstohaveakeytoensureproperinsertionofthecable. •SeethestandardUSBconnectorforreference. SPRAAR7–December 200 7USB2 .0BoardDesignandLayoutGuidelines9 SubmitDocumentationFeedback www.ti.com 3.4ESDProtectionSystemDesignConsideration 4References References ESDprotectionsystemdesignconsiderationiscoveredinSection2ofthisdocument.Thefollowingare additionalconsiderationsforESDprotectioninasystem. •MetallicshieldingforbothESDandEMI •ChassisGNDisolationfromtheboardGND •AirgapdesignedonboardtoabsorbESDenergy •ClampingdiodestoabsorbESDenergy •CapacitorstodivertESDenergy •TheuseofexternalESDcomponentsontheDP/DMlinesmayaffectsignalqualityandarenot recommended. USB2 .0Specification,Intel , 20 00, http://www .usb. org/developers/docs/ •HighSpeedUSBPlatformDesignGuidelines,Intel , 20 00, http://www.intel.com/technology /usb/ download /usb2 dg_R1 _0. pdf •SelectionandSpecificationofCrystalsforTexasInstrumentsUSB2.0Devices(SLLA 122 ) 1 0USB2 .0BoardDesignandLayoutGuidelinesSPRAAR7–December 200 7 SubmitDocumentationFeedback IMPORTANTNOTICE TexasInstrumentsIncorporatedanditssubsidiaries(TI)reservetherighttomakecorrections,modifications,enhancements, improvements,andotherchangestoitsproductsandservicesatanytimeandtodiscontinueanyproductorservicewithoutnotice. Customersshouldobtainthelatestrelevantinformationbeforeplacingordersandshouldverifythatsuchinformationiscurrentand complete.AllproductsaresoldsubjecttoTI’stermsandconditionsofsalesuppliedatthetimeoforderacknowledgment. TIwarrantsperformanceofitshardwareproductstothespecificationsapplicableatthetimeofsaleinaccordancewithTI’s standardwarranty.TestingandotherqualitycontroltechniquesareusedtotheextentTIdeemsnecessarytosupportthis warranty.Exceptwheremandatedbygovernmentrequirements,testingofallparametersofeachproductisnotnecessarily performed. TIassumesnoliabilityforapplicationsassistanceorcustomerproductdesign.Customersareresponsiblefortheirproductsand applicationsusingTIcomponents.Tominimizetherisksassociatedwithcustomerproductsandapplications,customersshould provideadequatedesignandoperatingsafeguards. TIdoesnotwarrantorrepresentthatanylicense,eitherexpressorimplied,isgrantedunderanyTIpatentright,copyright,mask workright,orotherTIintellectualpropertyrightrelatingtoanycombination,machine,orprocessinwhichTIproductsorservices areused.InformationpublishedbyTIregardingthird-partyproductsorservicesdoesnotconstitutealicensefromTItousesuch productsorservicesorawarrantyorendorsementthereof.Useofsuchinformationmayrequirealicensefromathirdpartyunder thepatentsorotherintellectualpropertyofthethirdparty,oralicensefromTIunderthepatentsorotherintellectualpropertyofTI. ReproductionofTIinformationinTIdatabooksordatasheetsispermissibleonlyifreproductioniswithoutalterationandis accompaniedbyallassociatedwarranties,conditions,limitations,andnotices.Reproductionofthisinformationwithalterationisan unfairanddeceptivebusinesspractice.TIisnotresponsibleorliableforsuchaltereddocumentation.Informationofthirdparties maybesubjecttoadditionalrestrictions. ResaleofTIproductsorserviceswithstatementsdifferentfromorbeyondtheparametersstatedbyTIforthatproductorservice voidsallexpressandanyimpliedwarrantiesfortheassociatedTIproductorserviceandisanunfairanddeceptivebusiness practice.TIisnotresponsibleorliableforanysuchstatements. TIproductsarenotauthorizedforuseinsafety-criticalapplications(suchaslifesupport)whereafailureoftheTIproductwould reasonablybeexpectedtocauseseverepersonalinjuryordeath,unlessofficersofthepartieshaveexecutedanagreement specificallygoverningsuchuse.Buyersrepresentthattheyhaveallnecessaryexpertiseinthesafetyandregulatoryramifications oftheirapplications,andacknowledgeandagreethattheyaresolelyresponsibleforalllegal,regulatoryandsafety-related requirementsconcerningtheirproductsandanyuseofTIproductsinsuchsafety-criticalapplications,notwithstandingany applications-relatedinformationorsupportthatmaybeprovidedbyTI.Further,BuyersmustfullyindemnifyTIandits representativesagainstanydamagesarisingoutoftheuseofTIproductsinsuchsafety-criticalapplications. TIproductsareneitherdesignednorintendedforuseinmilitary/aerospaceapplicationsorenvironmentsunlesstheTIproductsare specificallydesignatedbyTIasmilitary-gradeor"enhancedplastic."OnlyproductsdesignatedbyTIasmilitary-grademeetmilitary specifications.BuyersacknowledgeandagreethatanysuchuseofTIproductswhichTIhasnotdesignatedasmilitary-gradeis solelyattheBuyer'srisk,andthattheyaresolelyresponsibleforcompliancewithalllegalandregulatoryrequirementsin connectionwithsuchuse. TIproductsareneitherdesignednorintendedforuseinautomotiveapplicationsorenvironmentsunlessthespecificTIproducts aredesignatedbyTIascompliantwithISO/TS16949requirements.Buyersacknowledgeandagreethat,iftheyuseany non-designatedproductsinautomotiveapplications,TIwillnotberesponsibleforanyfailuretomeetsuchrequirements. FollowingareURLswhereyoucanobtaininformationonotherTexasInstrumentsproductsandapplicationsolutions: ProductsApplications Amplifiersamplifier.ti.comAudiowww.ti.com/audio DataConvertersdataconverter.ti.comAutomotivewww.ti.com/automotive DSPdsp.ti.comBroadbandwww.ti.com/broadband Interfaceinterface.ti.comDigitalControlwww.ti.com/digitalcontrol Logiclogic.ti.comMilitarywww.ti.com/military PowerMgmtpower.ti.comOpticalNetworkingwww.ti.com/opticalnetwork Microcontrollersmicrocontroller.ti.comSecuritywww.ti.com/security RFIDwww.ti-rfid.comTelephonywww.ti.com/telephony LowPowerwww.ti.com/lpwVideo&Imagingwww.ti.com/video Wireless Wirelesswww.ti.com/wireless MailingAddress:TexasInstruments,PostOfficeBox655 303 ,Dallas,Texas7 526 5 Copyright 20 07,TexasInstrumentsIncorporated . 8 ClockfrequenciesgeneratethemainsourceofenergyinaUSBdesign.TheUSBdifferentialDP/DMpairs operateinhigh-speedmodeat480Mbps.Systemclockscanoperateat12MHz,48MHz ,and6 0MHz. TheUSBcablecanbehaveasamonopoleantenna;takecaretopreventRFcurrentsfromcouplingonto thecable. WhendesigningaUSBboard,thesignalsofmostinterestare: •Deviceinterfacesignals:Clocksandothersignal/datalinesthatrunbetweendevicesonthePCB. •Powergoingintoandoutofthecable:TheUSBconnectorsocketpin1(VBUS)maybeheavily filteredandneedonlypasslowfrequencysignalsoflessthan~ 100 KHz.TheUSBsocketpin4 (analogground)mustbeabletoreturnthecurrentduringdatatransmission,andmustbefiltered sparingly. •Differentialtwistedpairsignalsgoingoutoncable,DPandDM:Dependinguponthedatatransferrate, thesedeviceterminalscanhavesignalswithfundamentalfrequenciesof240MHz(highspeed),6 MHz(fullspeed) ,and7 50kHz(lowspeed). •Externalcrystalcircuit(deviceterminalsXIandX0):12MHz,19.2MHz ,24 MHz ,and4 8MHz fundamental.Whenusinganexternalcrystalasareferenceclock,a24MHzandhighercrystalis highlyrecommended. Alltrademarksarethepropertyoftheirrespectiveowners. SPRAAR7–December 200 7USB2 .0BoardDesignandLayoutGuidelines1 SubmitDocumentationFeedback www.ti.com 2USBPHYLayoutGuide 2. 1GeneralRoutingandPlacement 2. 2SpecificGuidelinesforUSBPHYLayout 2. 2.1Analog,PLL,andDigitalPowerSupplyFiltering Analog PowerSupply SoC Board FerriteBead Digital PowerSupply FerriteBead 0. 1µF 0. 01µF 0. 001 µF 10 µF 0. 1µF 0. 01µF 0. 001 µF 10 µF USBPHYLayoutGuide ThefollowingsectionsdescribeindetailthespecificguidelinesforUSBPHYLayout. UsethefollowingroutingandplacementguidelineswhenlayingoutanewdesignfortheUSBphysical layer(PHY).Theseguidelineshelpminimizesignalqualityandelectromagneticinterference(EMI) problemsonafour-or-morelayerevaluationmodule(EVM). •PlacetheUSBPHYandmajorcomponentsontheun-routedboardfirst.Formoredetails,see Section2 .2. 3. •Routethehigh-speedclockandhigh-speedUSBdifferentialsignalswithminimumtracelengths. •Routethehigh-speedUSBsignalsontheplaneclosesttothegroundplane,wheneverpossible. •Routethehigh-speedUSBsignalsusingaminimumofviasandcorners.Thisreducessignal reflectionsandimpedancechanges. •Whenitbecomesnecessarytoturn 90 ,usetwo45°turnsoranarcinsteadofmakingasingle 90 turn.Thisreducesreflectionsonthesignaltracesbyminimizingimpedancediscontinuities. •DonotrouteUSBtracesunderornearcrystals,oscillators,clocksignalgenerators,switching regulators,mountingholes,magneticdevicesorIC’sthatuseorduplicateclocksignals. •Avoidstubsonthehigh-speedUSBsignalsbecausetheycausesignalreflections.Ifastubis unavoidable,thenthestubshouldbelessthan 200 mils. •Routeallhigh-speedUSBsignaltracesovercontinuousplanes(V CC orGND),withnointerruptions. Avoidcrossingoveranti-etch,commonlyfoundwithplanesplits. ThefollowingsectionsdescribeindetailthespecificguidelinesforUSBPHYLayout. TominimizeEMIemissions,adddecouplingcapacitorswithaferritebeadatpowersupplyterminalsfor theanalog,phase-lockedloop(PLL),anddigitalportionsofthechip.Placethisarrayasclosetothechip aspossibletominimizetheinductanceofthelineandnoisecontributionstothesystem.Ananalogand digitalsupplyexampleisshowninFigure1.Incaseofmultiplepowersupplypinswiththesamefunction, tiethemuptoasinglelow-impedancepointintheboardandthenaddthedecouplingcapacitors,in additiontotheferritebead.ThisarrayofcapsandferritebeadimproveEMIandjitterperformance.Take bothEMIandjitterintoaccountbeforealteringtheconfiguration. Figure1.SuggestedArrayCapacitorsandaFerriteBeadtoMinimizeEMI 2USB2 .0BoardDesignandLayoutGuidelinesSPRAAR7–December 200 7 SubmitDocumentationFeedback www.ti.com 2. 2.2Analog,Digital,andPLLPartitioning 2. 2.3BoardStackup Signal1 PowerPlane GNDPlane Signal 2 2 .2. 4CableConnectorSocket USBPHYLayoutGuide ConsidertherecommendationslistedbelowtoachieveproperESD/EMIperformance: •Usea0 .01 µFcaponeachcablepowerVBUSlinetochassisGNDclosetotheUSBconnectorpin. •Usea0 .01 µFcaponeachcablegroundlinetochassisGNDnexttotheUSBconnectorpin. •Ifvoltageregulatorsareused,placea0 .01 µFcaponbothinputandoutput.Thisistoincreasethe immunitytoESDandreduceEMI.Forotherrequirements,seethedevice-specificdatasheet. Ifseparatepowerplanesareused,theymustbetiedtogetheratonepointthroughalow-impedance bridgeorpreferablythroughaferritebead.Caremustbetakentocapacitivelydecoupleeachpowerrail closetothedevice.Theanalogground,digitalground,andPLLgroundmustbetiedtogethertothe low-impedancecircuitboardgroundplane. BecauseofthehighfrequenciesassociatedwiththeUSB,aprintedcircuitboardwithatleastfourlayers isrecommended;twosignallayersseparatedbyagroundandpowerlayerasshowninFigure2. Figure2.Four-LayerBoardStack-Up Themajorityofsignaltracesshouldrunonasinglelayer,preferablySIGNAL1.Immediatelynexttothis layershouldbetheGNDplane,whichissolidwithnocuts.Avoidrunningsignaltracesacrossasplitin thegroundorpowerplane.Whenrunningacrosssplitplanesisunavoidable,sufficientdecouplingmust beused.MinimizingthenumberofsignalviasreducesEMIbyreducinginductanceathighfrequencies. Shortthecableconnectorsocketsdirectlytoasmallchassisgroundplane(GNDstrap)thatexists immediatelyunderneaththeconnectorsockets.ThisshortsEMI(andESD)directlytothechassisground beforeitgetsontotheUSBcable.Thisetchplaneshouldbeaslargeaspossible,butalltheconductors comingoffconnectorpins1through6musthavetheboardsignalGNDplanerununder.Ifneeded,scoop outthechassisGNDstrapetchtoallowforthesignalgroundtoextendundertheconnectorpins.Note thattheetchescomingfrompins 1and4 (VBUSpowerandGND)shouldbewideandvia-edtotheir respectiveplanesassoonaspossible,respectingthefilteringthatmaybeinplacebetweentheconnector pinandtheplane.SeeFigure3foraschematicexample. PlaceaferriteinserieswiththecableshieldpinsneartheUSBconnectorsockettokeepEMIfromgetting ontothecableshield.Theferritebeadbetweenthecableshieldandgroundmaybevaluedbetween 10 and 50 at 100 MHz;itshouldberesistivetoapproximately1GHz.TokeepEMIfromgettingontothe cablebuspowerwire(averylargeantenna)aferritemaybeplacedinserieswithcablebuspower, VBUS,neartheUSBconnectorpin1.Theferritebeadbetweenconnectorpin1andbuspowermaybe valuedbetween47Ωandapproximately 100 0Ωat 100 MHz.Itshouldcontinuebeingresistiveoutto approximately1GHz,asshowninFigure3. SPRAAR7–December 200 7USB2 .0BoardDesignandLayoutGuidelines3 SubmitDocumentationFeedback www.ti.com U2 FerriteBead VBUS U1 USB Socket 5 4 3 2 1 6 SHIELD_GND GND DP DM +5V SHIELD_GND FerriteBead 2. 2.5ClockRoutings Trace 3W. 4SPRAAR7–December 200 7 SubmitDocumentationFeedback www.ti.com 2. 2.6Crystals/Oscillator PowerPins USB PHY 0. 1µF 0. 001 µF X1 X0 XTAL 2. 2.7DP/DMTrace USBPHYLayoutGuide KeepthecrystalanditsloadcapacitorsclosetotheUSBPHYpins,XIandXO(seeFigure5).Notethat frequenciesfrompowersourcesorlargecapacitorscancausemodulationswithintheclockandshould notbeplacednearthecrystal.Intheseinstances,errorssuchasdroppedpacketsoccur.Aplaceholder foraresistor,inparallelwiththecrystal,canbeincorporatedinthedesigntoassistoscillatorstartup. Powerisproportionaltothecurrentsquared.ThecurrentisI=C*dv/dt,sincedv/dtisafunctionofthe PHY,currentisproportionaltothecapacitiveload.Cuttingtheloadtodecreasesthecurrentbyandthe powerto1/4theoriginalvalue.Formoredetailsoncrystalselection,seetheSelectionandSpecification ofCrystalsforTexasInstrumentsUSB2.0Devices(SLLA 122 ). Figure5.PowerSupplyandClockConnectiontotheUSBPHY PlacetheUSBPHYascloseaspossibletotheUSB2.0connector.Thesignalswingduringhigh-speed operationontheDP/DMlinesisrelativelysmall( 400 mV± 10% ),soanydifferentialnoisepickedupon thetwistedpaircanaffectthereceivedsignal.WhentheDP/DMtracesdonothaveanyshielding,the tracestendtobehavelikeanantennaandpicksupnoisegeneratedbythesurroundingcomponentsin theenvironment.Tominimizetheeffectofthisbehavior: •DP/DMtracesshouldalwaysbematchedlengthsandmustbenomorethan4inchesinlength; otherwise,theeyeopeningmaybedegraded(seeFigure6). •RouteDP/DMtracesclosetogetherfornoiserejectionondifferentialsignals,paralleltoeachotherand withintwomilsinlengthofeachother(startthemeasurementatthechippackageboundary,nottothe ballsorpins). •Ahigh-speedUSBconnectionismadethroughashielded,twistedpaircablewithadifferential characteristicimpedanceof 90 ±15%.Inlayout,theimpedanceofDPandDMshouldeachbe45Ω ± 10% . •DP/DMtracesshouldnothaveanyextracomponentstomaintainsignalintegrity.Forexample,traces cannotberoutedtotwoUSBconnectors. SPRAAR7–December 200 7USB2 .0BoardDesignandLayoutGuidelines5 SubmitDocumentationFeedback www.ti.com Minimize ThisDistance USB PHY Connector D+ D- VBUS GND D- D+ Cable Connector 2. 2.8DP/DMVias 2. 2.9ImagePlanes USBPHYLayoutGuide Figure6.USBPHYConnectorandCableConnector Whenaviamustbeused,increasetheclearancesizearoundittominimizeitscapacitance.Eachvia introducesdiscontinuitiesinthesignal’stransmissionlineandincreasesthechanceofpickingup interferencefromtheotherlayersoftheboard.Becarefulwhendesigningtestpointsontwistedpairlines; through-holepinsarenotrecommended. Animageplaneisalayerofcopper(voltageplaneorgroundplane),physicallyadjacenttoasignalrouting plane.Useofimageplanesprovidesalowimpedance,shortestpossiblereturnpathforRFcurrents.Fora USBboard,thebestimageplaneisthegroundplanebecauseitcanbeusedforbothanaloganddigital circuits. •Donotroutetracessotheycrossfromoneplanetotheother.ThiscancauseabrokenRFreturnpath resultinginanEMIradiatingloopasshowninFigure7.Thisisimportantforhigherfrequencyor repetitivesignals.Therefore,onamulti-layerboard,itisbesttorunallclocksignalsonthesignal planeaboveasolidgroundplane. •Avoidcrossingtheimagepowerorgroundplaneboundarieswithhigh-speedclocksignaltraces immediatelyaboveorbelowtheseparatedplanes.Thisalsoholdstrueforthetwistedpairsignals(DP, DM).AnyunusedareaofthetopandbottomsignallayersofthePCBcanbefilledwithcopperthatis connectedtothegroundplanethroughvias. 6USB2 .0BoardDesignandLayoutGuidelinesSPRAAR7–December 200 7 SubmitDocumentationFeedback www.ti.com Don't Do AnalogPowerPlane UnwantedCapacitance DigitalPowerPlane USBPHYLayoutGuide Figure7.DoNotCrossPlaneBoundaries •Donotoverlapplanesthatdonotreferenceeachother.Forexample,donotoverlapadigitalpower planewithananalogpowerplaneasthisproducesacapacitancebetweentheoverlappingareasthat couldpassRFemissionsfromoneplanetotheother,asshowninFigure8. Figure8.DoNotOverlapPlanes SPRAAR7–December 200 7USB2 .0BoardDesignandLayoutGuidelines7 SubmitDocumentationFeedback www.ti.com SlotinImagePlane RFReturn Current Bad SlotinImagePlane RFReturn Current Better 2. 2.10JTAGInterface 2. 2.11PowerRegulators 3ElectrostaticDischarge(ESD) 3.1IECESDStressingTest ElectrostaticDischarge(ESD) •Avoidimageplaneviolations.TracesthatrouteoveraslotinanimageplaneresultsinapossibleRF returnloop,asshowninFigure9. Figure9.DoNotViolateImagePlanes FortestanddebugoftheUSBPHYonly,anIEEEStandard1149.1-19 90, IEEEStandardTestAccess PortandBoundary-ScanArchitecture(JTAG)andSerialTestandConfigurationInterface(STCI)maybe availableontheSystem-on-Chip(SoC).Ifavailable,keeptheUSBPHYJTAGinterfacelessthansix inches;keepingthisdistanceshortreducesnoisecouplingfromotherdevicesandsignallossdueto resistance. Switchingpowerregulatorsareasourceofnoiseandcancausenoisecouplingifplacedclosetosensitive areasonacircuitboard.Therefore,theswitchingpowerregulatorshouldbekeptawayfromtheDP/DM signals,theexternalclockcrystal(orclockoscillator),andtheUSBPHY. InternationalElectronicCommission(IEC)6 100 0-4-xxisasetofabout25testingspecificationsfromthe IEC.IECESDStressingisdonebothun-poweredandwithpowerapplied,andwiththedevicefunctioning. Theremustbenophysicaldamage,andthedevicemustkeepworkingnormallyaftertheconclusionof thestressing.Typically,equipmenthastopassIECstressingat8kVcontactand15kVairdischarge,or higher.Tomarketproducts/systemsintheEuropeancommunity,allproducts/systemsmustbeCE compliantandhavetheCEMark.ToobtaintheCEMark,allproducts/systemsneedtogothroughand passIECstandardrequirements;forESD,itis6 100 0-4 -2. 6 100 0-4-2requiresthattheproducts/systems passcontactdischargeat8kVandairdischargeat15kV.WhenperforminganIECESDStressing,only pinsaccessibletotheoutsideworldneedtopassthetest.Thesystemintowhichtheintegratedcircuit(IC) isplacedmakesadifferenceinhowwelltheICdoes.Forexample: •CablebetweenthezappointandtheICattenuatethehighfrequenciesinthewaveform. •SeriesinductanceonthePCBboardattenuatesthehighfrequencies. •Unlessthecapacitor’sgroundconnectionisinductive,capacitancetogroundshuntsawayhigh frequencies. ThefollowingsectionsdescribeindetailtheIECESDStressingTestmodesandtesttypes. 8USB2 .0BoardDesignandLayoutGuidelinesSPRAAR7–December 200 7 SubmitDocumentationFeedback www.ti.com 3.1.1TestMode 3.1.2AirDischargeMode 3.1.3TestType 3.2TIComponentLevelIECESDTest 3.3ConstructionofaCustomUSBConnector ElectrostaticDischarge(ESD) TheIECESDStressingtestisdonethroughtwomodes:contactdischargemodeandairdischargemode. Forthecontactdischargetestmode,thepreferredwayisdirectcontactappliedtotheconductivesurfaces oftheequipmentundertest(EUT).InthecaseoftheUSBsystem,theconductivesurfaceistheouter casingoftheUSBconnector.TheelectrodeoftheESDgeneratorisheldincontactwiththeEUTora couplingplanepriortodischarge.Thearcformationiscreatedundercontrolledconditions,insidearelay, resultinginrepeatablewaveforms;however,thisarcdoesnotaccuratelyrecreatethecharacteristicunique tothearcofanactualESDevent. Theairdischargeusuallyappliestoanon-conductivesurfaceoftheEUT.Insteadofadirectcontactwith theEUT,thechargedelectrodeoftheESDgeneratorisbroughtclosetotheEUT,andasparkintheairto theEUTactuatesthedischarge.Comparedtothecontactdischargemode,theairdischargeismore realistictotheactualESDoccurrence.However,duetothevariationsofthearclength,itmaynotbeable toproducerepeatablewaveform. TheIECESDStressingtesthastwotesttypes:directdischargeandindirectdischarge.Directdischarge isappliesdirectlytothesurfaceorthestructureoftheEUT.Itincludesbothcontactdischargeandair dischargemodes.IndirectdischargeappliestoacouplingplaneinthevicinityoftheEUT.Theindirect dischargeisusedtosimulatepersonaldischargetoobjectswhichareadjacenttotheEUT.Itincludes contactdischargemodeonly. TIComponentLevelIECESDTesttestsonlytheICterminalsthatareexposedinsystemlevel applications.Itcanbeusedtodeterminetherobustnessofon-chipprotectionandthelatch-upimmunity. TheICcanonlypasstheTIComponentLevelIECESDtestwhenthereisnolatch-upandICisfully functionalafterthetest. AstandardUSBconnector,eithertypeAortypeB,providesgoodESDprotection.However,ifacustom USBconnectorisdesired,thefollowingguidelinesshouldbeobservedtoensuregoodESDprotection. •Thereshouldbeaneasilyaccessibleshieldplatenexttotheconnectorforair-dischargemode purpose. •TietheoutershieldoftheconnectortoGND.Whenacableisinsertedintotheconnector,theshieldof thecableshouldfirstmakecontactwiththeoutershield. •IftheconnectorincludespowerandGND,theleadofpowerandGNDneedtobelongerthanthe leadsofsignal. •Theconnectorneedstohaveakeytoensureproperinsertionofthecable. •SeethestandardUSBconnectorforreference. SPRAAR7–December 200 7USB2 .0BoardDesignandLayoutGuidelines9 SubmitDocumentationFeedback www.ti.com 3.4ESDProtectionSystemDesignConsideration 4References References ESDprotectionsystemdesignconsiderationiscoveredinSection2ofthisdocument.Thefollowingare additionalconsiderationsforESDprotectioninasystem. •MetallicshieldingforbothESDandEMI •ChassisGNDisolationfromtheboardGND •AirgapdesignedonboardtoabsorbESDenergy •ClampingdiodestoabsorbESDenergy •CapacitorstodivertESDenergy •TheuseofexternalESDcomponentsontheDP/DMlinesmayaffectsignalqualityandarenot recommended. USB2 .0Specification,Intel , 20 00, http://www .usb. org/developers/docs/ •HighSpeedUSBPlatformDesignGuidelines,Intel , 20 00, http://www.intel.com/technology /usb/ download /usb2 dg_R1 _0. pdf •SelectionandSpecificationofCrystalsforTexasInstrumentsUSB2.0Devices(SLLA 122 ) 1 0USB2 .0BoardDesignandLayoutGuidelinesSPRAAR7–December 200 7 SubmitDocumentationFeedback IMPORTANTNOTICE TexasInstrumentsIncorporatedanditssubsidiaries(TI)reservetherighttomakecorrections,modifications,enhancements, improvements,andotherchangestoitsproductsandservicesatanytimeandtodiscontinueanyproductorservicewithoutnotice. Customersshouldobtainthelatestrelevantinformationbeforeplacingordersandshouldverifythatsuchinformationiscurrentand complete.AllproductsaresoldsubjecttoTI’stermsandconditionsofsalesuppliedatthetimeoforderacknowledgment. TIwarrantsperformanceofitshardwareproductstothespecificationsapplicableatthetimeofsaleinaccordancewithTI’s standardwarranty.TestingandotherqualitycontroltechniquesareusedtotheextentTIdeemsnecessarytosupportthis warranty.Exceptwheremandatedbygovernmentrequirements,testingofallparametersofeachproductisnotnecessarily performed. TIassumesnoliabilityforapplicationsassistanceorcustomerproductdesign.Customersareresponsiblefortheirproductsand applicationsusingTIcomponents.Tominimizetherisksassociatedwithcustomerproductsandapplications,customersshould provideadequatedesignandoperatingsafeguards. TIdoesnotwarrantorrepresentthatanylicense,eitherexpressorimplied,isgrantedunderanyTIpatentright,copyright,mask workright,orotherTIintellectualpropertyrightrelatingtoanycombination,machine,orprocessinwhichTIproductsorservices areused.InformationpublishedbyTIregardingthird-partyproductsorservicesdoesnotconstitutealicensefromTItousesuch productsorservicesorawarrantyorendorsementthereof.Useofsuchinformationmayrequirealicensefromathirdpartyunder thepatentsorotherintellectualpropertyofthethirdparty,oralicensefromTIunderthepatentsorotherintellectualpropertyofTI. ReproductionofTIinformationinTIdatabooksordatasheetsispermissibleonlyifreproductioniswithoutalterationandis accompaniedbyallassociatedwarranties,conditions,limitations,andnotices.Reproductionofthisinformationwithalterationisan unfairanddeceptivebusinesspractice.TIisnotresponsibleorliableforsuchaltereddocumentation.Informationofthirdparties maybesubjecttoadditionalrestrictions. ResaleofTIproductsorserviceswithstatementsdifferentfromorbeyondtheparametersstatedbyTIforthatproductorservice voidsallexpressandanyimpliedwarrantiesfortheassociatedTIproductorserviceandisanunfairanddeceptivebusiness practice.TIisnotresponsibleorliableforanysuchstatements. TIproductsarenotauthorizedforuseinsafety-criticalapplications(suchaslifesupport)whereafailureoftheTIproductwould reasonablybeexpectedtocauseseverepersonalinjuryordeath,unlessofficersofthepartieshaveexecutedanagreement specificallygoverningsuchuse.Buyersrepresentthattheyhaveallnecessaryexpertiseinthesafetyandregulatoryramifications oftheirapplications,andacknowledgeandagreethattheyaresolelyresponsibleforalllegal,regulatoryandsafety-related requirementsconcerningtheirproductsandanyuseofTIproductsinsuchsafety-criticalapplications,notwithstandingany applications-relatedinformationorsupportthatmaybeprovidedbyTI.Further,BuyersmustfullyindemnifyTIandits representativesagainstanydamagesarisingoutoftheuseofTIproductsinsuchsafety-criticalapplications. TIproductsareneitherdesignednorintendedforuseinmilitary/aerospaceapplicationsorenvironmentsunlesstheTIproductsare specificallydesignatedbyTIasmilitary-gradeor"enhancedplastic."OnlyproductsdesignatedbyTIasmilitary-grademeetmilitary specifications.BuyersacknowledgeandagreethatanysuchuseofTIproductswhichTIhasnotdesignatedasmilitary-gradeis solelyattheBuyer'srisk,andthattheyaresolelyresponsibleforcompliancewithalllegalandregulatoryrequirementsin connectionwithsuchuse. TIproductsareneitherdesignednorintendedforuseinautomotiveapplicationsorenvironmentsunlessthespecificTIproducts aredesignatedbyTIascompliantwithISO/TS16949requirements.Buyersacknowledgeandagreethat,iftheyuseany non-designatedproductsinautomotiveapplications,TIwillnotberesponsibleforanyfailuretomeetsuchrequirements. FollowingareURLswhereyoucanobtaininformationonotherTexasInstrumentsproductsandapplicationsolutions: ProductsApplications Amplifiersamplifier.ti.comAudiowww.ti.com/audio DataConvertersdataconverter.ti.comAutomotivewww.ti.com/automotive DSPdsp.ti.comBroadbandwww.ti.com/broadband Interfaceinterface.ti.comDigitalControlwww.ti.com/digitalcontrol Logiclogic.ti.comMilitarywww.ti.com/military PowerMgmtpower.ti.comOpticalNetworkingwww.ti.com/opticalnetwork Microcontrollersmicrocontroller.ti.comSecuritywww.ti.com/security RFIDwww.ti-rfid.comTelephonywww.ti.com/telephony LowPowerwww.ti.com/lpwVideo&Imagingwww.ti.com/video Wireless Wirelesswww.ti.com/wireless MailingAddress:TexasInstruments,PostOfficeBox655 303 ,Dallas,Texas7 526 5 Copyright 20 07,TexasInstrumentsIncorporated