SystemVerilog For Design phần 9 pps

Chapter 11: A Complete Design Modeled with SystemVerilog 321 11.6 Testbench The testbench send and receive methods for the Utopia interface are encapsulated in the UtopiaMethod interface. Example 11-6: UtopiaMethod interface for encapsulating test methods interface UtopiaMethod; task automatic Initialise (); endtask task automatic Send (input ATMCellType Pkt, input int PortID); static int PacketID; PacketID++; Pkt.tst.PortID = PortID; Pkt.tst.PacketID = PacketID; // iterate through bytes of packet, deasserting // Start Of Cell indicater @(negedge Utopia.clk_out); Utopia.clav <= 1; for (int i=0; i<=52; i++) begin // If not enabled, loop while (Utopia.en === 1'b1) @(negedge Utopia.clk_out); // Assert Start Of Cell indicater, assert enable, // send byte 0 (i==0) Utopia.soc <= (i==0) ? 1'b1 : 1'b0; Utopia.data <= Pkt.Mem[i]; @(negedge Utopia.clk_out); end Utopia.data <= 8'bx; Utopia.clav <= 0; endtask task automatic Receive (input int PortID); ATMCellType Pkt; Utopia.clav = 1; while (Utopia.soc!==1'b1 && Utopia.en!==1'b0) @(negedge Utopia.clk_out); for (int i=0; i<=52; i++) begin // If not enabled, loop while (Utopia.en!==1'b0) @(negedge Utopia.clk_out); Pkt.Mem[i] = Utopia.data; @(negedge Utopia.clk_out); end 322 SystemVerilog for Design Utopia.clav = 0; // Write Rxed data to logfile `ifdef verbose $write("Received packet at port %0d from port %0d PKT(%0d)\n", PortID, Pkt.tst.PortID, Pkt.tst.PacketID); //PortID, Pkt.nni.Payload[0], Pkt.nni.Payload[1:4]); `endif endtask endinterface The testbench HostWrite and HostRead methods for the CPU interface are encapsulated in the CPUMethod interface. Example 11-7: CPUMethod interface for encapsulating test methods interface CPUMethod; task automatic Initialise_Host (); CPU.BusMode <= 1; CPU.Addr <= 0; CPU.DataIn <= 0; CPU.Sel <= 1; CPU.Rd_DS <= 1; CPU.Wr_RW <= 1; endtask task automatic HostWrite (int a, CellCfgType d); // configure #10 CPU.Addr <= a; CPU.DataIn <= d; CPU.Sel <= 0; #10 CPU.Wr_RW <= 0; while (CPU.Rdy_Dtack!==0) #10; #10 CPU.Wr_RW <= 1; CPU.Sel <= 1; while (CPU.Rdy_Dtack==0) #10; endtask task automatic HostRead (int a, output CellCfgType d); #10 CPU.Addr <= a; CPU.Sel <= 0; #10 CPU.Rd_DS <= 0; while (CPU.Rdy_Dtack!==0) #10; #10 d = CPU.DataOut; CPU.Rd_DS <= 1; CPU.Sel <= 1; while (CPU.Rdy_Dtack==0) #10; endtask endinterface Chapter 11: A Complete Design Modeled with SystemVerilog 323 The main testbench module uses the encapsulated methods listed above. Example 11-8: Utopia ATM testbench `include "definitions.sv" module test; parameter int NumRx = `RxPorts; parameter int NumTx = `TxPorts; // NumRx x Level 1 Utopia Rx Interfaces Utopia Rx[0:NumRx-1] (); // NumTx x Level 1 Utopia Tx Interfaces Utopia Tx[0:NumTx-1] (); // Intel-style Utopia parallel management interface CPU mif (); // Miscellaneous control interfaces logic rst; logic clk; logic Initialised; `include "./testbench_instance.sv" task automatic RandomPkt (inout ATMCellType Pkt, inout seed); Pkt.uni.GFC = $random(seed); Pkt.uni.VPI = $random(seed) & 8'hff; Pkt.uni.VCI = $random(seed); Pkt.uni.CLP = $random(seed); Pkt.uni.PT = $random(seed); Pkt.uni.HEC = hec(Pkt.Mem[0:3]); for (int i=0; i<=47; i++) begin Pkt.uni.Payload[i] = 47-i; //$random(seed); end endtask logic [7:0] syndrom[0:255]; initial begin: gen_syndrom int i; logic [7:0] sndrm; for (i = 0; i < 256; i = i + 1 ) begin sndrm = i; repeat (8) begin if (sndrm[7] === 1'b1) sndrm = (sndrm << 1) ^ 8'h07; 324 SystemVerilog for Design else sndrm = sndrm << 1; end syndrom[i] = sndrm; end end // Function to compute the HEC value function automatic logic [7:0] hec (logic [31:0] hdr); logic [7:0] rtn; rtn = 8'h00; repeat (4) begin rtn = syndrom[rtn ^ hdr[31:24]]; hdr = hdr << 8; end rtn = rtn ^ 8'h55; return rtn; endfunction // System Clock and Reset initial begin #0 rst = 0; clk = 0; #5 rst = 1; #5 clk = 1; #5 rst = 0; clk = 0; forever begin #5 clk = 1; #5 clk = 0; end end CellCfgType lookup [255:0]; // copy of look-up table function logic [0:NumTx-1] find (logic [11:0] VPI); for (int i=0; i<=255; i++) begin if (lookup[i].VPI == VPI) begin return lookup[i].FWD; end end return 0; endfunction // Stimulus initial begin automatic int seed=1; CellCfgType CellFwd; $display("Configuration RxPorts=%0d TxPorts=%0d", Chapter 11: A Complete Design Modeled with SystemVerilog 325 `RxPorts, `TxPorts); mif.Method.Initialise_Host(); // Configure through Host interface repeat (10) @(negedge clk); $display("Loading Memory"); for (int i=0; i<=255; i++) begin CellFwd.FWD = i; `ifdef FWDALL CellFwd.FWD = '1; `endif CellFwd.VPI = i; mif.Method.HostWrite(i, CellFwd); lookup[i] = CellFwd; end // Verify memory $display("Verifying Memory"); for (int i=0; i<=255; i++) begin mif.Method.HostRead(i, CellFwd); if (lookup[i] != CellFwd) begin $display("Error, Mem Location 0x%h contains 0x%h, expected 0x%h", i, lookup[i], CellFwd); $stop; end end $display("Memory Verified"); Initialised=1; repeat (5000000) @(negedge clk); $display("Error Timeout"); $finish; end int TxPktCtr [0:NumTx-1]; logic [0:NumRx-1] RxGenInProgress; genvar RxIter; genvar TxIter; generate // replicate access to ports for (RxIter=0; RxIter<NumRx; RxIter++) begin: RxGen initial begin: Sender int seed; logic [0:NumTx-1] TxPortTarget; ATMCellType Pkt; Rx[RxIter].data=0; Rx[RxIter].soc=0; 326 SystemVerilog for Design Rx[RxIter].en=1; Rx[RxIter].clav=0; Rx[RxIter].ready=0; RxGenInProgress[RxIter] = 1; wait (Initialised === 1'b1); seed=RxIter+1; Rx[RxIter].Method.Initialise(); repeat (200) begin RandomPkt(Pkt, seed); TxPortTarget = find(Pkt.uni.VPI); // Increment counter if output packet expected for (int i=0; i<NumTx; i++) begin if (TxPortTarget[i]) begin TxPktCtr[i]++; //$display("port %0d ->> %0d", RxIter, i); end end Rx[RxIter].Method.Send(Pkt, RxIter); //$display("Port %d sent packet", RxIter); repeat ($random(seed)%200) @(negedge clk); end RxGenInProgress[RxIter] = 0; end end endgenerate // Response - open files for response generate for (TxIter=0; TxIter<NumTx; TxIter++) begin: TxGen initial begin: Receiver wait (Tx[TxIter].reset===1); wait (Tx[TxIter].reset===0); forever begin Tx[TxIter].Method.Receive(TxIter); TxPktCtr[TxIter] ; end end end endgenerate // Check for all detected packets logic [0:NumTx-1] TxDetectEnd; generate for (TxIter=0; TxIter<NumTx; TxIter++) begin: TxDetect initial begin Chapter 11: A Complete Design Modeled with SystemVerilog 327 TxDetectEnd[TxIter] = 1'b1; wait (Initialised === 1'b1); wait (RxGenInProgress === 0); wait (TxPktCtr[TxIter] == 0) TxDetectEnd[TxIter] = 1'b0; $display("TxPktCtr[%0d] == %d", TxIter, TxPktCtr[TxIter]); end end endgenerate initial begin wait (Initialised === 1'b1); wait (RxGenInProgress === 0); wait (TxDetectEnd === 0); $finish; end endmodule The testbench instance of the design is contained in a separate file, so that pre-and post-synthesis versions can be used. squat #(NumRx, NumTx) squat(Rx, Tx, mif, rst, clk); 11.7 Summary This chapter has presented a larger example, modeled using the SystemVerilog extensions to the Verilog HDL. Structures are used to encapsulate all the variables related to NNI and UNI packets. This allows these many individual signals to be referenced using the structure names, instead of having to reference each signal individ- ually. This encapsulation simplifies the amount of code required to represent complex sets of information. The concise code is easier to read, to test, and to maintain. These NNI and UNI structures are grouped together as a union, which allows a single piece of storage to represent either type of packet. Because the union is packed, a value can be stored as one packet type, and retrieved as the other packet type. This further simplifies the code required to transfer a packet from one format to another. 328 SystemVerilog for Design The communication between the major blocks of the design is encapsulated into interfaces. This moves the declarations of the several ports of each module in the design to a central location. The port declarations within each module are minimized to a single interface port. The redundancy of declaring the same ports in sev- eral modules is eliminated. SystemVerilog constructs are also used to simplify the code required to verify the design. The same union used to store the NNI and UNI packets is used to store test values as an array of bytes. The testbench can load the union variable using bytes, and the value can be read by the design as an NNI or UNI packet. It is not necessary to copy test values into each variable that makes up a packet. SystemVerilog includes a large number of additional enhancements for verification that are not illustrated in this example. These enhancements are covered in the companion book, SystemVerilog for Verification 1 . 1. Spear, Chris “SystemVerilog for Verification”, Norwell, MA: Springer 2006, 0-387-27036-1. Chapter 12 Behavioral and Transaction Level Modeling E 12-0: PLE 12-0: R E 12-0. his chapter defines Transaction Level Modeling (TLM) as an adjunct to behavioral modeling. The chapter explains how TLM can be used, and shows how SystemVerilog is suited to TLM. Behavioral modeling can be used to provide a high level executable specification for development of both RTL code and the testbench. Transaction level modeling allows the system executable specifica- tion to be partitioned into executable specifications of the sub- systems. The executable specifications shown in this chapter are generally not considered synthesizable. However, there are some tools called “high level” or “behavioral” synthesis tools which are able to han- dle particular categories of behavioral or transaction level model- ing. The topics covered in this chapter include: • Definition of a transaction • Transaction level model of a bus • Multiple slaves • Arbitration between multiple masters • Semaphores • Interfacing transaction level with register transfer level models T 330 SystemVerilog for Design 12.1 Behavioral modeling Behavioral modeling (or behavior level modeling) is a style where the state machines of the control logic are not explicitly coded. An implicit state machine is an always block which has more than one event control in it. For instance, the following code generates a 1 pulse after the reset falls: always begin do @(posedge clock) while (reset); @(posedge clock) a = 1; @(posedge clock) a = 0; end An RTL description would have an explicit state register, as fol- lows: logic [1:0] state; always_ff @(posedge clock) if (reset) state = 0; else if (state == 0) begin state = 1; a = 1; end else if (state == 1) begin state = 2; a = 0; end else state = 0; Note that there is an even more abstract style of behavioral model- ing that is not cycle-accurate, and therefore can be used before the detailed scheduling of the design as an executable specification. An example is an image processing algorithm that is to be implemented in hardware. 12.2 What is a transaction? In everyday life, a transaction is an interaction between two people or organizations to transfer information, money, etc. In a digital system, a transaction is a transfer of data and control between two subsystems. This normally means a request and a response. A trans- action has attributes such as type, data, start time, duration, and sta- tus. It may also contain sub-transactions. [...]... used in verification, and are therefore described in the companion book, SystemVerilog for Verification1 1 Spear, Chris SystemVerilog for Verification”, Norwell, MA: Springer 2006, 0-387-27036-1 354 SystemVerilog for Design 12.8 Summary Transactions have traditionally been used in system modeling and in hardware verification TLM has not been used much by hardware designers One of the reasons is that... style presented in this chapter Appendix A The SystemVerilog Formal Definition (BNF) This appendix contains the formal definition of the SystemVerilog standard The definition is taken directly from Annex A of the IEEE 1800-2005 SystemVerilog Language Reference Manual (SystemVerilog LRM)1 The formal definition of SystemVerilog is described in BackusNaur Form (BNF) The variant of BNF used in this appendix... interface Membus; extern forkjoin task ReadMem (input logic [ 19: 0] Address, output logic [15:0] Data, bit Error); extern forkjoin task WriteMem (input logic [ 19: 0] Address, input logic [15:0] Data, output bit Error); extern task Request(); extern task Relinquish(); endinterface 336 SystemVerilog for Design module Tester (interface Bus); logic [15:0] D; logic E; int A; initial begin for (A = 0; A < 21'h100000;... // repeated from previous example logic [15:0] D; logic E; int A; 346 SystemVerilog for Design initial begin for (A = 0; A < 21'h100000; A = A + 21'h40000) begin fork #1000; Bus.WriteMem(A[ 19: 0], 0, E); join if (E) $display ("%t bus error on write %h", $time, A); else $display ("%t write OK %h", $time, A); fork #1000; Bus.ReadMem(A[ 19: 0], D, E); join if (E) $display ("%t bus error on read %h", $time,... else $display ("%t write OK %h", $time, A); Bus.Relinquish; end join fork #1000; begin Bus.Request; Bus.ReadMem(A[ 19: 0], D, E); if (E) $display("%t bus error on read %h", $time, A); else $display ("%t read OK %h", $time, A); Bus.Relinquish; end join end : loop end : test_block endmodule 340 SystemVerilog for Design // Memory Modules // forkjoin task model delays if OK (last wins) module Memory (interface... #50 mrdc = 0; //min delay fork begin: ok @(negedge XACK) Data = ~ DAT; EndRead(); @(posedge XACK) Error = 0; disable timeout; end begin: timeout // Timeout if no acknowledgement #90 0 Error = 1; EndRead(); disable ok; end join FreeBus(); Master_State = IDLE; endtask task WriteMem (input logic [ 19: 0] Address, input logic [15:0] Data, output logic Error); 350 SystemVerilog for Design assert (Master_State... int Number = 1; // number of master for // request/grant enum {IDLE, READY, READ, WRITE} Master_State; logic [ 19: 0] adr logic [15:0] dat logic mrdc logic mwtc logic breq = = = = = 'z; 'z; 1; 1; 1; assign assign assign assign assign Wires.ADR = adr; Wires.DAT = dat; Wires.MRDC = mrdc; Wires.MWTC = mwtc; Wires.BREQ[Number] = breq; 344 logic logic SystemVerilog for Design cbrq = 1; busy = 1; assign Wires.CBRQ... D; E; LOWER = 20'h00000; UPPER = 20'h7ffff; Mem[LOWER:UPPER]; task ReadMem(input logic [ 19: 0] Address, output logic [15:0] Data, output logic Error); if (Address >= LOWER && Address = LOWER && Address Mem[Address] = Data;... 21'h100000; A = A + 21'h40000) begin fork #1000; Bus.WriteMem(A[ 19: 0], 0, E); join if (E) $display ("%t bus error on write %h", $time, A); else $display ("%t write OK %h", $time, A); fork #1000; Bus.ReadMem(A[ 19: 0], D, E); join if (E) $display ("%t bus error on read %h", $time, A); else $display ("%t read OK %h", $time, A); end end endmodule // Memory Modules // forkjoin task model delays if OK (last... endmodule : Clock module Tester (interface Bus); logic [15:0] D; logic E; int A; initial begin for (A = 0; A < 21'h100000; A = A + 21'h40000) begin fork #1000; Bus.WriteMem(A[ 19: 0], 0, E); join if (E) $display ("%t bus error on write %h", $time, A); else $display ("%t write OK %h", $time, A); fork #1000; Bus.ReadMem(A[ 19: 0], D, E); join if (E) $display ("%t bus error on read %h", $time, A); else $display ("%t . the code required to transfer a packet from one format to another. 328 SystemVerilog for Design The communication between the major blocks of the design is encapsulated into interfaces. This moves. Relinquish(); endinterface 336 SystemVerilog for Design module Tester (interface Bus); logic [15:0] D; logic E; int A; initial begin for (A = 0; A < 21'h100000; A = A + 21'h40000) begin fork #1000;. example. These enhancements are covered in the companion book, SystemVerilog for Verification 1 . 1. Spear, Chris SystemVerilog for Verification”, Norwell, MA: Springer 2006, 0-387-27036-1. Chapter