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236 SystemVerilog for Design .reg_file_sel(reg_file_sel), .zero_enable(zero_enable), .carry_enable(carry_enable), .polarity(polarity), .option(isoption), .tris(istris), .instruct_reg(instruct_reg) ); register_files regs ( .dout(reg_file_out), .tmr0_reg(tmr0_reg), .status_reg(status_reg), .fsr_reg(fsr_reg), .port_a(port_a), .port_b(port_b), .port_c(port_c), .trisa(trisa), .trisb(trisb), .trisc(trisc), .option_reg(option_reg), .w_reg(w_reg), .instruct_reg(instruct_reg), .program_data(program_data), .port_a_pins(port_a_pins), .data_bus(data_bus), .address(reg_file_addr), .clk(clk), .resetN(resetN), .skip(skip), .reg_file_sel(reg_file_sel), .zero_enable(zero_enable), .carry_enable(carry_enable), .w_reg_enable(w_reg_enable), .reg_file_enable(reg_file_enable), .zero(zero), .carry(carry), .special_reg_sel(special_reg_sel), .isoption(isoption), .istris(istris) ); alu alu ( .y(data_bus), .carry_out(carry), .zero_out(zero), .a(alu_a), .b(alu_b), Chapter 9: SystemVerilog Design Hierarchy 237 .opcode(alu_opcode), .carry_in(status_reg[0]) ); glue_logic glue ( .port_b_pins(port_b_pins), .port_c_pins(port_c_pins), .alu_a(alu_a), .alu_b(alu_b), .expan_out(expan_out), .expan_addr(expan_addr), .reg_file_addr(reg_file_addr), .reg_file_enable(reg_file_enable), .special_reg_sel(special_reg_sel), .expan_read(expan_read), .expan_write(expan_write), .skip(skip), .instruct_reg(instruct_reg), .program_counter(program_counter), .port_a(port_a), .port_b(port_b), .port_c(port_c), .data_bus(data_bus), .expan_in(expan_in), .fsr_reg(fsr_reg), .tmr0_reg(tmr0_reg), .status_reg(status_reg), .w_reg(w_reg), .reg_file_out(reg_file_out), .alu_a_sel(alu_a_sel), .alu_b_sel(alu_b_sel), .reg_file_sel(reg_file_sel), .polarity(polarity), .zero(zero) ); endmodule Named port connection advantages An advantage of named port connections is that they reduce the risk of an inadvertent design error because a net was connected to the wrong port. In addition, the named port connections better docu- ment the intent of the design. In the example above, it is very obvi- ous which signal is intended to be connected to which port of the name d por t connections are a preferred style 238 SystemVerilog for Design flip-flop, without having to go look at the source code of each mod- ule. Many companies have internal modeling guidelines that require using the named port connection style in netlists, because of these advantages. Named port connection disadvantages The disadvantage of the named port connection style is that it is very verbose. Netlists can contain tens or hundreds of module instances, and each instance can have dozens of ports. Both the name of the port and the name of the net connected to the port must be listed for each and every port connection in the netlist. Port and net names can be up to 1024 characters long in Verilog tools. When long, descriptive port names and net names are used, and there are many ports for each module name, the size and verbosity of a netlist using named port connections can become excessively large and difficult to maintain. 9.4.1 Implicit .name port connections SystemVerilog provides three enhancements that greatly simplify netlists: .name (pronounced “dot-name”) port connections, .* (pronounced “dot-star”) port connections, and interfaces. The .name and .* styles are discussed in the following subsections, and interfaces are presented in Chapter 10. The SystemVerilog .name port connection syntax combines the advantages of both the conciseness of ordered port connections with self-documenting code and order independence of named-port connections, eliminating the disadvantages of each of the two Ver- ilog styles. In many Verilog netlists, especially top-level netlists that connect major design blocks together, it is common to use the same name for both the port name and the name of the net con- nected to the port. For example, the module might have a port called data, and the interconnected net is also called data. Using Verilog’s named port connection style, it is necessary to repeat the name twice in order to connect the net to the port, for example: .data(data). SystemVerilog simplifies the named port connection syntax by allowing just the port name to be specified. When only the port name is given, SystemVerilog infers that a net or variable of the same name will automatically be connected to the name d por t connections are verbose .name i s an abbreviation of named port connections .name s i mp lifi es connections to module instances .name i n f ers a connection of a net and port of the same name Chapter 9: SystemVerilog Design Hierarchy 239 port. This means the verbose Verilog style of .data(data) can be reduced to simply .data. When the name of a net does not match the port to which it is to be connected, the Verilog named port connection is used to explicitly connect the net to the port. As with the Verilog named port connec- tions, an unconnected port can be left either unspecified, or explic- itly named with an empty parentheses set to show that there is no connection. Example 9-4 lists the simple processor model shown previously in example 9-3, but with SystemVerilog’s .name port connection style for all nets that are the same name as the port. Compare this example to example 9-3, to see how the .name syntax reduces the verbosity of named port connections. Using the .name connection style, the netlist is easier to read and to maintain. Example 9-4: Simple netlist using SystemVerilog’s .name port connections module miniPIC ( inout wire [7:0] port_a_pins, inout wire [7:0] port_b_pins, inout wire [7:0] port_c_pins, input wire clk, input wire resetN ); wire [11:0] instruct_reg, program_data; wire [10:0] program_counter, program_address; wire [ 7:0] tmr0_reg, status_reg, fsr_reg, w_reg, option_reg, reg_file_out, port_a, port_b, port_c, trisa, trisb, trisc, data_bus, alu_a, alu_b; wire [ 6:0] reg_file_addr; wire [ 3:0] alu_opcode; wire [ 1:0] alu_a_sel, alu_b_sel; wire reg_file_sel, special_reg_sel, reg_file_enable, w_reg_enable, zero_enable, carry_enable, skip, isoption, istris, polarity, carry, zero; pc_stack pcs ( // module instance with .name port connections .program_counter, .program_address, .clk, .resetN, .instruct_reg, .data_bus, .name can b e combined with named port connections 240 SystemVerilog for Design .status_reg ); prom prom ( .dout(program_data), .clk, .address(program_address) ); instruction_decode decoder ( .alu_opcode, .alu_a_sel, .alu_b_sel, .w_reg_enable, .reg_file_sel, .zero_enable, .carry_enable, .polarity, .option(isoption), .tris(istris), .instruct_reg ); register_files regs ( .dout(reg_file_out), .tmr0_reg, .status_reg, .fsr_reg, .port_a, .port_b, .port_c, .trisa, .trisb, .trisc, .option_reg, .w_reg, .instruct_reg, .program_data, .port_a_pins, .data_bus, .address(reg_file_addr), .clk, .resetN, .skip, .reg_file_sel, .zero_enable, .carry_enable, .w_reg_enable, Chapter 9: SystemVerilog Design Hierarchy 241 .reg_file_enable, .zero, .carry, .special_reg_sel, .isoption, .istris ); alu alu ( .y(data_bus), .carry_out(carry), .zero_out(zero), .a(alu_a), .b(alu_b), .opcode(alu_opcode), .carry_in(status_reg[0]) ); glue_logic glue ( .port_b_pins, .port_c_pins, .alu_a, .alu_b, .reg_file_addr, .reg_file_enable, .special_reg_sel, .skip, .instruct_reg, .program_counter, .port_a, .port_b, .port_c, .data_bus, .fsr_reg, .tmr0_reg, .status_reg, .w_reg, .reg_file_out, .alu_a_sel, .alu_b_sel, .reg_file_sel, .polarity, .zero ); endmodule 242 SystemVerilog for Design In order to infer a connection to a named port, the net or variable must match both the port name and the port vector size. In addition, the types on each side of the port must be compatible. Incompatible types are any port connections that would result in a warning or error if a net or variable is explicitly connected to the port. The rules for what connections will result in errors or warnings are defined in the IEEE 1364-2005 Verilog standard, in section 12.3.10 1 . For example, a tri1 pullup net connected to a tri0 pull- down net through a module port will result in a warning, per the Verilog standard. Such a connection will not be inferred by the .name syntax. These restrictions reduce the risk of unintentional connections being inferred by the .name connection style. Any mismatch in vector sizes and/or types can still be forced, using the full named port connection style, if that is the intent of the designer. Such mis- matches must be explicitly specified, however. They will not be inferred from the .name syntax. 9.4.2 Implicit .* port connection SystemVerilog provides an additional short cut to simplify the spec- ification of large netlists. The .* syntax indicates that all ports and nets (or variables) of the same name should automatically be con- nected together for that module instance. As with the .name syn- tax, for a connection to be inferred, the name and vector size must match exactly, and the types connected together must be compati- ble. Any connections that cannot be inferred by .* must be explicitly connected together, using Verilog’s named port connec- tion syntax. Example 9-5 illustrates the use of SystemVerilog’s .* port con- nection syntax. 1. IEEE Std 1364-2005, Language Reference Manual (LRM). See page xxvii of this book for details. .name connection inference rules . *i n f ers connections of all nets and ports of the same name Chapter 9: SystemVerilog Design Hierarchy 243 Example 9-5: Simple netlist using SystemVerilog’s .* port connections module miniPIC ( inout wire [7:0] port_a_pins, inout wire [7:0] port_b_pins, inout wire [7:0] port_c_pins, input wire clk, input wire resetN ); wire [11:0] instruct_reg, program_data; wire [10:0] program_counter, program_address; wire [ 7:0] tmr0_reg, status_reg, fsr_reg, w_reg, option_reg, reg_file_out, port_a, port_b, port_c, trisa, trisb, trisc, data_bus, alu_a, alu_b; wire [ 6:0] reg_file_addr; wire [ 3:0] alu_opcode; wire [ 1:0] alu_a_sel, alu_b_sel; wire reg_file_sel, special_reg_sel, reg_file_enable, w_reg_enable, zero_enable, carry_enable, skip, isoption, istris, polarity, carry, zero; pc_stack pcs ( // module instance with .* port connections .* ); prom prom ( .*, .dout(program_data), .address(program_address) ); instruction_decode decoder ( .*, .option(isoption), .tris(istris) ); register_files regs ( .*, .dout(reg_file_out), .address(reg_file_addr) ); alu alu ( .y(data_bus), .carry_out(carry), .zero_out(zero), .a(alu_a), 244 SystemVerilog for Design .b(alu_b), .opcode(alu_opcode), .carry_in(status_reg[0]) ); glue_logic glue ( .* ); endmodule 9.5 Net aliasing SystemVerilog adds an alias statement that allows two different names to reference the same net. For example: wire clock; wire clk; alias clk = clock; The net clk is an alias for clock, and clock is an alias for clk. Both names refer to the same logical net. Defining an alias for a net does not copy the value of one net to some other net. In the preceding example, clk is not a copy of clock. Rather, clk is clock, just referenced by a different name. Any value changes on clock will be seen by clk, since they are the same net. Conversely, any value changes on clk will be seen by clock, since they are the same net. SystemVerilog adds two new types of hierarchy blocks that can also have ports, interfaces (see Chapter 10), and programs (refe r to the companion book, SystemVerilog for Verification). Instances of these new blocks can also use the .name and .* inferred port connections. SystemVerilog also allows calls to functions and tasks to use named connections, including the .name and .* shortcuts. This is covered in section 6.3.5 on page 156. NOTE an a li as crea t es two or more names for the same net Chapter 9: SystemVerilog Design Hierarchy 245 alias versus assign The alias statement is not the same as the assign continuous assignment. An assign statement continuously copies an expres- sion on the right-hand side of the assignment to a net or variable on the left-hand side. This is a one-way copy. The net or variable on the left-hand side reflects any changes to the expression on the right-hand side. But, if the value of the net or variable on the left- hand side is changed, the change is not reflected back to the expres- sion on the right-hand side. An alias works both ways, instead of one way. Any value changes to the net name on either side of the alias statement will be reflected on the net name on the other side. This is because an alias is effec- tively one net with two different names. Multiple aliases Several nets can be aliased together. A change on any of the net names will be reflected on all of the nets that are aliased together. wire reset, rst, resetN, rstN; alias rst = reset; alias reset = resetN; alias resetN = rstN; The previous set of aliases can also be abbreviated to a single state- ment containing a series of aliases, as follows: alias rst = reset = resetN = rstN; The order in which nets are listed in an alias statement does not matter. An alias is not an assignment of values, it is a list of net names that refer to the same object. 9.5.1 Alias rules SystemVerilog imposes several restrictions on what signals can be aliased to another name. • Only the net types can be aliased. Variables cannot be aliased. Verilog’s net types are wire, uwire, wand, wor, tri, triand, trior, tri0, tri1, and trireg. an a li as i s no t an assignment c h anges on any aliased net affect all aliased nets a li ases are no t order dependent on l y ne tt ypes can be aliased [...]... with the discrete signals Example 10-2 shows how SystemVerilog s interfaces can reduce the amount of code required to model the simple design shown in Figure 10-1 By encapsulating the signals that make up main_bus as an interface, the redundant declarations for these signals within each module are eliminated  270 SystemVerilog for Design Example 10-2: SystemVerilog module interconnections using interfaces... defined, and therefore default to a wire type In order to change the type for the ci input port, the port direction must be re-specified, even though it is the same direction as the preceding ports 9.8.3 SystemVerilog port declarations SystemVerilog simplifies the declaration of module ports in several ways Chapter 9: SystemVerilog Design Hierarchy 259 first port defaults First, SystemVerilog specifies... design blocks Figure 10-1 shows the block diagram for this simple design, and example 10-1 lists the Verilog source code for the module declarations involved Figure 10-1: Block diagram of a simple design Internal Memory Instruction Fetch Master Processor main_bus Test Generator Slave Processor Example 10-1: Verilog module interconnections for a simple design /********************** Top-level Netlist... between modules If, for example, three modules read and write from a shared memory device, then the read and write control logic must be duplicated in each of these modules module ports Yet another disadvantage of using module ports to connect the inhibit abstract blocks of a design together is that detailed interconnections for the top-down design design must be determined very early in the design cycle... of a design that maps directly to the physical connections that will be in the actual hardware For large designs, however, using module ports to connect blocks of a design together can become tedious and redundant Consider the following example that connects five blocks of a design together using a rudimentary bus architecture called main_bus, plus some additional connections between some of the design. .. specified for all but the a and b input ports These two ports will automatically infer the default type The optional vector size is specified for the data, result, a, and b ports; but not for the co and ci ports The unsized ports will default to the default size of their respective types, which are both 1 bit wide The vector sizes for result and co are different In order to change the size declaration for. .. unions are unpacked, the connections must match exactly on each side of the port 254 SystemVerilog for Design For unpacked arrays, an exact match on each side of the port is when there are the same number of dimensions in the array, each dimension is the same size, and each element of the array is the same size For unpacked structures and unions, an exact match on each side of the port means that... This is counter to the top-down design paradigm, where models are first written at an abstract level without extensive design detail At an abstract level, an interconnecting bus should not require defining each and every signal that makes up the bus Indeed, very early in the design specification, all that might be known is that the blocks of the design will share certain information In the block diagram... represented as a single connection Using Verilog’s module ports to connect the design blocks together, however, does not allow modeling at that same level of abstraction Before any block of the design can be modeled, the bus must first be broken down to individual signals 10.1.2 Advantages of SystemVerilog interfaces an interface is SystemVerilog adds a powerful new port type to Verilog, called an an abstract... could have come from any of the modules that share the variable 9 .7. 2 Synthesis guidelines NOTE Passing references through ports is not synthesizable Chapter 9: SystemVerilog Design Hierarchy 2 57 Passing references to variables through module ports is not synthesizable It is recommended that the use of ref ports should be reserved for abstract modeling levels where synthesis is not a consideration . name Chapter 9: SystemVerilog Design Hierarchy 243 Example 9-5: Simple netlist using SystemVerilog s .* port connections module miniPIC ( inout wire [7: 0] port_a_pins, inout wire [7: 0] port_b_pins, inout. maintain. Example 9-4: Simple netlist using SystemVerilog s .name port connections module miniPIC ( inout wire [7: 0] port_a_pins, inout wire [7: 0] port_b_pins, inout wire [7: 0] port_c_pins, input wire clk, input. ( .y(data_bus), .carry_out(carry), .zero_out(zero), .a(alu_a), 244 SystemVerilog for Design .b(alu_b), .opcode(alu_opcode), .carry_in(status_reg[0]) ); glue_logic glue ( .* ); endmodule 9.5 Net aliasing SystemVerilog adds an alias