MEMORY, MICROPROCESSOR, and ASIC phần 1 pps

[...]... References 12 9 13 9 14 9 15 12 1 12–2 12 –4 12 –6 12 –7 12 –9 12 10 12 11 12 14 12 –22 12 –23 12 –24 12 –24 12 –25 12 –26 12 –26 12 –27 Logic Synthesis for Field Programmable Gate Array (FPGA) Technology John W Lockwood 13 .1 Introduction 13 .2 FPGA Structures 13 .3 Logic Synthesis 13 .4 Look-up Table (LUT) Synthesis 13 1 13–2 13 –4 13 –6 xiii 13 .5 Chortle 13 .6 Two-Step Approaches 13 .7 Conclusion References 14 Testability... 11 1 11 1 11 2 11 14 11 15 11 19 11 – 21 ASIC Design Sumit Gupta and Rajesh K.Gupta 12 .1 Introduction 12 .2 Design Styles 12 .3 Steps in the Design Flow 12 .4 Hierarchical Design 12 .5 Design Representation and Abstraction Levels 12 .6 System Specification 12 .7 Specification Simulation and Verification 12 .8 Architectural Design 12 .9 Logic Synthesis 12 .10 Physical Design 12 .11 I/O Architecture and Pad Design 12 .12 ... Design 12 .12 Tests after Manufacturing 12 .13 High-Performance ASIC Design 12 .14 Low Power Issues 12 .15 Reuse of Semiconductor Blocks 12 .16 Conclusion References 13 10 1 10–4 10 –7 10 10 10 –27 Architecture Daniel A.Connors and Wen-mei W.Hwu 11 .1 Introduction 11 .2 Types of Microprocessors 11 .3 Major Components of a Microprocessor 11 .4 Instruction Set Architecture 11 .5 Instruction-Level Parallelism 11 .6 Industry... Concepts and DFT Nick Kanopoulos 14 .1 Introduction: Basic Concepts 14 .2 Design for Testability References 15 15 1 15–8 15 14 CAD Tools for BIST/DFT and Delay Faults Spyros Tragoudas 16 .1 Introduction 16 .2 CAD for Stuck-At Faults 16 .3 CAD for Path Delays References Index xiv 14 1 14–3 14 –5 ATPG and BIST Dimitri Kagaris 15 .1 Automatic Test Pattern Generation 15 .2 Built-In Self-Test References 16 13 –7 13 12 13 16 ... 13 12 13 16 13 16 16 1 16 1 16 14 16 –20 I 1 1 System Timing 1. 1 1. 2 Introduction Synchronous VLSI Systems 1- 1 1- 3 General Overview • Advantages and Drawbacks of Synchronous Systems 1. 3 Synchronous Timing and Clock Distribution Networks 1- 5 Background • Definitions and Notation • Clock Scheduling • Structure of the Clock Distribution Network 1. 4 University of Pittsburgh University of Rochester 1- 13 Common... Hsinchu,Taiwan CONTENTS 1 System Timing Ivan S.Kourtev and Eby G.Friedman 1. 1 Introduction 1. 2 Synchronous VLSI Systems 1. 3 Synchronous Timing and Clock Distribution Networks 1. 4 Timing Properties of Synchronous Storage Elements 1. 5 A Final Note 1. 6 Glossary of Terms References 2 ROM/PROM/EPROM Jen-Sheng Hwang 2 .1 Introduction 2.2 ROM 2.3 PROM References 3 1- 1 1- 3 1- 5 1- 13 1- 27 1- 27 1- 29 2 -1 2 -1 2-4 2-9 SRAM... 8 -1 8-2 8 -16 8-24 Introduction Design Verification Environment Random and Biased-Random Instruction Generation Correctness Checking Coverage Metrics Smart Simulation Wide Simulation 9 -1 9-3 9-5 9-6 9-8 9 -10 9 -12 9.8 Emulation 9.9 Conclusion References 10 Microprocessor Layout Method Tanay Karnik 10 .1 Introduction 10 .2 Layout Problem Description 10 .3 Manufacturing 10 .4 Chip Planning References 11 11 1. .. defined in Definition 1. 3 obeys the antisymmetric property (1. 2) FIGURE 1. 3 Graphs G and its underlying graph Gu of the graph N=5 registers Memory, Microprocessor, and ASIC 1- 8 The clock skew Tskew (i,j) as defined in Definition 1. 3 is a component in the timing constraints of a local data path (see inequalities 1. 19, 1. 24, 1. 34, 1. 35, and 1. 40).Therefore, clock skew is defined and is only of practical... Definition 1. 4, the timing constraints of a local data path Ri Rf with flip-flops (Eqs 1. 19 and 1. 24) become (1. 5) (1. 6) For a local data path Ri Rf consisting of the flip-flows Ri and Rf, the setup and hold time violations are avoided if Eqs 1. 5 and 1. 6, respectively, are satisfied The clock skew Tskew(i, f) for a local data path Ri Rf can be either positive or negative, as illustrated in Figs 1. 15 and 1. 16,... occur at times (1. 13) and the trailing edges of c(t) occur at times (1. 14) In practice, however, it is possible for the edges of a clock signal to fluctuate in time, that is, not to occur precisely at the times described by Eqs 1. 13 and 1. 14 for the leading and trailing edges, respectively.This FIGURE 1. 12 A typical clock signal System Timing 1- 19 phenomenon is known as clock jitter and may be due . Microprocessor 11 –2 11 .4 Instruction Set Architecture 11 14 11 .5 Instruction-Level Parallelism 11 15 11 .6 Industry Trends 11 19 References 11 – 21 12 ASIC Design Sumit Gupta and Rajesh K.Gupta 12 .1 Introduction. Description 10 –4 10 .3 Manufacturing 10 –7 10 .4 Chip Planning 10 10 References 10 –27 11 Architecture Daniel A.Connors and Wen-mei W.Hwu 11 .1 Introduction 11 1 11. 2 Types of Microprocessors 11 1 11. 3 Major. Simulation and Verification 12 10 12 .8 Architectural Design 12 11 12 .9 Logic Synthesis 12 14 12 .10 Physical Design 12 –22 12 .11 I/O Architecture and Pad Design 12 –23 12 .12 Tests after Manufacturing 12 –24 12 .13