PIC18FXX2 DS39564C-page 270 © 2006 Microchip Technology Inc. 22.3.2 TIMING CONDITIONS The temperature and voltages specified in Table 22-3 apply to all timing specifications unless otherwise noted. Figure 22-4 specifies the load conditions for the timing specifications. TABLE 22-3: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC FIGURE 22-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS AC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ T A ≤ +85°C for industrial -40°C ≤ T A ≤ +125°C for extended Operating voltage V DD range as described in DC spec Section 22.1 and Section 22.2. LC parts operate for industrial temperatures only. VDD/2 CL RL Pin Pin V SS VSS CL RL =464Ω C L = 50 pF for all pins except OSC2/CLKO and including D and E outputs as ports Load condition 1 Load condition 2 © 2006 Microchip Technology Inc. DS39564C-page 271 PIC18FXX2 22.3.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 22-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) TABLE 22-4: EXTERNAL CLOCK TIMING REQUIREMENTS OSC1 CLKO Q4 Q1 Q2 Q3 Q4 Q1 1 2 3 3 4 4 Param. No. Symbol Characteristic Min Max Units Conditions 1A F OSC External CLKI Frequency (1) DC 40 MHz EC, ECIO, -40°C to +85°C Oscillator Frequency (1) DC 25 MHz EC, ECIO, +85°C to +125°C DC 4 MHz RC osc 0.1 4 MHz XT osc 4 25 MHz HS osc 4 10 MHz HS + PLL osc, -40°C to +85°C 4 6.25 MHz HS + PLL osc, +85°C to +125°C 5 200 kHz LP Osc mode 1 T OSC External CLKI Period (1) 25 — ns EC, ECIO, -40°C to +85°C Oscillator Period (1) 40 — ns EC, ECIO, +85°C to +125°C 250 — ns RC osc 250 10,000 ns XT osc 40 250 ns HS osc 100 250 ns HS + PLL osc, -40°C to +85°C 160 250 ns HS + PLL osc, +85°C to +125°C 25 — μsLP osc 2 T CY Instruction Cycle Time (1) 100 — ns TCY = 4/FOSC, -40°C to +85°C 160 — ns TCY = 4/FOSC, +85°C to +125°C 3 TosL, To sH External Clock in (OSC1) High or Low Time 30 — ns XT osc 2.5 — μsLP osc 10 — ns HS osc 4TosR, To sF External Clock in (OSC1) Rise or Fall Time — 20 ns XT osc — 50 ns LP osc —7.5nsHS osc Note 1: Instruction cycle period (T CY) equals four times the input oscillator time-base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. PIC18FXX2 DS39564C-page 272 © 2006 Microchip Technology Inc. TABLE 22-5: PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2 TO 5.5V) FIGURE 22-6: CLKO AND I/O TIMING Param No. Sym Characteristic Min Typ† Max Units Conditions —F OSC Oscillator Frequency Range 4 — 10 MHz HS mode only —F SYS On-chip VCO System Frequency 16 — 40 MHz HS mode only —t rc PLL Start-up Time (Lock Time) — — 2 ms — ΔCLK CLKO Stability (Jitter) -2 — +2 % † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note: Refer to Figure 22-4 for load conditions. OSC1 CLKO I/O Pin (input) I/O Pin (output) Q4 Q1 Q2 Q3 10 13 14 17 20, 21 19 18 15 11 12 16 Old Value New Value © 2006 Microchip Technology Inc. DS39564C-page 273 PIC18FXX2 TABLE 22-6: CLKO AND I/O TIMING REQUIREMENTS FIGURE 22-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING Param. No. Symbol Characteristic Min Typ Max Units Conditions 10 TosH2ckL OSC1↑ to CLKO↓ —75200ns(Note 1) 11 TosH2ckH OSC1↑ to CLKO↑ —75200ns(Note 1) 12 TckR CLKO rise time — 35 100 ns (Note 1) 13 TckF CLKO fall time — 35 100 ns (Note 1) 14 TckL2ioV CLKO↓ to Port out valid — — 0.5 T CY + 20 ns (Note 1) 15 TioV2ckH Port in valid before CLKO ↑ 0.25 T CY + 25 — — ns (Note 1) 16 TckH2ioI Port in hold after CLKO ↑ 0——ns(Note 1) 17 TosH2ioV OSC1↑ (Q1 cycle) to Port out valid — 50 150 ns 18 TosH2ioI OSC1↑ (Q2 cycle) to Port input invalid (I/O in hold time) PIC18FXXX 100 — — ns 18A PIC18LFXXX 200 — — ns 19 TioV2osH Port input valid to OSC1↑ (I/O in setup time) 0 — — ns 20 TioR Port output rise time PIC18FXXX — 10 25 ns 20A PIC18LFXXX — — 60 ns V DD = 2V 21 TioF Port output fall time PIC18FXXX — 10 25 ns 21A PIC18LFXXX — — 60 ns V DD = 2V 22†† TINP INT pin high or low time TCY ——ns 23†† T RBP RB7:RB4 change INT high or low time TCY ——ns 24†† TRCP RC7:RC4 change INT high or low time 20 ns †† These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKO output is 4 x T OSC. VDD MCLR Internal POR PWRT Time-out OSC Time-out Internal Reset Watchdog Timer Reset 33 32 30 31 34 I/O Pins 34 Note: Refer to Figure 22-4 for load conditions. PIC18FXX2 DS39564C-page 274 © 2006 Microchip Technology Inc. FIGURE 22-8: BROWN-OUT RESET TIMING TABLE 22-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS VDD BVDD 35 VBGAP = 1.2V V IRVST Enable Internal Reference Voltage Internal Reference Voltage stable 36 Typical Param. No. Symbol Characteristic Min Typ Max Units Conditions 30 TmcL MCLR Pulse Width (low) 2 — — μs 31 TWDT Watchdog Timer Time-out Period (No Postscaler) 71833ms 32 T OST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC —TOSC = OSC1 period 33 TPWRT Power up Timer Period 28 72 132 ms 34 T IOZ I/O Hi-impedance from MCLR Low or Watchdog Timer Reset —2—μs 35 T BOR Brown-out Reset Pulse Width 200 — — μsVDD ≤ BVDD (see D005) 36 T IVRST Time for Internal Reference Voltage to become stable —20500μs 37 T LVD Low Voltage Detect Pulse Width 200 — — μsVDD ≤ VLVD (see D420) © 2006 Microchip Technology Inc. DS39564C-page 275 PIC18FXX2 FIGURE 22-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS TABLE 22-8: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Note: Refer to Figure 22-4 for load conditions. 46 47 45 48 41 42 40 T0CKI T1OSO/T1CKI TMR0 or TMR1 Param No. Symbol Characteristic Min Max Units Conditions 40 Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — ns With Prescaler 10 — ns 41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5T CY + 20 — ns With Prescaler 10 — ns 42 Tt0P T0CKI Period No Prescaler T CY + 10 — ns With Prescaler Greater of: 20 n S or TCY + 40 N — ns N = prescale value (1, 2, 4, , 256) 45 Tt1H T1CKI High Time Synchronous, no prescaler 0.5T CY + 20 — ns Synchronous, with prescaler PIC18FXXX 10 — ns PIC18LFXXX 25 — ns Asynchronous PIC18FXXX 30 — ns PIC18LFXXX 50 — ns 46 Tt1L T1CKI Low Time Synchronous, no prescaler 0.5T CY + 5 — ns Synchronous, with prescaler PIC18FXXX 10 — ns PIC18LFXXX 25 — ns Asynchronous PIC18FXXX 30 — ns PIC18LFXXX 50 — ns 47 Tt1P T1CKI input period Synchronous Greater of: 20 n S or TCY + 40 N — ns N = prescale value (1, 2, 4, 8) Asynchronous 60 — ns Ft1 T1CKI oscillator input frequency range DC 50 kHz 48 Tcke2tmrI Delay from external T1CKI clock edge to timer increment 2 T OSC 7 TOSC — PIC18FXX2 DS39564C-page 276 © 2006 Microchip Technology Inc. FIGURE 22-10: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) TABLE 22-9: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Note: Refer to Figure 22-4 for load conditions. CCPx (Capture Mode) 50 51 52 CCPx 53 54 (Compare or PWM Mode) Param. No. Symbol Characteristic Min Max Units Conditions 50 TccL CCPx input low time No Prescaler 0.5 T CY + 20 — ns With Prescaler PIC18FXXX 10 — ns PIC18LFXXX 20 — ns 51 TccH CCPx input high time No Prescaler 0.5 T CY + 20 — ns With Prescaler PIC18FXXX 10 — ns PIC18LFXXX 20 — ns 52 TccP CCPx input period 3 T CY + 40 N —nsN = prescale value (1,4 or 16) 53 TccR CCPx output fall time PIC18FXXX — 25 ns PIC18LFXXX — 60 ns VDD = 2V 54 TccF CCPx output fall time PIC18FXXX — 25 ns PIC18LFXXX — 60 ns V DD = 2V © 2006 Microchip Technology Inc. DS39564C-page 277 PIC18FXX2 FIGURE 22-11: PARALLEL SLAVE PORT TIMING (PIC18F4X2) TABLE 22-10: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4X2) Note: Refer to Figure 22-4 for load conditions. RE2/CS RE0/RD RE1/WR RD7:RD0 62 63 64 65 Param. No. Symbol Characteristic Min Max Units Conditions 62 TdtV2wrH Data in valid before WR ↑ or CS↑ (setup time) 20 25 — — ns ns Extended Temp. Range 63 TwrH2dtI WR↑ or CS↑ to data–in invalid (hold time) PIC18FXXX 20 — ns PIC18LFXXX 35 — ns V DD = 2V 64 TrdL2dtV RD ↓ and CS↓ to data–out valid — — 80 90 ns ns Extended Temp. Range 65 TrdH2dtI RD ↑ or CS↓ to data–out invalid 10 30 ns 66 TibfINH Inhibit of the IBF flag bit being cleared from WR ↑ or CS↑ —3 T CY PIC18FXX2 DS39564C-page 278 © 2006 Microchip Technology Inc. FIGURE 22-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) TABLE 22-11: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param. No. Symbol Characteristic Min Max Units Conditions 70 TssL2scH, TssL2scL SS ↓ to SCK↓ or SCK↑ input TCY —ns 71 TscH SCK input high time (Slave mode) Continuous 1.25 T CY + 30 — ns 71A Single Byte 40 — ns (Note 1) 72 TscL SCK input low time (Slave mode) Continuous 1.25 T CY + 30 — ns 72A Single Byte 40 — ns (Note 1) 73 TdiV2scH, TdiV2scL Setup time of SDI data input to SCK edge 100 — ns 73A T B2B Last clock edge of Byte1 to the 1st clock edge of Byte2 1.5 TCY + 40 — ns (Note 2) 74 TscH2diL, TscL2diL Hold time of SDI data input to SCK edge 100 — ns 75 TdoR SDO data output rise time PIC18FXXX — 25 ns PIC18LFXXX — 60 ns V DD = 2V 76 TdoF SDO data output fall time PIC18FXXX — 25 ns PIC18LFXXX — 60 ns V DD = 2V 78 TscR SCK output rise time (Master mode) PIC18FXXX — 25 ns PIC18LFXXX — 60 ns V DD = 2V 79 TscF SCK output fall time (Master mode) PIC18FXXX — 25 ns PIC18LFXXX — 60 ns V DD = 2V 80 TscH2doV, TscL2doV SDO data output valid after SCK edge PIC18FXXX — 50 ns PIC18LFXXX — 150 ns V DD = 2V Note 1: Requires the use of Parameter # 73A. 2: Only if Parameter # 71A and # 72A are used. SS SCK (CKP = 0) SCK (CKP = 1) SDO SDI 70 71 72 73 74 75, 76 78 79 80 79 78 MSb LSb bit6 - - - - - -1 MSb In LSb In bit6 - - - -1 Note: Refer to Figure 22-4 for load conditions. © 2006 Microchip Technology Inc. DS39564C-page 279 PIC18FXX2 FIGURE 22-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) TABLE 22-12: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No. Symbol Characteristic Min Max Units Conditions 71 TscH SCK input high time (Slave mode) Continuous 1.25 T CY + 30 — ns 71A Single Byte 40 — ns (Note 1) 72 TscL SCK input low time (Slave mode) Continuous 1.25 T CY + 30 — ns 72A Single Byte 40 — ns (Note 1) 73 TdiV2scH, TdiV2scL Setup time of SDI data input to SCK edge 100 — ns 73A T B2B Last clock edge of Byte1 to the 1st clock edge of Byte2 1.5 TCY + 40 — ns (Note 2) 74 TscH2diL, TscL2diL Hold time of SDI data input to SCK edge 100 — ns 75 TdoR SDO data output rise time PIC18FXXX — 25 ns PIC18LFXXX — 60 ns V DD = 2V 76 TdoF SDO data output fall time PIC18FXXX — 25 ns PIC18LFXXX — 60 ns V DD = 2V 78 TscR SCK output rise time (Master mode) PIC18FXXX — 25 ns PIC18LFXXX — 60 ns V DD = 2V 79 TscF SCK output fall time (Master mode) PIC18FXXX — 25 ns PIC18LFXXX — 60 ns V DD = 2V 80 TscH2doV, TscL2doV SDO data output valid after SCK edge PIC18FXXX — 50 ns PIC18LFXXX — 150 ns VDD = 2V 81 TdoV2scH, TdoV2scL SDO data output setup to SCK edge TCY —ns Note 1: Requires the use of Parameter # 73A. 2: Only if Parameter # 71A and # 72A are used. SS SCK (CKP = 0) SCK (CKP = 1) SDO SDI 81 71 72 74 75, 76 78 80 MSb 79 73 MSb In bit6 - - - - - -1 LSb In bit6 - - - -1 LSb Note: Refer to Figure 22-4 for load conditions. [...]... 1 MHz mode(1) 93 2(TOSC)(BRG + 1) 400 kHz mode Setup time — 100 kHz mode TSU:STO STOP condition — 2(TOSC)(BRG + 1) 1 MHz mode(1) 92 2(TOSC)(BRG + 1) 1 MHz mode(1) Hold time 2(TOSC)(BRG + 1) Conditions — ns ns 2 Note 1: Maximum pin capacitance = 10 pF for all I C pins FIGURE 22- 19: MASTER SSP I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 91 107 92 SDA In 1 09 1 09 110 SDA Out Note: DS 395 64C-page 284... 100 kHz mode 4700 — Setup time 92 100 kHz mode 400 kHz mode Hold time THD:STA START condition Setup time 91 TSU:STA Characteristic 400 kHz mode 600 — 100 kHz mode 4000 — 400 kHz mode 600 — THD:STO STOP condition Hold time FIGURE 22-17: ns ns I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 1 09 1 09 SDA Out Note: Refer to Figure 22-4 for load conditions DS 395 64C-page 282 © 2006 Microchip... Technology Inc DS 395 64C-page 281 PIC18FXX2 FIGURE 22-16: I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA STOP Condition START Condition Note: Refer to Figure 22-4 for load conditions TABLE 22-15: I2C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param Symbol No 90 Min Max Units Conditions ns Only relevant for Repeated START condition ns After this period, the first clock pulse is generated 93 TSU:STO 4700... the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released © 2006 Microchip Technology Inc DS 395 64C-page 283 PIC18FXX2 FIGURE 22-18: MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS SCL 93 91 90 92 SDA STOP Condition START Condition Note: Refer to Figure... 0.1 CB 300 ns VDD ≥ 4.2V 90 TSU:STA START condition setup time 100 kHz mode 4.7 — μs 400 kHz mode 0.6 — μs Only relevant for Repeated START condition 91 THD:STA START condition hold 100 kHz mode time 400 kHz mode 4.0 — μs μs 106 THD:DAT Data input hold time 0.6 — 100 kHz mode 0 — ns 400 kHz mode 0 0 .9 μs ns After this period, the first clock pulse is generated 107 TSU:DAT Data input setup time 100... 132 A/D DATA ADRES 9 8 7 2 1 OLD _DATA 0 NEW _DATA TCY ADIF GO SAMPLE DONE SAMPLING STOPPED Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts This allows the SLEEP instruction to be executed 2: This is a minimal RC delay (typically 100 nS), which also disconnects the holding capacitor from the analog input © 2006 Microchip Technology Inc DS 395 64C-page... 3.5 4.0 FOSC (MHz) © 2006 Microchip Technology Inc DS 395 64C-page 291 PIC18FXX2 FIGURE 23-7: TYPICAL IDD vs FOSC OVER VDD (LP MODE) 100 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 90 80 5.5V 70 5.0V IDD (uA) 60 4.5V 50 4.0V 40 3.5V 3.0V 30 2.5V 20 2.0V 10 0 20 30 40 50 60 70 80 90 100 90 100 FOSC (kHz) FIGURE 23-8: MAXIMUM IDD vs FOSC OVER... ns VDD ≥ 4.2V 90 TSU:STA START condition 100 kHz mode setup time 400 kHz mode 2(TOSC)(BRG + 1) — ms 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms Only relevant for Repeated START condition THD:STA START condition 100 kHz mode hold time 400 kHz mode 2(TOSC)(BRG + 1) — ms 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 91 106 107 THD:DAT Data input hold time TSU:DAT Data input setup... (Note 2) 74 TscH2diL, TscL2diL Hold time of SDI data input to SCK edge 100 — ns 75 TdoR SDO data output rise time PIC18FXXX — 25 ns PIC18LFXXX — 60 ns 76 TdoF SDO data output fall time PIC18FXXX — 25 ns PIC18LFXXX — 60 ns 10 50 ns — 25 ns 72A 77 TssH2doZ SS↑ to SDO output hi-impedance 78 TscR SCK output rise time (Master mode) PIC18FXXX PIC18LFXXX — 60 ns 79 TscF SCK output fall time (Master mode) PIC18FXXX... TdiV2scH, TdiV2scL Setup time of SDI data input to SCK edge 72A 40 — ns 100 — ns 1.5 TCY + 40 — ns 100 — ns PIC18FXXX — 25 ns PIC18LFXXX — 60 ns PIC18FXXX — 25 ns PIC18LFXXX 73 Single Byte — 60 ns 73A TB 2 B Last clock edge of Byte1 to the first clock edge of Byte2 74 TscH2diL, TscL2diL Hold time of SDI data input to SCK edge 75 TdoR SDO data output rise time 76 TdoF SDO data output fall time (Note 1) 77 . load conditions. 90 91 92 100 101 103 106 107 1 09 1 09 110 102 SCL SDA In SDA Out © 2006 Microchip Technology Inc. DS 395 64C-page 285 PIC18FXX2 TABLE 22-18: MASTER SSP I 2 C BUS DATA REQUIREMENTS. BITS REQUIREMENTS FIGURE 22- 19: MASTER SSP I 2 C BUS DATA TIMING Note: Refer to Figure 22-4 for load conditions. 91 93 SCL SDA START Condition STOP Condition 90 92 Param. No. Symbol Characteristic. kHz mode 600 — 93 T HD:STO STOP condition 100 kHz mode 4000 — ns Hold time 400 kHz mode 600 — Note: Refer to Figure 22-4 for load conditions. 90 91 92 100 101 103 106 107 1 09 1 09 110 102 SCL SDA In SDA Out ©