Điện tử số - Phần 2 docx

Digital Electronics Digital Electronics Dr. Pham Ngoc Nam © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL 1/2 Acknowledgement Acknowledgement • The main part of the slides was adopted and modified from the original slides of Prof. Rudy Lauwereins, Vice president of IMEC, Leuven, Belgium with his permission. © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL Your instructor • Bộ môn kỹ thuật điện tử tin học  Office: C9-401  Email: pnnam-fet@mail.hut.edu.vn • Research:  FPGA, PSoC, hệ nhúng  Trí tuệ nhân tạo • Education:  K37 điện tử-ĐHBK Hà nội (1997)  Master về trí tuệ nhân tạo 1999, Đại học K.U. Leuven, vương quốc Bỉ  Đề tài: Nhận dạng chữ viết tay  Tiến sỹ kỹ thuật chuyên ngành điện tử-tin học, 9/ 2004, Đại học K.U. Leuven-IMEC, Vương Quốc Bỉ  Đề tài: quản lý chất lượng dịch vụ trong các ứng dụng đa phương tiện tiên tiến © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL 1/4 Course contents Course contents • Digital design • Combinatorial circuits: without status • Sequential circuits: with status • FSMD design: hardwired processors • Language based HW design: VHDL © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL 1/5 Course contents Course contents  Digital design • Combinatorial circuits: without status • Sequential circuits: with status • FSMD design: hardwired processors • Language based HW design: VHDL © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL 1/6 Contents of “Digital Design” Contents of “Digital Design” • Introduction to the course • Data representation • Boolean algebra • Logical gates © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL 1/7 Contents of “Digital Design” Contents of “Digital Design” • Introduction to the course  Course book  Goal  Exercises and laboratory sessions  Exam • Data representation • Boolean algebra • Logical gates © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL 1/8 Contents of “Digital Design” Contents of “Digital Design” • Introduction to the course  Course book  Goal  Exercises and laboratory sessions  Exam • Data representation • Boolean algebra • Logical gates © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL 1/9 Course books Course books • Mandatory:  “Principles of Digital Design”, Daniel D. Gajski, Prentice Hall, 1997, ISBN 0-13- 301144-5 • References:  Douglas L. Perry, VHDL: Programming by Examples, McGraw-Hill, fourth Edition, 2002.  “Logic and Computer Design Fundamentals”, M. Morris Mano & Charles R. Kime, Prentice Hall, 2nd edition, 2000, ISBN 0-13-016176-4  TS. Nguy n Nam Quân :ễ “Toán logic và K ỹ thu t s ”, Nhà xu t b n khoa h c và k thu t, ậ ố ấ ả ọ ỹ ậ 2006 © R.Lauwereins Imec 2001 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL 1/10 Contents of “Digital Design” Contents of “Digital Design” • Introduction to the course  Course book  Goal  Exercises and laboratory sessions  Exam • Data representation • Boolean algebra • Logical gates [...]... 1011.01 12=  1•8+0•4+1 2+ 1•1+0•0.5+1•0 .25 +1•0. 125  1 23 +0 22 +1 21 +1 20 +0• 2- 1 +1• 2- 2 +1• 2- 3  r = radix (r = 2) , d = digit (0 ≤ d ≤ 1), m = #digits before radix point (binary point), n = #digits after radix point B= m −1 ∑d i=− n i 2 i © R.Lauwereins Imec 20 01 Digital design Combinatorial circuits Sequential circuits FSMD design VHDL 1 /20 Octal • 7654. 328 =  7•5 12+ 6•64+5•8+4•1+3•0. 125 +2 0.015 625  7•83+6• 82+ 5•81+4•80+3• 8-1 +2 8 -2 ... we obtain -D? • D* = rm - D ⇒ D* + D = rm = 0 when we retain only the m least significant digits ⇒ D* = -D • eg D=001 12 ⇒ D*=110 02+ 000 12= 110 12 D+D*=001 12+ 110 12= 1000 02= 24=0 when we retain only the m least significant bits; we may hence use D*=110 12 for the binary representation of -D =-3 10 • What is the negation of D=000 02? D*=111 12+ 000 12= 1000 02= 000 02 There is only 1 notation for ‘zero’ • A 2- complement... D*=111 12+ 000 12= 1000 02= 000 02 There is only 1 notation for ‘zero’ • A 2- complement integer with n bits lies between -( 2n-1) and +(2n- 1-1 ) © R.Lauwereins Imec 20 01 Two’s complement notation Decimal Digital design Combinatorial circuits Sequential circuits FSMD design VHDL 1/33 2- complement Sign-magnitude -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111... Sequential circuits FSMD design VHDL Sign-Magnitude representation • Each number consists of two parts : sign and magnitude • Decimal example: + 123 10 (by convention also ‘ 123 ’) and -1 23 10 • Binary: sign represented by MSB; ‘0’ = positive, ‘1’ = negative • Binary example: 0110 02 = + 121 0 en 1110 02 = -1 21 0 • A sign-magnitude integer with n bits lies between -( 2n- 1-1 ) and +(2n- 1-1 ) with two representations for... The 10-complement of 123 10 is 103 - 123 10 = 87710 • eg The 2- complement of 110 12 is 24 - 1310 = 310 = 001 12 • Call D’ the digit complement, then D*=D’+1 (proof in book); this offers us an easier way of determining the two’s complement: • eg The 2- complement of 110 12 is 001 02 + 000 12 = 001 12 © R.Lauwereins Imec 20 01 Digital design Combinatorial circuits Sequential circuits FSMD design VHDL 1/ 32 Two’s... 1 /28 © R.Lauwereins Imec 20 01 Sign-Magnitude addition and subtraction Start subtraction Digital design Combinatorial circuits s2=s 2 Sequential circuits no no FSMD design VHDL no mr=0 sr=0 m1>m2 s1=s2 yes yes m1 . R.Lauwereins Imec 20 01 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL 1/19 Binary Binary • 1011.011 2 =  1•8+0•4+1 2+ 1•1+0•0.5+1•0 .25 +1•0. 125  1 2 3 +0 2 2 +1 2 1 +1 2 0 +0 2 -1 +1 2 -2 +1 2 -3  r. 20 01 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL 1 /20 Octal Octal • 7654. 32 8 =  7•5 12+ 6•64+5•8+4•1+3•0. 125 +2 0.015 625  7•8 3 +6•8 2 +5•8 1 +4•8 0 +3•8 -1 +2 8 -2  r = radix. 20 01 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL 1/19 Binary Binary • 1011.011 2 =  1•8+0•4+1 2+ 1•1+0•0.5+1•0 .25 +1•0. 125  1 2 3 +0 2 2 +1 2 1 +1 2 0 +0 2 -1 +1 2 -2 +1 2 -3  r = radix (r = 2) , d = digit (0 ≤ d ≤ 1), m = #digits before radix point (binary point), n = #digits after radix point ∑ − −= •= 1 2 m ni i i dB © R.Lauwereins Imec 20 01 Digital design Combina- torial circuits Sequential circuits FSMD design VHDL 1 /20 Octal Octal • 7654. 32 8 =  7•5 12+ 6•64+5•8+4•1+3•0. 125 +2 0.015 625  7•8 3 +6•8 2 +5•8 1 +4•8 0 +3•8 -1 +2 8 -2  r