The BIOS Companion doc

THÔNG TIN TÀI LIỆU

Cấu trúc

The BIOS
- BIOS Data Area
- What Happens When You Switch On
- How old is my BIOS?
- Identifying Your BIOS
  - Acer ID Strings
  - ALR (Gateway) ID Strings
  - AMI ID Strings
  - AOpen ID Strings
  - Award ID Strings
  - BIOStar ID Strings
  - DTK ID Strings
  - Gateway ID Strings
  - Intel ID Strings
  - Micronics ID Strings
  - MR BIOS ID Strings
  - Packard Bell ID Strings
  - Phoenix ID Strings
  - Sony Vaio ID Strings
  - Tandon ID Strings
  - Tyan ID Strings
  - Zeos ID Strings
  - Using The Registry
- What's in my machine (using debug)?
  - Testing Your Ports
  - Identifying Your Graphics Card
  - Clearing The Master Boot Record
- Where Can I Get A New BIOS?
- Flash BIOS Upgrades
- Recovering A Corrupt BIOS
- DMI
- Facilities Provided
  - The Bootstrap Loader
  - The Power On Self Test
  - CMOS settings
  - Utilities
The Motherboard
- Bits and Bytes
- The Central Processor
  - Slots and Sockets
  - The 8088
  - The 80286
  - The 80386
  - The 80486
  - Clock Doubling
  - Overclocking
  - The Pentium
  - Centrino
  - Celeron
  - Cyrix Instead
  - IBM
  - AMD
  - IDT
  - Transmeta
  - MMX
  - Summing up
- Chip Reference Chart
Memory
- Static RAM
- Dynamic RAM
- Wait states
- Shadow RAM
- Random Access Memory
  - Base (or Conventional) Memory
  - Upper Memory
  - Extended Memory
  - High Memory
  - Expanded Memory
  - Virtual Memory
  - Shared Memory
- CMOS Memory Map
- Numbers On Chips
  - SIMMs
  - DIMMs
  - SIPPs
Bus Types
- ISA
- EISA
- Micro Channel Architecture
- Local Bus
  - VL-BUS
  - PCI
- PCMCIA
- USB
- FireWire
Expansion Cards
- Direct Memory Access (DMA)
- Base Memory Address
- Base I/O Address
- Interrupt Setting
Performance
Open Sesame
- Setup Programs
  - Compaq
  - Epson
  - GRiD
  - NEC
  - Panasonic
  - Samsung
Softmenu Setup
- Brand Name
- Frequency
- Cache Size
- CPU Operating Speed
- User Define: Warning
- Ext. Clock (CPU/AGP/PCI)
- Multiplier Factor
- Estimated new CPU clock
- DRAM Ratio (CPU:DRAM)
- AGP Ratio (CPU:AGP:PCI)
- Fixed AGP/PCI Frequency
- CPU Power Supply
- CPU Core Voltage
- DDR SDRAM Voltage
- AGP Voltage
Standard CMOS Setup
- Settings
  - Date and Time
  - Daylight Saving
  - Hard Disk (C and D)
  - Primary Master/Primary Slave, etc.
  - Floppy Disks
  - Removable Device (Legacy Floppy)
  - Keyboard Installed
  - Video Display
  - Halt on
  - Floppy 3 Mode Support
  - Full Screen Logo Show
  - Full Screen Logo
  - Boot Sequence
  - Boot Other Device
  - Try Other Boot Device
  - Boot Sequence EXT means
  - First Boot Device
  - Second Boot Device
  - Third Boot Device
  - IDE Hard Drive
  - ATAPI CD ROM
  - Quick Boot
  - Other Boot Device Select
Advanced CMOS Setup
- Settings
  - Typematic Rate Programming
  - Above 1 Mb Memory Test
  - Memory Parity Error Check
  - Memory Priming
  - Memory Test Tick Sound
  - Hit <Del> Message Display
  - Hard Disk Type 47 Data Area
  - Scratch RAM Option
  - Wait For <F1> If Any Error
  - System Boot Up <Num Lock>
  - Boot Up NumLock Status
  - Numeric co-processor
  - Weitek Processor
  - System Boot Up Sequence
  - Boot Up Sequence
  - Boot Sequence
  - Permit Boot from...
  - Drive C: Assignment
  - Floppy Drive Seek At Boot
  - Boot Up Floppy Seek
  - Boot E000 Adapters
  - HDD Sequence SCSI/IDE First
  - Quick Power On Self Test
  - Swap Floppy Drive
  - Floppy Disk Access Control
  - Legacy Diskette A:
  - Legacy Diskette B:
  - System Boot Up CPU Speed
  - Boot Up System Speed
  - Cold Boot Delay
  - System Warmup Delay
  - Delay IDE Initial (sec)
  - External Cache Memory
  - Cache memory bad, do not enable
  - Internal Cache Memory
  - Fast Gate A20 Option
  - Gate A20 Option
  - Low A20# Select
  - Turbo Switch Function
  - Gate A20 Emulation
  - Gateway A20 Option
  - Fast Reset Emulation
  - Fast Reset Latency
  - Keyboard Emulation
  - KBC Input Clock
  - Keyboard Controller Clock
  - Video ROM Shadow C000, 32K
  - Video BIOS Shadow
  - Fast Video BIOS
  - Adapter ROM Shadow C800, 16K
  - System ROM Shadow
  - Shadowing Address Ranges (xxxxx-xxxxx Shadow)
  - C8000-CFFFF Shadow/D0000-DFFFF Shadow
  - C8000-CFFFF Shadow/E0000-EFFFF Shadow
  - CPU Internal Core Speed
  - CPU Host Bust Frequency
  - CPU Core: Bus Freq. Multiple
  - CPU Core Voltage
  - CPU Clock Failed Reset
  - Password Checking Option
  - Security Option
  - Supervisor/User Password
  - Network Password Checking
  - Boot Sector Virus Protection
  - CIH Buster Protection
  - Anti-Virus Protection
  - Virus Warning
  - ChipAway Virus On Guard
  - Small Logo (EPA) Show
  - Report no FDD for Win 95
  - ATA 66/100 IDE Cable MSG
  - Turbo Frequency
Advanced Chipset Setup
- Automatic Configuration
- Refresh
  - SDRAM PH limit
  - SDRAM Page Hit Limit
  - SDRAM Idle Limit
  - SDRAM Idle Cycle Limit
  - Hidden Refresh
  - Hidden Refresh Control
  - DRAM Refresh Mode
  - AT Style Refresh
  - Concurrent Refresh
  - Decoupled Refresh Option
  - Burst Refresh
  - Refresh When CPU Hold
  - DRAM Burst of 4 Refresh
  - Fast DRAM Refresh
  - Divide for Refresh
  - Hi-speed Refresh
  - Slow Refresh
  - Slow Refresh Enable
  - DRAM Slow Refresh
  - Refresh Interval (15.6 µsec)
  - Refresh Mode Select
  - Staggered Refresh
  - DRAM Refresh Period
  - Refresh RAS active time
  - Slow Memory Refresh Divider
  - Refresh Value
  - Refresh RAS# Assertion
  - DRAM RAS Only Refresh
  - DRAM Refresh Queue
  - DRAM Refresh Method
  - DRAM Refresh Rate
  - DRAM Refresh Stagger By
  - DRAM Read Burst (EDO/FPM)
  - Refresh Cycle Time (187.2 us)
  - PLT Enable
- Data Bus
  - AT Cycle Wait State
  - Extra AT Cycle Wait State
  - 16-bit Memory, I/O Wait State
  - 8-bit Memory, I/O Wait State
  - Command Delay
  - AT Bus I/O Command Delay
  - AT Bus 16 Bit Command Delay
  - AT Bus Address Hold Time
  - AT Bus n Bit Wait States
  - 16-bit I/O Recovery Time
  - 8-bit I/O Recovery Time
  - ISA I/O Recovery
  - ISA I/O wait state
  - ISA memory wait state
  - ISA write insert w/s
  - W/S in 32-bit ISA
  - 16 Bit ISA I/O Command WS
  - 16 Bit ISA Mem Command WS
  - AT Bus Clock Source
  - AT Clock
  - AT Bus Clock
  - AT Clock Option
  - ATCLK Stretch
  - Synchronous AT Clock
  - ISA Bus Speed
  - Bus Clock Selection
  - Bus Mode
  - Fast AT Cycle
  - ISA IRQ
  - Master Mode Byte Swap
  - DMA clock source
  - DMA Clock
  - DMA Wait States
  - DMA Command Width
  - MEMR# Signal
  - MEMW# Signal
  - DMA Address/Data Hold Time
  - DMA MEMR Assertion Delay
  - I/O Recovery Time Delay
  - I/O Recovery Select
  - AT Bus Precharge Wait State
  - I/O Cmd Recovery Control
  - Single ALE Enable
  - ALE During Bus Conversion
  - E0000 ROM belongs to AT BUS
  - Internal MUX Clock Source
  - Fast Decode Enable
  - Fast CPU Reset
  - Extended I/O Decode
  - Local Bus Ready
  - Local Bus Ready Delay 1 Wait
  - Local Bus Latch Timing
  - Latch Local Bus
  - ADS Delay
  - IDE Multi Block Mode
  - IDE Block Mode Transfer
  - Multi-Sector Transfers
  - IDE Multiple Sector Mode
  - Multiple Sector Setting
  - IDE (HDD) Block Mode
  - IDE 32-bit Transfer
  - CPU ADS# Delay 1T or Not
  - Fast Programmed I/O Mode
  - IDE Primary Master PIO
  - IDE Primary/Secondary Master/Slave PIO
  - IDE Primary/Secondary Master/Slave UDMA
  - Channel 0 DMA Type F
  - Channel 1 DMA Type F
  - IDE DMA Transfer Mode
  - Large Disk DOS Compatibility
  - IDE LBA Translations
  - LBA Mode Control
  - IDE Prefetch Mode
  - ISA IRQ 9,10,11
  - IDE Translation Mode
  - Onboard CMD IDE Mode 3
  - Enhanced ISA Timing
  - Back To Back I/O Delay
  - DMA FLOW THRU Mode
  - Extended DMA Registers
  - Hold PD Bus
  - DMA Channel Select
  - Concurrent Mode
  - Fast Programmed I/O Modes
  - Local Device Syn. Mode
  - Data Transfer
  - DMA Frequency Select
  - Hard Disk Pre-Delay
  - Initialisation Timeout
- Cacheing
  - Cache RAM (SRAM) Types
  - Pipeline Cache Timing
  - Cache Timing
  - F000 Shadow Cacheable
  - Fast Cache Read/Write
  - Flush 486 cache every cycle
  - Read/Write Leadoff
  - Async SRAM Read WS
  - Async SRAM Write WS
  - Async SRAM Leadoff Time
  - Sync SRAM Leadoff Time
  - Async SRAM Burst Time
  - Cache Burst Read Cycle Time
  - Cache Read Burst
  - Cache Write Burst
  - Cache Read Wait State
  - Cache Write Wait State
  - Cache Read Hit Burst
  - SRAM Read Timing
  - SRAM WriteTiming
  - Cache Address Hold Time
  - Burst SRAM Burst Cycle
  - Cache Mapping
  - Data Pipeline
  - Cache Wait State
  - Cache Read Burst Mode
  - Cache Write Burst Mode
  - Cache Read Cycle
  - SRAM Back-to-Back
  - SRAM Type
  - CPU Internal Cache/External Cache
  - CPU Cycle Cache Hit WS.
  - Cache Write (Hit) Wait State
  - Fast Cache Read Hit
  - Fast Cache Write Hit
  - Cache Tag Hit Wait States
  - Tag Compare Wait States
  - Cache Scheme
  - HITMJ Timing
  - Internal Cache WB/WT
  - External Cache WB/WT
  - CPU Level 1 Cache
  - CPU Level 2 Cache
  - CPU Level 2 Cache ECC Checking
  - CPU L2 cache ECC Checking
  - Cache Write Back
  - L2 Cache Write Policy
  - L1 Cache Policy
  - L1 Cache Update Mode
  - L2 Cache Enable
  - L2 Cache Zero Wait State
  - L2 Cache Cacheable Size
  - L2 Cache ECC Checking
  - L2 Cache Cacheable DRAM Size
  - L2 Cache Latency
  - Cache Over 64 Mb of DRAM
  - Linear Mode SRAM Support
  - M1 Linear Burst Mode
  - Cache Write Cycle
  - Posted Write Enable
  - Posted Write Framebuffer
  - Posted I/O Write
  - Tag Ram Includes Dirty
  - Tag/Dirty Implement
  - Alt Bit Tag RAM
  - Tag Option
  - Tag RAM Size
  - Non-cacheable Block-1 Size
  - Non-cacheable Block-1 Base
  - Non-cacheable Block-2 Size
  - Non-cacheable Block-2 Base
  - Memory above 16 Mb Cacheable
  - Cacheable RAM Address Range
  - XXXX Memory Cacheable
  - C000 Shadow Cacheable
  - Video BIOS Area cacheable
  - Video BIOS cacheable
  - Video Buffer Cacheable
  - System video cacheable
  - System BIOS Cacheable
  - Video BIOS Cacheable
  - Video RAM Cacheable
  - VESA L2 Cache Write
  - Shadow RAM cacheable
  - SRAM Speed Option
  - Cache Early Rising
  - L2 Cache Tag Bits
  - SRAM Burst R/W Cycle
  - SYNC SRAM Support
  - L2 (WB) Tag Bit Length
  - Shortened 1/2 CLK2 of L2 cache
  - VESA L2 Cache Read
  - 1MB Cache Memory
  - Cache Memory Data Buffer
  - Cache Cycle Check
  - Pipeline Burst Cache NA#
  - Cache Read Pipeline
- Memory
  - Bank X/Y DRAM Timing
  - SDRAM SRAS Precharge Delay: tRP
  - SDRAM Addr A Clk Out Drv
  - SDRAM Addr B Clk Out Drv
  - SDRAM CAS/RAS/WE CKE Drv
  - SDRAM DQM Drv
  - SDRAM TRC
  - SDRAM TRP SRAS Precharge
  - SDRAM TRAS Timing
  - SDRAM Trrd Timing Value
  - SDRAM CAS Latency
  - SDRAM TRCD
  - SDRAM Trcd Timing Value
  - Super Bypass Mode
  - Super Bypass Wait State
  - Write Data In to Read Delay
  - Write Recovery Time
  - DRAM Read/Write Timing
  - RAS# To CAS# Delay
  - Memory Read Wait State
  - Memory Write Wait State
  - DRAM Read Wait State
  - Add Extra Wait for RAS#
  - Add Extra Wait for CAS#
  - DRAM (Read/Write) Wait States
  - DRAM Burst Write Mode
  - DRAM Read Burst Timing
  - DRAM Write Burst Timing
  - DRAM Timing Option
  - EDO:SPM Read Burst Timing
  - FP Mode DRAM Read WS
  - DRAM Timing
  - DRAM Timing Selectable
  - DRAM Post Write
  - DRAM Read/FPM
  - Fast DRAM
  - DRAM Write Burst (B/E/P)
  - DRAM Read Burst (B/E/P)
  - DRAM Write Page Mode
  - DRAM Last Write to CAS#
  - DRAM Code Read Page Mode
  - MD Driving Strength
  - DRAM Read Latch Delay
  - Delay DRAM Read Latch
  - Page Code Read
  - Page Hit Control
  - DRAM Precharge Wait State
  - DRAM Wait State
  - DRAM RAS# Precharge Time
  - DRAM Speed
  - DRAM Timing Control
  - DRAM to PCI RSLP
  - FP DRAM CAS Prec. Timing
  - FP DRAM RAS Prec. Timing
  - CAS Low Time for Write/Read
  - DRAM CAS# Hold Time
  - CAS Address Hold Time
  - Read CAS# Pulse Width
  - Write CAS# Pulse Width
  - CAS Read Pulse Width in Clks
  - DRAM RAS# Pulse Width
  - DRAM RAS Precharge Time
  - Write Pipeline
  - RAMW# Assertion Timing
  - EDO CAS Pulse Width
  - EDO CAS Precharge Time
  - EDO RAS Precharge Time
  - EDO RAS# to CAS# Delay
  - EDO RAS# Wait State
  - EDO MDLE Timing
  - EDO BRDY# Timing
  - EDO RAMW# Power Setting
  - EDO DRAM Read Burst
  - EDO DRAM Write Burst
  - EDO Read Wait State
  - EDO read WS
  - DRAM CAS Timing Delay
  - EDO Back-to-Back Timing
  - DRAM RAS# Active
  - DRAM R/W Burst Timing
  - Fast EDO Path Select
  - RAS Precharge Time
  - RAS Precharge Period
  - RAS Precharge @Access End
  - RAS Precharge In CLKS
  - CAS Precharge In CLKS
  - CAS# Precharge Time
  - CAS# width to PCI master write
  - RAS Active Time
  - Row Address Hold In CLKS
  - RAS Pulse Width In CLKS
  - RAS Pulse Width Refresh
  - CAS Pulse Width
  - CAS Read Width In CLKS
  - CAS Write Width In CLKS
  - RAS to CAS delay time
  - RAS(#) To CAS(#) Delay
  - RAS to CAS Delay Timing
  - RAS#-to-CAS# Address Delay
  - DRAM write push to CAS delay
  - CAS Before RAS
  - Late RAS Mode
  - RAS Timeout Feature
  - RAS Timeout
  - Turbo Read Leadoff
  - CAS Width in Read Cycle
  - Read-Around-Write
  - DRAM Read-Around-Write
  - OMC Read Around Write
  - DRAM Write CAS Pulse Width
  - DRAM Head Off Timing
  - Interleave Mode
  - Bank Interleaving
  - Extended Read Around Write
  - F000 UMB User Info
  - Fast Page Mode DRAM
  - Fast R-W Turn Around
  - R/W Turnaround
  - Highway Read
  - DDR Read Path Short Latency Mode
  - Enhanced Page Mode
  - Enhanced Memory Write
  - Page Mode Read WS
  - Pipelined CAS
  - *00 Write Protect
  - Parity Checking Method
  - Parity Check
  - Memory Parity Check
  - Base Memory Size
  - Memory Parity/ECC Check
  - F/E Segment Shadow RAM
  - Disable Shadow Memory Size
  - Disable Shadow Memory Base
  - Memory Remapping (or Relocation/Rollover)
  - 384 KB Memory Relocation
  - 256 KB Remap Function
  - RAM Wait State
  - Memory Reporting
  - Global EMS Memory
  - DRAM Relocate (2, 4 & 8 M)
  - Extended Memory Boundary
  - Shared Memory Size of VGA
  - Shared Memory Enable
  - Cycle Check Point
  - VGA Shared Memory Size
  - Cycle Early Start
  - MA Timing Setting
  - MA Additional Wait State
  - EDO CAS# MA Wait State
  - DRAM Fast Leadoff
  - Reduce DRAM Leadoff Cycle
  - DRAM Read Pipeline
  - Read Pipeline
  - DRAM R/W Leadoff Timing
  - DRAM Leadoff Timing
  - MA Drive Capacity
  - Memory Address Drive Strength
  - Mem. Dr.Str. (MA/RAS)
  - DRAM Speed Selection
  - EDO Speed Selection
  - Fast EDO Leadoff
  - Speculative Leadoff
  - DRAM Speculative leadoff
  - SDRAM Speculative Read
  - DRAM Speculative Read
  - SDRAM Wait State Control
  - SDRAM WR Retire Rate
  - USWC Write Posting
  - USWC Write Post
  - Video Memory Cache Mode
  - CPU Burst Write Assembly
  - OPB Burst Write Assembly
  - SDRAM Leadoff Command
  - SDRAM (CAS Lat/RAS-to-CAS)
  - SDRAM RAS to CAS Delay
  - SDRAM RAS Precharge Time
  - SDRAM Precharge Control
  - SDRAM Page Closing Policy
  - SDRAM CAS Latency Time
  - SDRAM RAS Latency Time
  - SDRAM Cycle Length
  - SDRAM Cycle Time Tras/Trc
  - DRAM Cyle Time
  - DRAM Read Latch Delay
  - Bank cycle time tRC (SDRAM active to precharge time), tRAS
  - SDRAM Bank Interleave
  - DRAM Interleave Time
  - Force 4-Way Interleave
  - CAS Latency
  - Row Precharge Time
  - Configure SDRAM Timing By
  - SDRAM Configuration
  - RAS Pulse Width
  - SDRAM Frequency
  - Burst Length
  - SDRAMIT Command
  - SDRAM WR Retire Rate
  - Special DRAM WR Mode
  - DRAM Clock
  - SDRAM Burst X-1-1-1-1-1-1-1
  - DRAM Command Rate
  - DRAM Act to PreChrg CMD
  - DRAM PreChrg to Act CMD
  - Sustained 3T Write
  - 2 Bank PBSRAM
  - Turn-Around Insertion
  - Turn-Around Insertion Delay
  - DRAM ECC/PARITY Select
  - Single Bit Error Report
  - ECC Checking/Generation
  - Memory Parity/ECC Check
  - Memory Parity SERR# (NMI)
  - OMC Mem Address Permuting
  - OMC DRAM Page Mode
  - DRAM Page Mode Operation
  - CPU to DRAM Page Mode
  - Fast Command
  - Fast Strings
  - Fast MA to RAS# Delay
  - Fast RAS to CAS Delay
  - DRAM Quick Read Mode
  - Bank 0/1 DRAM Type
  - 386 DRAM Quick Write Mode
  - DRAM Page Idle Timer
  - DRAM Page Open Policy
  - DRAM Enhanced Paging
  - DRAM Posted Write Buffer
  - DRAM Data Integrity Mode
  - SDRAM ECC Setting
  - LD-Off DRAM RD/WR cycles
  - CPU-DRAM back-to-back transaction
  - PCI-to-DRAM Prefetch
  - Bank n DRAM Type
  - RDRAM Pool B State
  - DRAM Background Cycles
  - Leadoff DRAM R/W Command
  - Leadoff DRAM B/G Command
  - DRAM Addr/Cmd Rate
  - Auto Detect DIMM/PCI Clk
  - DRAM Idle Timer
  - EMS Enable
- Miscellaneous
  - Turbo Mode
  - Prefetch Caching
  - CPU Low Speed Clock
  - Co-processor Ready# Delay
  - Co-processor Wait States
  - C000 32K Early Shadow
  - Check ELBA# Pin
  - Appian Controller
  - Mouse Support Option
  - IRQ XX Used By ISA
  - IRQ 12 used by ISA or PS/2 Mouse
  - PS/2 Mouse Function Control
  - CPU Address Pipelining
  - CPU Drive Strength
  - Keyboard Reset Control
  - Keyboard Clock Select
  - Novell Keyboard Management
  - Middle BIOS
  - Delay Internal ADSJ Feature
  - Synch ADS
  - Internal ADS Delay
  - NMI Handling
  - Power-On Delay
  - Software I/O Delay
  - Sampling Activity Time
  - GAT Mode
  - Guaranteed Access Time
  - SIO GAT Mode
  - NA# Enable
  - Chipset NA# Asserted
  - LGNT# Synchronous to LCLK
  - LOCAL ready syn mode
  - Local Ready Delay Setting
  - Cyrix A20M Pin
  - Cyrix Pin Enabled
  - Chipset Special Features
  - Host Bus Slave Device
  - Cyrix LSSR bit
  - Host Bus LDEV
  - Polling Clock Setting
  - Assert LDEV0# for VL
  - Signal LDEV# Sample Time
  - Host Bus LRDY
  - Memory Hole At 512-640K
  - LBD# Sample Point
  - 486 Streaming
  - CHRDY for ISA Master
  - NA (NAD) Disable for External Cache
  - Set Mouse Lock
  - ATA-Disc
  - P6 Microcode Updated
  - Disconnect Selection
  - ChipAwayVirus
  - OS Select For DRAM >64MB
  - OS Support for more than 64 Mb
  - OS/2 Compatible Mode
  - Boot to OS/2, DRAM 64 Mb or Above
  - Verifying DMI Status
  - MPS 1.1 Mode
  - POST Testing
  - MPS Version Control For OS
  - Use Multiprocessor Specification
  - BIOS Update
  - In Order Queue Depth
  - Large Disk Access Mode
  - Assign IRQ for VGA
  - Assign IRQ for USB
  - Monitor Mode
  - Speed Model
  - Language
  - Audio DMA
  - S.M.A.R.T. for Hard Disks
  - Spread Spectrum Modulated
  - FSB Spread Spectrum
  - Clock Spread Spectrum
  - Auto Detect DIMM/PCI Clk
  - Boot Speed
  - Physical Drive
  - NCR SCSI at AD17 Present in
  - CPU Warning Temperature
  - PCI Secondary IDE INT# Line
  - Power-Supply Type
  - CPU Core Voltage
  - Quick Frame Generation
  - PCI Primary IDE INT# Line
  - IN0-IN6(V)
  - Current CPU Temperature
  - Current System Temperature
  - Current CPUFAN1 Speed
  - Current CPUFAN1/2/3 Speed
  - Vcore/Vio/+5V/+12V/-5V/-12V
  - MB Temperature, CPU Temperature, POWER Temperature
  - CPU Fan Speed, POWER Fan Speed, CHASSIS Fan Speed
  - VCORE Voltage, +3.3V Voltage, +5 Voltage, +12 Voltage
  - Turbo External Clock
  - Starting Point of Paging
  - Processor Number Feature
  - Linear Merge
  - DREQ6 PIN as
  - Flash BIOS Protection
  - BIOS Protection
  - Drive NA before BRDY
  - 591 Version A Function
  - Hardware Reset Protect
  - MWB Write Buffer Timeout Flush
  - IOQ (4 level)
  - Chassis Intrusion Detection
  - CPU FSB Clock
  - PCI IDE Busmaster
  - CPU FSB/PCI Overclocking
  - S2K I/O Compensation
  - S2K Bus Driving Strength
  - CPU/DRAM CLK Synch CTL
  - CPU Ratio/Vcore (V)
  - CS[5.0]# Hold Time CTL
  - DQS/CSB Hold Time CTL
  - CKE Hold Time CTL
  - DRAM Ratio H/W Strap
  - DOS Flat Mode
  - Act Bank A to B CMD Delay
  - DRAM Driver Slew
  - DDR RAM CAS Latency
  - DDR Voltage
  - FPU OPCODE Compatible Mode
  - Game Accelerator
  - N/B Strap CPU As
  - Athlon 4 SSED Instruction
  - CPU Hyper-Threading
  - ISA Enable Bit
  - Master Priority Rotation
  - P2C/C2P Concurrency
  - Memory Termination
  - ISA 14.318MHz Clock
VGA BIOS
- AGP
  - AGP Aperture Size (64 Mb)
  - Graphic Win Size
  - AGP 2X Mode
  - AGP 4x Mode
  - AGP 8x Mode
  - 4X AGP Support
  - AGP 4x Drive Strength
  - AGP Drive Strength P or N Ctrl
  - AGP Driving Control
  - AGP Driving Value
  - AGP Comp. Driving
  - Manual AGP Comp. Driving
  - AGPCLK/CPU FSB CLK
  - AGP Fast Write Transaction
  - AGP Fast Write
  - AGPCLK/CPUCLK
  - AGP Transfer Mode
  - AGP Master 1 WS Read
  - AGP Master 1 WS Write
  - AGP Sideband Support
  - AGP Read Synchronisation
  - Core Chip Clock Adjust
  - AGP ISA Aliasing
  - AGP Always Compensate
  - DBI Output for AGP Trans
  - No Mask of SBA FE
  - Init Display First
  - Init AGP Display First
  - Video Memory Clock Adjust
  - Chip Voltage Adjust
  - V-Ref & Memory Voltage Adjust
  - Boot Up Display Select
  - Fan Speed
  - GPU Temperature
  - TV-Out Format
  - Post Up Delay
  - Post Up Prompt
  - ISA Linear Frame Buffer
  - Residence of VGA Card
  - ISA LFB Size
  - ISA VGA Frame Buffer Size
  - VGA Memory Clock (MHz)
  - VGA Frame Buffer
  - Video Palette Snoop
  - Palette Snooping
  - Graphic Window WR Combine
  - PCI/VGA Palette Snoop
  - VGA Palette Snoop
  - PCI/VGA Snooping
  - VGA DAC Snooping
  - Snoop Filter
  - PCI VGA Buffering
  - Initial Display
  - Search for MDA Resources
  - Primary VGA BIOS
  - Video Shadow Before Video Init
  - Turbo VGA (0 WS at A/B)
Power Management
- Smart Battery System
- PM Control by APM
- Power Management/APM
- Power Management
- ACPI Function
- ACPI Standby State
- ACPI Suspend Type
- USB Wakeup from S3
- ACPI Suspend-to-RAM
- Call VGA at S3 Resuming
- Power/Sleep LED
- PM Events
- GP 105 Power Up Control
- IDE Standby Power Down Mode
- HDD Power Down
- HDD Standby Timer
- Standby Mode Control
- IDE Spindown
- Doze Timer/System Doze
- Power-down mode timers
- Global Standby Timer
- Green Timer
- Suspend Timer
- Global Suspend Timer
- Sleep Clock
- Sleep Timer
- Suspend Mode Option
- Suspend Mode
- Suspend Mode Switch
- Suspend Option
- Auto Keyboard Lockout
- CPU Clock (System Slow Down)
- Event Monitoring
- Monitor Power/Display Power Down
- Monitor Event in Full On Mode
- Individual IRQ Wake Up Events (System IRQ Monitor Events)
- IRQ 1(-15) Monitor
- IRQ8 Break Suspend
- IRQ8 Break [Event From] Suspend
- IRQ8 Clock Event
- DRQ 0 (-7) Monitor
- System Events I/O Port Settings
- Keyboard IO Port Monitor
- Floppy IO Port Monitor
- Hard Disk IO Port Monitor
- Video Port IO Monitor
- VGA Adapter Type
- Video Memory Monitor
- Low CPU Clock Speed
- Power Management Control
- Power Management RAM Select
- O.S
- Factory Test Mode
- APM BIOS
- APM BIOS Data Area
- ACPI I/O Device Node
- Device Power Management
- System Power Management
- Auto Clock Control
- Power Button Override
- PWR Button < 4 Secs
- Power Down and Resume Events
- DMA Request
- Reload Global Timer Events
- NON-SMI CPU Support
- Video Off In Suspend
- Throttle Duty Cycle
- Soft-off by PWR-BTTN
- Power Button Function
- Switch Function
- System Monitor Events
- Video Off Option
- Video Off After
- Video Off Method
- Resume By Ring
- Resume By LAN/Ring
- RTC Alarm Resume
- Wake up on PME
- Wake up on Ring/LAN
- Ring Power Up Act
- Resume By Alarm
- Resume by USB From S3
- WakeUp by OnChip Lan
- Alarm Date/Hour/Minute/Second
- Keyboard Resume
- Thermal Duty Cycle
- CPU Warning Temperature
- CPU Critical Temperature
- Fan Failure Control
- Automatic Power Up
- After AC Power Loss
- AC PWR Loss Restart
- Power On By PS/2 Keyboard
- Power On By PS/2 Mouse
- Instant On Support
- ZZ Active in Suspend
- Advanced OS Power
- BIOS PM on AC
- BIOS PM Timers
- COM Port Activity
- VGA Activity
- VGA Active Monitor
- Video Timeout
- LPT Port Activity
- CPU Fan Off In Suspend
- CPU Fan on Temp High
- Doze Mode
- Doze Timer
- Doze Timer Select
- Doze Mode Control
- Doze Speed (div by)
- Standby Speed (div by)
- Wake/Power Up On Ext. Modem
- Standby Mode Control
- Standby Timer Select
- Standby Timers
- FDD/COM/LPT Port
- FDD Detection
- HDD detection
- Video Detection
- IRQn Detection
- LREQ Detection
- Wake on Ring
- Wake Up Events
- Wake Up Event in Inactive Mode Enable
- WakeUp Event In Inactive Mode
- Inactive Mode Control
- Watch Dog Timer
- WDT Active Time
- WDT Configuration Port
- WDT Time Out Active For
- Boot from LAN first
- CRT Power Down
- CRT Sleep
- GPI05 Power Up Control
- Day of Month Alarm
- Month Alarm
- Week Alarm
- Hot Key Power Off
- LDEV Detection
- Shutdown Temperature
- DRQ Detection
- Modem Use IRQ
- Power Up On PCI Card
- Suspend To RAM
- Primary INTR
- Inactive Timer Select
- Display Activity/IRQ3/IRQ4……
- Clock Throttle
- K7 CLK_CTL Select
Plug and Play/PCI
- High Priority PCI Mode
- PCI Master Read Caching
- Resources Controlled By
- Force Updating ESCD
- Clear NVRAM
- 430HX Global Features
- APIC Function
- IO APIC
- APIC Mode
- Interrupt Mode [APIC]
- Latency Timer (PCI Clocks)
- PCI Latency Timer
- Reset Configuration Data
- Slot PIRQ
- Using IRQ
- Slot 1/5, 2, 3, 4 IRQ
- Host-to-PCI Bridge Retry
- PCI Delayed Transaction
- Delayed Transaction/PCI 2.1 support/passive release
- PCI Dynamic Bursting
- DMA Channel 0/1/3/5/6/7
- IRQ 3/5/7/9/10/11/14/15
- PCI Slot x INTx
- PCI Slot 1 IRQ, PCI Slot 2 IRQ
- Slot x INT# Map To
- Slot X Using INT#
- Edge/Level Select
- PCI Device, Slot 1/2/3
- Enable Device
- Xth Available IRQ
- 1st-6th Available IRQ
- IRQ Assigned To
- PCI IRQ Activated by
- PIRQ_0 Use IRQ No. ~ PIRQ_3 Use IRQ No.
- IDE Speed
- DMA Assigned To
- DMA n Assigned To
- 1st/2nd Fast DMA Channel
- IDE Prefetch Buffers
- PCI IDE Prefetch Buffers
- Configuration Mode
- PCI IDE 2nd Channel
- PCI Slot IDE 2nd Channel
- PCI timeout
- PCI to L2 Write Buffer
- Primary IDE INT#, Secondary IDE INT#
- Primary & Secondary IDE INT#
- Primary 32 Bit Transfers Mode
- Secondary 32 Bit Transfers Mode
- PCI IDE IRQ Map to
- PCI-Slot X
- PCI Bus Parking
- Primary Frame Buffer
- IDE Burst Mode
- IDE Data Port Post Write
- IDE Buffer for DOS & Win
- IDE Master (Slave) PIO Mode
- Host Clock/PCI Clock
- HCLK PCICLK
- ISA Bus Clock
- ISA Clock
- ISA Bus Clock Option
- ISA Bus Clock Frequency
- PCI Write-byte-Merge
- PCI-ISA BCLK Divider
- PCI Write Burst
- PCI Write Burst WS
- CPU-to-PCI Read Buffer
- PCI-Auto
- CPU-To-PCI Write Buffer
- PCI-to-CPU Write Buffer
- PCI Write Buffer
- PCI-To-CPU Write Posting
- CPU-to-PCI Read-Line
- L2 to PCI Read Buffer
- CPU-to-PCI Read-Burst
- Byte Merging
- Byte Merge Support
- CPU to PCI Byte Merge
- Word Merge
- PCI to DRAM Buffer
- Latency for CPU to PCI write
- PCI Cycle Cache Hit WS
- Use Default Latency Timer Value
- Latency Timer Value
- PCI Master Latency
- Latency from ADS# status
- Max burstable range
- CPU Host/PCI Clock
- CPU to PCI burst memory write
- CPU-To-PCI Burst Mem. WR.
- CPU to PCI Bursting
- CPU to PCI post memory write
- CPU to PCI Write Buffer
- CPU to PCI Buffer
- PCI to ISA Write Buffer
- DMA Line Buffer
- ISA Master Line Buffer
- SIO Master Line Buffer
- ISA Line Buffer
- CPU/PCI Post Write Delay
- Post Write Buffer
- SIO PCI Post Write Buffer
- Post Write CAS Active
- PCI master accesses shadow RAM
- Enable Master
- AT bus clock frequency
- Base I/O Address
- Base Memory Address
- Parity
- Memory Hole
- Memory Map Hole; Memory Map Hole Start/End Address
- Memory Hole Size
- Memory Hole Start Address
- Memory Hole at 15M Addr.
- Memory Hole at 15M-16M
- Local Memory 15-16M
- 15-16M Memory Location
- Multimedia Mode
- E8000 32K Accessible
- P5 Piped Address
- PCI Arbiter Mode
- PCI Arbitration Rotate Priority
- Stop CPU When Flush Assert
- Stop CPU when PC Flush
- Stop CPU at PCI Master
- Preempt PCI Master Option
- I/O Cycle Recovery
- I/O Recovery Period
- Action When W_Buffer Full
- CPU Pipelined Function
- Pipelined Function
- Fast Back-to-Back
- CPU-to-PCI Fast Back to Back
- PCI Fast Back to Back Wr
- Primary Frame Buffer
- M1445RDYJ to CPURDYJ
- Delay ISA/LDEVJ check in CLK2
- VESA Master Cycle ADSJ
- CPU Dynamic-Fast-Cycle
- LDEVJ Check Point Delay
- Master IOCHRDY
- CPU Memory sample point
- Memory Sample Point
- PCI to CPU Write Pending
- LDEV# Check point
- Local Memory Detect Point
- Local memory check point
- Delay for SCSI/HDD (Secs)
- FRAMEJ generation
- Busmaster IDE on PCI
- VGA Type
- PCI Mstr Timing Mode
- PCI Arbit. Rotate Priority
- I/O Cycle Post-Write
- PCI Post-Write Fast
- CPU Mstr Post-WR Buffer
- Graphic Posted Write Buffer
- PCI Mstr Post-WR Buffer
- CPU Mstr Post-WR Burst Mode
- PCI Mstr Burst Mode
- CPU Mstr Fast Interface
- PCI Mstr Fast Interface
- CAS Delay in Posted-WR
- CPU Mstr DEVSEL# Time-out
- PCI Mstr DEVSEL# Time-out
- IRQ Line
- Arbiter timer timeout (PC CLK) 2 x 32
- Fast Back-to-Back Cycle
- State Machines
- On Board PCI/SCSI BIOS
- PCI I/O Start Address
- PCI Memory Start Address
- VGA 128k Range Attribute
- CPU-PCI Burst Memory Write
- CPU-PCI Post Memory Write
- Posted PCI Memory Writes
- CPU-To-PCI Write Posting
- CPU To PCI Write Buffers
- OPB P6 to PCI Write Posting
- OPB PCI to P6 Write Posting
- CPU-To-PCI IDE Posting
- CPU Read Multiple Prefetch
- CPU Line Read Multiple
- OPB P6 Line Read
- CPU Line Read Prefetch
- OPB Line Read Prefetch
- CPU Line Read
- CPU Read Multiple Prefetch
- DRAM Read Prefetch Buffer
- Read Prefetch Memory RD
- VGA Performance Mode
- Snoop Ahead
- DMA Line Buffer Mode
- Master Arbitration Protocol
- Host-to-PCI Wait State
- PCI Prefetch
- PCI Parity Check
- PCI Memory Burst Write
- PCI Clock Frequency
- 8 Bit I/O Recovery Time
- 16 Bit I/O Recovery Time
- 8/16 Bit I/O Recovery Time
- IO Recovery (BCLK)
- I/O Recovery Time
- PCI Mem Line Read
- PCI Mem Line Read Prefetch
- PCI Concurrency
- Concurrent PCI/Host
- Peer Concurrency
- PCI Bursting
- PCI (IDE) Bursting
- PCI Dynamic Bursting
- PCI Burst Write Combine
- Burst Write Combine
- PCI Preempt Timer
- Keyboard Controller Clock
- Burst Copy-Back Option
- PCI Streaming
- PCI-To-DRAM Pipeline
- IBC DEVSEL# Decoding
- CPU Pipeline Function
- PCI Dynamic Decoding
- CPU to PCI POST/BURST
- PCI Pre-Snoop
- Secondary CTRL Drives Present
- PCI Read Burst WS
- PCI Master Cycle
- Master Retry Timer
- CPU/PCI Write Phase
- PCI CLK
- IRQ 15 Routing Selection
- CPU cycle cache hit sam point
- PCI cycle cache hit sam point
- Plug and Play OS
- PnP OS
- PCI Passive Release
- Delayed Transaction
- PCI 2.1 Compliance
- Chipset Global Features
- FDD IRQ Can Be Free
- Multi Transaction Timer
- Multi-function INTB#
- Shared VGA Memory Speed
- PCI Master 0 WS Write
- PCI Master 1 WS Write
- PCI Master 1 WS Read
- PCI Delay Transaction
- PCI Master Read Prefetch
- PCI#2 Access #1 Retry
- Master Priority Rotation
- PCI Arbitration Mode
- PCI Bus Clock
- PCI IDE Bursting
- PCICLK-to-ISA SYSCLK Divisor
- Used By Legacy Device
- Use MultiProcessor Specification
- Write Allocate
- Extended CPU-PIIX4 PHLDA#
- Used MEM length
- Used Mem Base Addr
- Close Empty DIMM/PCI Clk
- FWH (Firmware Hub) Protection
- Ultra DMA 66 IDE Controller
- USB Function For DOS
- Flash Write Protect
- FPU OPCODE Compatible Mode
- CPU fast String
- PCI Master Read Caching
- SDRAM Closing Policy
- PCI/DIMM Clk Auto Detect
- High Priority PCI Mode
- LDT Setting
Peripheral Setup
- Programming Option
- Configuration Mode
- TxD, RxD Active
- Use IR Pins
- On Chip Serial ATA Mode
- OnChip Serial ATA
- SATA RAID ROM
- On Chip IDE Buffer (DOS/Windows)
- On Chip IDE Mode
- IDE 0 Master/Slave Mode, IDE 1 Master/Slave Mode
- On Chip Local Bus IDE
- On-Chip Primary PCI IDE
- On-Chip Secondary PCI IDE
- On-Chip Video Window Size
- On Chip PCI Device
- 2nd Channel IDE
- IDE Second Channel Control
- PCI IDE Card Present
- Onboard Floppy Drive
- Onboard FDC Controller
- Onboard FDC Swap A: B:
- Onboard IDE
- FDC Function
- Onboard Serial Port 1
- Onboard UART 1/2
- Onboard UART 1/2 Mode
- Onboard ATA Device First
- UART Mode Select
- Internal PCI/IDE
- UART 1/2 Duplex Mode
- UR2 Mode
- Serial Port 2 Mode
- First Serial Port
- Parallel Port Address
- IRQ Active State
- SuperIO Device
- Onboard Parallel Port
- Onboard IDE Controller
- Onboard PCI SCSI Chip
- Onboard Audio Chip
- Onboard PCI Device
- ECP DMA Select
- ECP Mode DMA
- Parallel Port EPP Type
- Port Mode
- Parallel Port Mode
- Enable/Disable.UART 2 Mode.
- Parallel Port
- LPT Extended Mode
- EPP Version
- EPP Mode Select
- DMA Channel
- WAVE2 DMA Select
- WAVE2 IRQ Select
- Floppy DMA Burst Mode
- Serial Port 1 MIDI
- USB Controller
- USB Function
- Assign IRQ For USB
- USB Keyboard Support
- USB Keyboard Support Via
- USB Latency Time (PCI CLK)
- USB Legacy Support
- Infrared Duplex
- Infra Red Duplex Type
- IR Function Duplex
- IR Duplex Mode
- Duplex Select
- IR Pin Select
- UART2 Use Infrared
- Onboard VGA Memory Size (iMb)
- Onboard VGA Memory Clock
- IRRX Mode Select
- NCR SCSI BIOS
- Write Buffer Level
- Offboard PCI IDE Card
- Audio DMA Select
- Audio I/O Base Address
- Audio IRQ Select
- USB Keyboard Support
- Onboard IR Function
- Onboard Game Port
- Onboard MIDI Port
- Onboard RAID
- MIDI IRQ Select
- Joystick Function
- MPU-401 Configuration
- MPU-401 I/O Base Address
- Serial Port 1/2 Interrupt
- PWRON After PWR-Fail
- Keyboard Power On Function
- Mouse Power On Function
- COMn
- AC97 Audio
- MC97 Modem
- Port 64/60 Emulation
- Onboard Card Reader Type
- PCI Card Support for SMBus
- Disable Unused PCI Clock
- Speech POST Reporter
- System Monitor Setup
  - Delay Prior To Thermal
  - FAN Fail Alarm Selectable
  - Shutdown when FAN Fail
  - CPU FanEQ Speed Control
  - Active Temperature
  - CPU Shutdown Temperature
  - All Voltages, Fans Speed and Thermal Monitoring
  - Fan Speed
  - Voltage Values
  - VCCVID(CPU) Voltage, VTT(+1.5V) Voltage
  - I/O Plane Voltage
  - Core Plane Voltage
  - Plane Voltage
  - LCD&CRT
Nasty Noises
- Advantage/Bravo/Manhattan/Ascentia/Premium/Premmia
- Advantage/Bravo
- Manhattan
- Ascentia J
- Ascentia 810/800/Explorer/Bravo
- BIOS Update Beep Codes
- AST Enhanced
- Early Premium 286
- Early POST Beep Codes
- AST Phoenix
- v4.51
- XT 8086/88 v3.0
- 286/386 v3.03
- EGA BIOS v1.6
- General
- Contura 400 Family
- AT
- Prospeed 486SX/C
Error Messages & Codes
- v4.5x
- XT 8086/88 v3.0
- 286/386 v 3.03
- ISA/EISA v4.5
- M24 Memory Errors
Post Codes
- Shutdown or Reset Commands
- Manufacturing Loop Jumper
- Obtaining Information About Your Computer
- POST Procedures
- AMI BIOS 2.2x
- AMI Colour BIOS
- AMI Ez-Flex BIOS
- AMI Old BIOS; 08/15/88-04/08/90
- AMI Plus BIOS
- AMI BIOS 04/09/90-02/01/91
- AMI New BIOS; 02/02/91-12/12/91
- AMI New BIOS; 06/06/92-08/08/93
- AMI WinBIOS; 12/15/93 Onwards
- 10/10/94
- Version 6.2 - 7/15/95
- Legacy BIOS
- Early POST Codes
- Version 3.0
- Version 3.00-3.03 8/26/87 286 N3.03 Extensions
- XT 8088/86 v3.1
- 386 v3.1
- ISA/EISA v4.0
- EISA BIOS
- Award Test Sequence-up to v4.2
- Award Test Sequence-after v4.2 (386/486)
- 3.Ox
- 3.00-3.03 8/26/87
- 286 N3.03 Extensions
- Original XT
- XT 8088/86 BIOS v3.1
- Modular (386) BIOS v3.1
- ISA/EISA BIOS v4.0
- EISA BIOS
- 4.5x-non PnP
- 4-5x PnP Elite
- Version 6.0 (Jan 29, 1999)
- Version 6.0 (Jan 29, 1999) Quick Post
- Version 6.0 S4 Codes
- Version 6.0 Boot Block Codes
- Award 6.0 Rev 1.0 11/03/99 Medallion (i810)
- Unexpected Errors
- v3.3
- POST Procedures
- POST Codes
- General
- Overall Power Up Sequence
- Base RAM Initialisation
- Base RAM Test
- VDU Initialisation and Test
- Memory Test
- 80286 Protected Mode
- 8042 and Keyboard
- System Board Test
- Diskette Test
- EISA TESTS (Deskpro/M, /LT, /33L, P486c)
- LT, SLT, LTE
- Standard POST Functions
- Option ROM Replacement
- Port 85=05 (Video POST)
- 286 DeskPro
- 386 DeskPro
- 486 DeskPro
- Non-Fatal Error Meanings tor ATs
- Post Procedures-Symphony 486 BIOS
- POST Codes
- Vectra
- Vectra ES
- Vectra QS & RS
- Pavilion Series 3100 & 8000
- IBM POST I/O Ports
- POST Procedures
- XT (Port 60)
- AT POST Codes
- Additional Protected Mode Tests
- PS/2 (Micro Channel) POST Codes
- CA810E
- Boot Block Recovery Code Checkpoints
- Runtime Code Uncompressed in F000 Shadow RAM
- 440 Series
- 440GX
- 440BX
- OR840
- XT Jumpstart
- AT Jumpstart
- POST Procedures
- OEM Specific
- Non-Fatal Errors
- 3.3
- 3.4
- 4.71
- EISA/ISA
- PC6
- 3302/3304/3728/PC916SX
- PC916 5/6
- 1076/AT&T 6312/WGS 80286
- M20
- M21/M24 (AT&T 6300)
- EISA 2.01
- PS/2 Compatible
- Philips Platform Cross Reference
- POST Procedures
- 2.52 BNP XT
- BIOS Plus or v1.0 POST/Beep Codes
- PCI
- Phoenix v3.07
- ISA/EISA/MCA BIOS POST/Beep Codes (fatal)
- ISA/EISA/MCA BIOS POST/Beep Codes (non-fatal)
- PicoBIOS v4.0 R6/UMC Chipset PCI
- v4.0 R6
- V4 Rel 6
- v3.07 AT BIOS (Phoenix 3.07)
- 16K XT
- PC/XT/AT
- Type A AT 29 Feb 1988
- Type B AT-1992
- 486 EISA-10 Oct 1989
- Post Procedures
- POST Codes
- Orion 4.1E-1992
- 191 BIOS -1992
INDEX
- Symbols
- Numerics
- A
- B
- C
- D
- E
- F
- G
- H
- I
- J
- K
- L
- M
- N
- O
- P
- Q
- R
- S
- T
- U
- V
- W
- X
- Z

Nội dung

1 The BIOS Companion Phil Croucher Legal Bit This book and any included software is sold as is without warranty of any kind, either express or implied, including but not limited to the implied warranties of merchantability and fitness for a particular purpose. Neither the Author, the Publisher nor its dealers or distributors assumes any liability for any alleged or actual damages arising from their use. Translation: Although this information has been gathered from original manufacturer's details or practical experience, it is always changing, or scarce, so there could be technical inaccuracies or typographical errors. As a result, changes will be made to the information in this book and included software without reference to anyone, and we don't guarantee that the product suits your purposes. As well, no liability is accepted for loss of data or business or damage to equipment as a result of using the information contained herein - backups are your responsibility! Copyrights, etc Windows, Windows `95, Windows NT, DOS and Xenix are trademarks and Microsoft is a registered trademark of Microsoft Corporation. Novell and NetWare are registered trademarks of Novell, Inc. Macintosh is a registered trademark of Apple Computer, Inc. VAX is a trademark of Digital Equipment Corporation. 8086, 80286, i386, i486, i486DX, i486DX2, i486DX4, i486SX, and i487SX, Intel OverDrive Processor are trademarks of Intel Corp. UNIX is a registered trademark of UNIX System Laboratories. IBM, PC, XT, AT and OS/2 are trademarks of International Business Machines Corp. PCI is a registered trademark of PCI Special Interest Group. Triton is a trademark of a company in Germany. Any code listings, although obtained from sites that are publicly accessed, may be copyrighted by their respective manufacturers. All other proprietary trade names, trademarks and names protected by copyright are fully acknowledged. They are mentioned for editorial purposes, with no intention of infringing them. This book copyright © 1986-2004 Phil Croucher. ISBN 0-9681928-0-7 All rights reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, without prior written permission from the author. Notice is hereby given that the name PHILIP ANDREW CROUCHER, in capital letters, or any variation thereof, is claimed by Phil Croucher, which name may not be used without permission. Sources Which are gratefully acknowledged: • Experience. • Many conversations with technicians. • Hundreds of motherboard manuals, not all of which were helpful! • AMI BIOS Tech Ref manual. • MR BIOS Tech Ref Manual. Thanks to Mike at Microid Research! • Readers, including Mick O'Donnell, Martyn Smith, Chris Crook, Chris Nicholson, Dart Computers, Pat Tan, John Dallman, Ulf Boehlau, Rick and Tilman at ProData, Adrian Clint of Samsung, Peter Farrow, Kerry and Toni at Award Software, Chuck French at Unicore, Ali Kiafar at ECS/TTX, John Dann at ProData, Jerome Czeikus and Mike Echlin. • amibios.txt, available from Jean-Paul Rodrigue in the University of Montreal, which had useful snippets, especially the explanation of Fast Decode. • amisetup, a shareware program from Robert Muchsel.Copyrights, etc. Praise For The BIOS Companion “The computer book of the month is The Bios Companion by Phil Croucher. Long-time readers of this column will recall I have recommended his book before. This tells you everything you ought to know about the BIOS in your system. Post codes, options, upgrades, you name it. Years ago, I called an earlier edition of this invaluable and I see no reason to change my view. Recommended.” Jerry Pournelle, Byte Magazine “You will find more information about your motherboard assembled here than I have ever seen.” Frank Latchford PCCT “Thank! I really appreciated this. I read it and was able to adjust my BIOS settings so that my machine runs about twice as fast. Pretty impressive. Thanks again.” Tony “This book is worth far more than is charged for it. Very well written. Probably the most-used reference book in my shop. a great value as the feature explanations trigger your thinking and allow you to figure out many related BIOS features in some of the newer versions.” Amazon reader “For those who need or want to fine tune, or simply understand, the basic and advanced features of their PC's BIOS, this book is an invaluable guide. It has a very broad range and covers both fundamental and more advanced topics as well as issues specific to particular bios types ( AMI, PHOENIX, etc. ) and versions. This is one book you need to have as a PC technician and a valuable resource for trouble shooting and configuring your personal PC even if your not.” Amazon reader “I found The Bios companion so useful that I "just have" to have all 3 books in the set. The extra Bios Companion is going to a friend who will gain great benefit from it. Yes I definitely want all three books. Thank you very much.” Mike Reinbolt “I received my package today containing the BIOS Companion book and 2 CD set I'm really impressed with what I did receive. I already had about HALF of the information, and to get THAT much, I had to get several books and web pages. GOOD JOB!! I had more time to go thru the book and think that you should change the word "HALF" to "FOURTH". I commend you on the great job you did. That's a hell of a lot of work for any major company to do, let alone an individual.” Craig Stubbs “I thoroughly enjoyed my purchase! The BIOS Companion is worth the cost just for the beep-code section alone. I am new to computers and have found the book and your site to be quite informative.” pcworker “I thought the BIOS Companion was quite good. Just chock full of the kind of info I had been looking for. First book I've gotten that was worth the more than price I paid.” Tony “While you are appreciative of my order, I am likewise appreciative of your efforts to make such a reference available. BIOS's are the most mysterious things in the computing world to figure out. I realize the BIOS manufactures have made great effort to provide detailed information in the BIOS help (F1) (ok, so that's a bit of sarcasm). Traditionally, I have had to piece bits of information together that I have found at various locations. Once again thanks.” Brian Presson, System Engineer “The Bios companion is an absolute must for anyone who builds or configures PC's! It is by far worth the money you pay for it. Phil Croucher has done a superb job! He explains in great detail all of the settings that even most PC technicians have no idea of what they do or effect, and mostly some very helpful suggestions on system settings as well. An Absolute Must have!” Larry Stark, LPG Computers Memphis, TN “I purchased the 2000 edition of the complete The BIOS Companion - PDF from DigiBuy today. Any way you look at it, the information contained is well worth the $15 dollar investment. I must personally thank you for publishing such a wonderful resource for techies such as myself. Thank you again for all of the hard work.” Sincerely, Boyd Stephens “I spent two hours going through the different sections therein. Everything is there and I can only say, 'AWSOME'.” Robert, San Francisco “Hi, Phil The book is absolutely phenomenal !! - Congratulations ! This is exactly the kind of reference many people (including our instructors) need - everything in one place, beautifully organised, crammed full of essential, UNDERSTANDABLE, info.” Alain Hendrikse, South Africa “Your BIOS guide I had from 1994 was one of those 'never throw it away' items that I knew I would need an update for.” Adrian Clint The BIOS Companion i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents 1The BIOS 1 BIOS Data Area 2 What Happens When You Switch On 13 How old is my BIOS? 13 Identifying Your BIOS 14 What's in my machine (using debug)? 37 Where Can I Get A New BIOS? 40 Flash BIOS Upgrades 40 Recovering A Corrupt BIOS 43 DMI 44 Facilities Provided 44 2The Motherboard 47 The Central Processor 49 Chip Reference Chart 63 3Memory 67 Static RAM 67 Dynamic RAM 67 Wait states 69 Shadow RAM 76 Random Access Memory 77 CMOS Memory Map 83 Numbers On Chips 87 4Bus Types 90 ISA 90 EISA 91 Micro Channel Architecture 91 Local Bus 91 PCMCIA 93 USB 94 FireWire 95 CONTENTS ii The BIOS Companion 5Expansion Cards 95 Direct Memory Access (DMA) 95 Base Memory Address 98 Base I/O Address 99 Interrupt Setting 101 6 Performance 105 7 Open Sesame 107 Setup Programs 108 8 Softmenu Setup 109 9 Standard CMOS Setup 111 Settings 111 10 Advanced CMOS Setup 119 Settings 119 11 Advanced Chipset Setup 133 Refresh 134 Data Bus 139 Cacheing 152 Memory 164 Miscellaneous 193 12 VGA BIOS 207 AGP 207 13 Power Management 217 14 Plug and Play/PCI 233 ESCD 234 PCI Identification 234 PCI Slot Configuration 256 . . . . . CONTENTS The BIOS Companion iii 15 Peripheral Setup 289 System Monitor Setup 298 16 Nasty Noises 301 ALR 301 Ambra 301 AMI 301 AST 302 Award 307 Compaq 308 Dell (Phoenix) 311 IBM 312 MR BIOS 313 Mylex/Eurosoft 313 NEC 314 Packard Bell 315 Phoenix 315 Quadtel 316 Tandon 316 17 Error Messages & Codes 317 AMI 317 AST 319 Award 320 HP Vectra 322 Olivetti 324 Phoenix 325 18 Post Codes 327 What is a POST Diagnostic Card?328 ACER 329 ALR 330 Ambra 331 AMI 331 Arche Technologies 354 AST 356 AT&T 358 Award 364 Chips and Technologies 388 Compaq 391 CONTENTS iv The BIOS Companion Dell 396 DTK 398 Eurosoft 399 Faraday A-Tease 399 Headstart 399 HP 400 IBM 406 Intel 411 Landmark 426 Magnavox 427 Micronics 427 MR BIOS 428 Mylex/Eurosoft 434 NCR 435 Olivetti 438 Packard Bell 443 Philips/Magnavox/Headstart 443 Phoenix 444 Quadtel 457 SuperSoft 459 Tandon 460 Tandy 464 Wyse 464 Zenith 464 The BIOS Companion 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T HE BIOS 1 he instructions that turn a PC into a useful machine come in three stages, starting with application programs, which are loaded by an operating system, which in turn is loaded by a bootstrap loader in the BIOS (the Basic Input/Output System). There are several in a PC, a good example being the one on the video card that controls the interface between it and the computer. However, we are concerned with the System BIOS, which is a collection of assembly language routines that allow programs and the components of a PC to communicate with each other at low level. It therefore works in two directions at once and is active all the time your computer is switched on. In this way, software doesn't have to talk to a device directly, but can call a BIOS routine instead. However, the BIOS is quite an Achilles Heel and can produce many incompatibilities, so these days it is often bypassed by 32-bit software (DOS relied on it totally) - some functions have migrated to the operating system, starting with Power Management (see ACPI), but NT and W2K have long been replacing BIOS Code with their own Hardware Abstraction Layer (HAL) in the Shadowed ROM area traditionally used by the BIOS after the machine has started. LinuxBIOS is an Open Source project aimed at replacing it with a little hardware initialization and a compressed Linux kernel that can be booted from a cold start (inside 3 seconds at last count). Linux, once bootstrapped, does not make use of BIOS calls, as it has all the low level hardware drivers itself. In addition, a "trusted BIOS" is being developed that can be included in any system that requires high assurance, such as NetTop. Some access to the Video BIOS is also allowed by some manufacturers. For the moment, though, the System BIOS will work in conjunction with the chipset, which is really what manages access to system resources such as memory, cache and the data buses, and actually is the subject of this book, as all those advanced settings relate to the chipset and not the BIOS as such. On an IBM-compatible, you will find the BIOS embedded into a ROM on the motherboard, together with hard disk utilities and a CMOS setup program, although this will depend on the manufacturer (the BIOS and CMOS are separate items). The ROM will usually occupy a 64K segment of upper memory at F000 in an ISA system, and a 128K segment starting at E000 with EISA or similar. It's on a chip so it doesn't get damaged if a disk fails, as sometimes used to happen on the Victor 9000/Sirius, which had the BIOS and system on the boot floppy. Older machines, such as 286s, will have two ROMs, labelled Odd and Even, or High and Low (they must be in the right slots), because of the 16-bit bus, but these days there tends to be only one-look for one with a printed label (older 386s sometimes had 4). You can get away with one because BIOS code is often copied into Shadow RAM (explained later), and not actually executed from ROM, but from extended memory. In addition, much of the code is redundant once the machine has started, and it gets replaced by the operating system anyway. Some newer machines may actually have two single-chip BIOSes, so if one fails, the back-up kicks in. Well, in theory, anyway - there have been reports of the BIOSes flashing each other out, so later backups have become read-only. T THE BIOS BIOS Data Area 2 The BIOS Companion 1 A Flash ROM allows you to change BIOS code without replacing chip(s). Flash ROM, or programmable read-only nonvolatile RAM, if you want to be posh, is similar to the EEPROM, being a storage medium that doesn't need a continuous power source, but deals with several blocks of memory at once, rather than single bytes, making it slightly faster, but only just. Also, Flash devices can be programmed in situ, whereas EEPROMS need a special device. Older BIOSes used EPROMs, which require ultra violet light to erase them, so were a more permanent solution. Even older BIOSes used PROMs, which can't be changed at all once programmed. All are nonvolatile, which means that they don't need a continuous source of power to keep information in them. Actually, this does include CMOS chips, as the power referred to is mains and not battery power, but the A+ exam might not agree. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIOS DATA AREA As well as ROM space, the BIOS takes 256 bytes of low memory as a BIOS Data Area, which contains details about the Num Lock state, keyboard buffer, etc. DOS, or whatever, loads higher than this, so it's quite safe. When power is applied, the BDA is created at memory location 0040:0000h. Here is what's in it:: Hex Dec Service Size Function 00h 0 Int 14h 2 bytes Base I/O address for serial port 1 (COM 1) 02h 2 Int 14h 2 bytes Base I/O address for serial port 2 (COM 2) 04h 4 Int 14h 2 bytes Base I/O address for serial port 3 (COM 3) 06h 6 Int 14h 2 bytes Base I/O address for serial port 4 (COM 4) 08h 8 Int 17h 2 bytes Base I/O address for parallel port 1 (LPT 1) 0Ah 10 Int 17h 2 bytes Base I/O address for parallel port 2 (LPT 2) 0Ch 12 Int 17h 2 bytes Base I/O address for parallel port 3 (LPT 3) 0Eh 14 POST 2 bytes Base I/O address for parallel port 4 (LPT 4) 10h 16 Int 11h 2 bytes Equipment Word Bits 15-14 - parallel ports installed 00b = 1 parallel port 01b = 2 parallel ports 03b = 3 parallel ports Bits 13-12 are reserved Bits 11-9 - serial ports installed 000b = none 001b = 1 serial port 002b = 2 serial ports 003b = 3 serial ports 004b = 4 serial ports Bit 8 is reserved Bit 7-6 - floppy drives installed 0b = 1 floppy drive 1b = 2 floppy drives Bits 5-4 - video mode 00b = EGA or later 01b = color 40x25 10b = color 80x25 11b = monochrome 80x25 [...]... example, with the AMI Hi-Flex BIOS, there are two more strings, displayed by pressing Ins during bootup, or any other key to create an error condition The BIOS Companion 13 1 THE BIOS Identifying Your BIOS IDENTIFYING YOUR BIOS Ac e r I D S tr in gs In the bottom left hand corner of the screen: ACR89xxx-xxx-950930-R03-B6 The first 2 characters after ACR identify the motherboard (see table) The last... manufacturer Otherwise, there can be up to three lines (from 1991 onwards) at the bottom left of the screen The first is displayed automatically, the other two can be seen by pressing the Insert key Aside from version numbers, the 1s and 0s indicate the state of the settings inside The Hi-Flex BIOS might look like this (from 1991): 41-0102-zz5123-00111111-101094-AMIS123-P Again, check the bold numbers in the. .. the order is the first floppy then the first hard drive, but you can change all that in the CMOS, to include CD ROM drives, Zip drives, etc If the floppy drive has a bootable disk in it, the BIOS will load sector 1, head 0, cylinder 0 into memory, starting at 0000:7C00h HOW OLD IS MY BIOS? If you want to check how old your BIOS is, the date is on the start-up screen, usually buried in the BIOS. .. and found in between the model name and the date: AP58 R1.00 July.21.1997 Aw a rd ID St ri ngs The date is at the front: 05/31/94-OPTI-596/546/82-2A5UIM200-00 The next bit is the chipset and the next to last the Part Number, of which characters 6 and 7 identify the manufacturer (M2) The first 5 letters (of the part number) refer to the chipset (here 2A5UI) and the last 2 (00) are the model number An... Or, in other words: aaaa-bbbb-mmddyy-Kc 14 The BIOS Companion THE BIOS Identifying Your BIOS where: aaaa bbbb mmddyy Kc BIOS type Customer Number Release date Keyboard BIOS version number If the first customer number (in bold above) is 1, 2, 8 or a letter, it is a non-AMI Taiwanese motherboard If it is 3, 4 or 5, it is from AMI 50 or 6 means a non-AMI US motherboard and 9 means an evaluation BIOS for... done) During the POST, the BIOS will look for a video BIOS between C000:000h and C780:000h, and test its checksum, after which it will allow the video BIOS to initialise itself and retake control afterwards (you will see the manufacturer's logo and various ID strings on the screen) Then the area between C800:000h to DF80:0000h will be searched in 2 K increments, looking for other ROMs They, too, will... WHEN YOU SWITCH ON The (x86) CPU is programmed to read the address space at FFFF:0000h, the last 16 bytes of memory in the first megabyte, which is just large enough to contain a jump command (JMP) that tells the processor where to find the BIOS code it is looking for (this is the bootstrap process) Next, the Power On Self Test (or POST) is run, to ensure the hardware is working (see the listings for... also use the S command to search for the word "version", although some computers, IBM and Compaq, for example, don't use version numbers In this case, the date will be near F000:FFE0 Quit debug by pressing q at the prompt The AMI WinBIOS has a normal date on the startup screen Otherwise, as you can see, you don't just get the date - many manufacturers include extras that identify the state of the chipset... communications area There are several types of BIOS because so many computers need to be IBM-compatible; they're not allowed to copy each other, for obvious reasons The BIOS worries about all the differences and presents a standard frontage to the operating system, which in turn provides a standard interface for application programs PC and motherboard manufacturers used to make their own BIOSes, and many... 82335 Memory controller BIOS Modified Flag; Incremented each time BIOS is modified from 1-9 then A-Z and reset to 1 If 0 BIOS has not yet been modified INTEL The AMI version number looks like this when used on Intel motherboards: 1.00.XX.??Y where: XX ?? Y BIOS version number Intel Motherboard model Usually 0 or 1 1.00.07.DH0 would be BIOS version 7 and a TC430HX (Tucson) motherboard AO pen I D St . kicks in. Well, in theory, anyway - there have been reports of the BIOSes flashing each other out, so later backups have become read-only. T THE BIOS BIOS Data Area 2 The BIOS Companion 1 A Flash. Function THE BIOS BIOS Data Area 12 The BIOS Companion 1 There are several types of BIOS because so many computers need to be IBM-compatible; they're not allowed to copy each other, for. bootstrap loader in the BIOS (the Basic Input/Output System). There are several in a PC, a good example being the one on the video card that controls the interface between it and the computer. However,

Ngày đăng: 02/08/2014, 03:20

Xem thêm