7-1 Chapter 7 - Memory Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring Computer Architecture and Organization Miles Murdocca and Vincent Heuring Chapter 7 – Memory 7-2 Chapter 7 - Memory Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring Chapter Contents 7.1 The Memory Hierarchy 7.2 Random-Access Memory 7.3 Memory Chip Organization 7.4 Case Study: Rambus Memory 7.5 Cache Memory 7.6 Virtual Memory 7.7 Advanced Topics 7.8 Case Study: Associative Memory in Routers 7.9 Case Study: The Intel Pentium 4 Memory System 7-3 Chapter 7 - Memory Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring The Memory Hierarchy 7-4 Chapter 7 - Memory Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring Functional Behavior of a RAM Cell Static RAM cell (a) and dynamic RAM cell (b). 7-5 Chapter 7 - Memory Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring Simplified RAM Chip Pinout 7-6 Chapter 7 - Memory Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring A Four-Word Memory with Four Bits per Word in a 2D Organization 7-7 Chapter 7 - Memory Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring A Simplified Representation of the Four-Word by Four-Bit RAM 7-8 Chapter 7 - Memory Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring 2-1/2D Organization of a 64-Word by One-Bit RAM 7-9 Chapter 7 - Memory Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring Two Four-Word by Four-Bit RAMs are Used in Creating a Four-Word by Eight-Bit RAM 7-10 Chapter 7 - Memory Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring Two Four-Word by Four-Bit RAMs Make up an Eight-Word by Four-Bit RAM [...]... Heuring © 20 07 M Murdocca and V Heuring 7- 13 Chapter 7 - Memory A ROM Stores Four Four-Bit Words Computer Architecture and Organization by M Murdocca and V Heuring © 20 07 M Murdocca and V Heuring 7- 14 Chapter 7 - Memory A Lookup Table (LUT) Implements an Eight-Bit ALU Computer Architecture and Organization by M Murdocca and V Heuring © 20 07 M Murdocca and V Heuring Chapter 7 - Memory 7- 15 Flash Memory.. . 7- 11 Chapter 7 - Memory Single-In-Line Memory Module • 256 MB dual in-line memory module organized for a 64-bit word with 16 16M × 8-bit RAM chips (eight chips on each side of the DIMM) Computer Architecture and Organization by M Murdocca and V Heuring © 20 07 M Murdocca and V Heuring 7- 12 Chapter 7 - Memory Single-InLine Memory Module • Schematic diagram of 256 MB dual in-line memory module... 20 07 M Murdocca and V Heuring Chapter 7 - Memory 7- 26 Direct Mapping Area Allocation • Area allocation for direct mapping scheme based on bits stored: Computer Architecture and Organization by M Murdocca and V Heuring © 20 07 M Murdocca and V Heuring 7- 27 Chapter 7 - Memory A Set Associative Mapping Scheme for a Cache Memory Computer Architecture and Organization by M Murdocca and V Heuring © 20 07 M... has four 16-word slots, a hit time of 80 ns, and a miss time of 2500 ns Load-through is used The cache is initially empty Computer Architecture and Organization by M Murdocca and V Heuring © 20 07 M Murdocca and V Heuring 7- 33 Chapter 7 - Memory Table of Events for Example Program Computer Architecture and Organization by M Murdocca and V Heuring © 20 07 M Murdocca and V Heuring 7- 34 Chapter 7 - Memory... © 20 07 M Murdocca and V Heuring Chapter 7 - Memory 7- 29 Set Associative Mapping Area Allocation • Area allocation for set associative mapping scheme based on bits stored: Computer Architecture and Organization by M Murdocca and V Heuring © 20 07 M Murdocca and V Heuring Chapter 7 - Memory 7- 30 Cache Read and Write Policies Computer Architecture and Organization by M Murdocca and V Heuring © 20 07 M Murdocca... logical 1 state Computer Architecture and Organization by M Murdocca and V Heuring © 20 07 M Murdocca and V Heuring Chapter 7 - Memory 7- 17 Rambus Memory • Comparison of DRAM and RDRAM configurations Computer Architecture and Organization by M Murdocca and V Heuring © 20 07 M Murdocca and V Heuring Chapter 7 - Memory 7- 18 Rambus Memory • Rambus technology on the Nintendo 64 motherboard (left) enables cost... and V Heuring © 20 07 M Murdocca and V Heuring Chapter 7 - Memory 7- 31 Hit Ratios and Effective Access Times • Hit ratio and effective access time for single level cache: • Hit ratios and effective access time for multi-level cache: Computer Architecture and Organization by M Murdocca and V Heuring © 20 07 M Murdocca and V Heuring Chapter 7 - Memory 7- 32 Direct Mapped Cache Example • Compute hit ratio... Murdocca and V Heuring 7- 20 Chapter 7 - Memory An Associative Mapping Scheme for a Cache Memory Computer Architecture and Organization by M Murdocca and V Heuring © 20 07 M Murdocca and V Heuring Chapter 7 - Memory 7- 21 Associative Mapping Example • Consider how an access to memory location (A035F014)16 is mapped to the cache for a 232 word memory The memory is divided into 2 27 blocks of 25 = 32 words... memory • Least recently used (LRU) • First-in/first-out (FIFO) • Least frequently used (LFU) • Random • Optimal (used for analysis only – look backward in time and reverseengineer the best possible strategy for a particular sequence of memory references.) Computer Architecture and Organization by M Murdocca and V Heuring © 20 07 M Murdocca and V Heuring 7- 24 Chapter 7 - Memory A Direct Mapping Scheme for... Memory Calculation of Hit Ratio and Effective Access Time for Example Program Computer Architecture and Organization by M Murdocca and V Heuring © 20 07 M Murdocca and V Heuring Chapter 7 - Memory 7- 35 Multi-level Cache Memory As an example, consider a two-level cache in which the L1 hit time is 5 ns, the L2 hit time is 20 ns, and the L2 miss time is 100 ns There are 10,000 memory references of which . Organization 7- 7 Chapter 7 - Memory Computer Architecture and Organization by M. Murdocca and V. Heuring © 20 07 M. Murdocca and V. Heuring A Simplified Representation of the Four-Word by Four-Bit RAM 7- 8 Chapter. RAM 7- 8 Chapter 7 - Memory Computer Architecture and Organization by M. Murdocca and V. Heuring © 20 07 M. Murdocca and V. Heuring 2-1 /2D Organization of a 64-Word by One-Bit RAM 7- 9 Chapter 7 - Memory Computer. Heuring Chapter 7 – Memory 7- 2 Chapter 7 - Memory Computer Architecture and Organization by M. Murdocca and V. Heuring © 20 07 M. Murdocca and V. Heuring Chapter Contents 7. 1 The Memory Hierarchy 7. 2 Random-Access