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EE 332 THIẾT BỊ VÀ mạch 09/04 II pdf

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9/3/2010 EE 332 DEVICES AND CIRCUITS II 04/09 Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen FREQUENCY ANALYSIS IN THE DESIGN OF ANALOG CIRCUITS  Intentional placed (external) capacitors    Inherent (internal) capacitors    Stray capacitors   Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen 9/3/2010 BJT AND ITS CAPACITIVE STRAY (INTERNAL) Recall diode capacitances: Depletion capacitance: Diffusion capacitance Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen FREQUENCY RESPONSE OF CE SHORTCIRCUIT / SMALL SIGNAL MODEL Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen 9/3/2010 FREQUENCY RESPONSE OF CE SHORTCIRCUIT / SMALL SIGNAL PARAMETERS Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen FREQUENCY RESPONSE OF CE SHORTCIRCUIT / GAIN Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen 9/3/2010 FREQUENCY RESPONSE OF CE SHORTCIRCUIT Rewrite this short-circuit gain to identify the pole and zero: Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen FREQUENCY RESPONSE OF CE SHORTCIRCUIT GAIN gmv f2 f1 Microelectronic Circuit Design Jaeger/Blalock fT Unity gain frequency: ©UW EE TC Chen 9/3/2010 FREQUENCY RESPONSE OF CE SHORTCIRCUIT GAIN Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen MILLER’S THEOREM Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen 9/3/2010 MILLER’S THEOREM Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen EXAMPLE VDD Estimate the poles of the circuit RD CF Vi VO RS Microelectronic Circuit Design Jaeger/Blalock M1 ©UW EE TC Chen 9/3/2010 EXAMPLE ANSWER VDD RD CF Vi VO M1 RS Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen EXAMPLE ANSWER VDD RD VO RS Vi M1 Cout Cin Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen 9/3/2010 EXAMPLE ANSWER VDD RD VO RS Vi M1 Cout Cin Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen EXAMPLE Calculate f in and f out , if gm  (150 )1 , ANSWER VDD RD  2k  , RS =1 k and C F  80 fF RD VO RS Vi M1 Cout Cin Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen 9/3/2010 FREQUENCY RESPONSE OF CE AMPLIFIER VCC R2 RC Rs C2 Q1 vo C1 vi R1 RE VBE ,on  0.7V ;VCE , sat  0.1V ;    Q1(2 N 3904)    100; F  150 ps;VA  100V ; C  pF ; C  pF  jc  je  CE  Rs  100; R1  10k ; R2  100k ;   RC  10k ; RE  1k ; RL  10k ; C  C  C  10 F ;V  12V E CC  Microelectronic Circuit Design Jaeger/Blalock      ©UW EE TC Chen FREQUENCY RESPONSE OF CE AMPLIFIER Three frequency regions: Consider medium frequencies: Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen 9/3/2010 FREQUENCY RESPONSE OF CE AMPLIFIER Step 2: SS parameters Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen FREQUENCY RESPONSE OF CE AMPLIFIER Step 3: Small signal analysis: Find source gain Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen 10 9/3/2010 FREQUENCY RESPONSE OF CE AMPLIFIER Low-Mid frequencies: include the effects of C1, C2, CE Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen FREQUENCY RESPONSE OF CE AMPLIFIER Low-Mid frequencies: include the effects of C1, C2, CE Rs C1 C2 gmv R1//R2 r ro RC RL vo vi RE CE Consider C2 and let C1, CE short Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen 11 9/3/2010 FREQUENCY RESPONSE OF CE AMPLIFIER Consider CE and let C1, C2 short Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen FREQUENCY RESPONSE OF CE AMPLIFIER Mid-high frequencies: include the effects of C and C Use Miller’s Theorem to simplify the C effects Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen 12 9/3/2010 FREQUENCY RESPONSE OF CE AMPLIFIER C vi R1//R2 Microelectronic Circuit Design Jaeger/Blalock C1 r ro gmv C2 RC RL ©UW EE TC Chen FREQUENCY RESPONSE OF CE AMPLIFIER Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen 13 9/3/2010 DESIGN PROJECT • This design project aims to utilize every single skill you have learned in EE 332 this quarter You will use your newly acquired knowledge to build a useful product that could potentially be subsequently refined and sold • Your job is to simulate an audio amplifier that can take the input from a CD player or portable music player and amplify the signal to drive a loudspeaker Your design can utilize any passive electronic components, discrete BJT’s or/and MOSFET’s (array chips are okay too) Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen 27 ©UW EE TC Chen 28 DESIGN PROJECT • Input signal specifications: – Signal voltage: 100mV pkpk (min) – 5.6V pkpk (max) – Signal source resistance 50 Ω • Equipment available for testing: – Software: PSPICE, HSPICE etc • Minimum Design Specifications of the amplifier: – – – – – Output power: 0.5W (minimum) Load Impedance (speaker): 8Ω Unity Gain Bandwidth: 20Hz – 20 kHz (-3dB) Idling power: < 1W Distortion: No distortion Microelectronic Circuit Design Jaeger/Blalock 14 9/3/2010 DESIGN PROJECT • Design Description: • A skeleton description of what your design may look like is as follows: • Your amplifier will take a small signal input from a music player, and then presumably send it into a gain stage to meet the gain requirements for the design As you have learned, we will need a specially designed output stage to drive a speaker resistance of ohms • The first is to ease requirements for simply meeting specifications, while leaving SIGNIFICANT room for optimization Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen 29 DESIGN PROJECT • Design Decision Justification: • There is no specific topology that you should follow, the method is open-ended and you are free to explore any resources With this in mind, the decisions and tradeoffs you make in your design will be critical in determining the overall quality of your project, and thus will play a significant role in the final grade Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen 30 15 9/3/2010 DESIGN PROJECT • Design Decision Justification: • You must justify all blocks in your design Why did you implement a given output stage? Which component did you use and why? It is encouraged to meet specifications while looking to optimize in areas performance (output power or bandwidth) This is a great opportunity to design something that is truly yours, so use it that way • Timeline: • I anticipate that this will take about 12 hours each person of the group to complete, Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen 31 ©UW EE TC Chen 32 DESIGN PROJECT • Project Report Requirements • Introduction – Briefly explain the objective of the project • Architecture Design – – – – Design specifications Block Diagrams Discussion on the chosen architecture Trade offs • Circuit Design – Schematics – Design equations and calculations – Simulation results Microelectronic Circuit Design Jaeger/Blalock 16 9/3/2010 DESIGN PROJECT • Project Report Requirements • Results • Maximum Output Power – What is the largest Vpk-pk on output that is not distorted/clipping and greater than or equal to 5W while achieving -3dB bandwidth of 20Hz20KHz? • Idling power DC power used with no input • Grading: • Report: Functionality: 40%; Justification: 60% Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen 33 17 ... Jaeger/Blalock ©UW EE TC Chen MILLER’S THEOREM Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen 9/3/2010 MILLER’S THEOREM Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen EXAMPLE... Jaeger/Blalock      ©UW EE TC Chen FREQUENCY RESPONSE OF CE AMPLIFIER Three frequency regions: Consider medium frequencies: Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen 9/3/2010 FREQUENCY... Microelectronic Circuit Design Jaeger/Blalock ©UW EE TC Chen 13 9/3/2010 DESIGN PROJECT • This design project aims to utilize every single skill you have learned in EE 332 this quarter You will use your newly

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