esd in silicon integrated circuits

ESD in Silicon Integrated Circuits, 2nd Edition Ajith Amerasekera, Charvaka Duvvury Copyright c  2002 John Wiley & Sons, Ltd ISB N s : 0-471-49871-8 (Hardback); 0-470-84605-4 (Electronic) ESD in Silicon Integrated Circuits Second Edition ESD in Silicon Integrated Circuits Second Edition Ajith Amerasekera Charvaka Duvvury Texas Instruments, Inc., USA With Warren Anderson Compaq Computer Corporation, USA Horst Gieser Fraunhofer Institute for Reliability and Microintegration IZM ATIS, Germany Sridhar Ramaswamy Texas Instruments, Inc., USA Copyright c  2002 by John Wiley & Sons, Ltd., Baffins Lane, Chichester, West Sussex PO 19 1UD, England Phone (+44) 1243 779777 e-mail (for orders and customer service enquiries): cs-books@wiley.co.uk Visit our Home Page on http://www.wileyeurope.com or http://www.wiley.com All Rights Reserved. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning or otherwise, except under the terms of the Copyright, Designs and Patents Act 1988 or under the terms of a license issued by the Copyright Licensing Agency Ltd., 90 Tottenham Court Road, London W1P 0LP, UK without the permission in writing of the Publisher. Requests to the Publisher should be addressed to the Permissions Department, John Wiley & Sons, Ltd., Baffins Lane, Chichester, West Sussex PO 19 1UD, England, or emailed to permreq@wiley.co.uk, or faxed to (+44) 1243 770571. Other Wiley Editorial Offices John Wiley & Sons, Inc., 605 Third Avenue, New York, NY 10158-0012, USA Jossey-Bass, 989 Market Street, San Francisco, CA 94103-1741, USA WILEY-VCH Verlag GmbH, Pappelallee 3, D-69469 Weinheim, Germany John Wiley & Sons Australia, Ltd., 33 Park Road, Milton, Queensland 4064, Australia John Wiley & Sons (Asia) Pte Ltd., 2 Clementi Loop #02-01, Jin Xing Distripark, Singapore 129809 John Wiley & Sons Canada, Ltd., 22 Worcester Road, Etobicoke, Ontario, Canada M9W 1L1 British Library Cataloguing in Publication Data A catalogue record for this book is available from the British Library ISBN 0 470 49871 8 Typeset in 10/12pt Times by Laserwords Private Limited, Chennai, India. Printed and bound in Great Britain by Antony Rowe Ltd., Chippenham, Wiltshire. This book is printed on acid-free paper responsibly manufactured from sustainable forestry in which at least two trees are planted for each one used for paper production. Contents Preface ix 1 Introduction 1 1.1 Background 1 1.2 The ESD Problem 3 1.3 Protecting Against ESD 4 1.4 Outline of the Book 4 Bibliography 7 2 ESD Phenomenon 8 2.1 Introduction 8 2.2 Electrostatic Voltage 9 2.3 Discharge 11 2.4 ESD Stress Models 12 Bibliography 15 3 Test Methods 17 3.1 Introduction 17 3.2 Human Body Model (HBM) 18 3.3 Machine Model (MM) 27 3.4 Charged Device Model (CDM) 28 3.5 Socket Device Model (SDM) 40 3.6 Metrology, Calibration, Verification 42 3.7 Transmission Line Pulsing (TLP) 47 3.8 Failure Criteria 58 3.9 Summary 60 Bibliography 61 4 Physics and Operation of ESD Protection Circuit Elements 68 4.1 Introduction 68 4.2 Resistors 68 4.3 Diodes 70 vi CONTENTS 4.4 Transistor Operation 77 4.5 Transistor Operation under ESD Conditions 85 4.6 Electrothermal Effects 95 4.7 SCR Operation 98 4.8 Conclusion 101 Bibliography 102 5 ESD Protection Circuit Design Concepts and Strategy 105 5.1 The Qualities of Good ESD Protection 106 5.2 ESD Protection Design Methods 109 5.3 Selecting an ESD Strategy 123 5.4 Summary 124 Bibliography 124 6 Design and Layout Requirements 126 6.1 Introduction 126 6.2 Thick Field Device 127 6.3 nMOS Transistors (FPDs) 132 6.4 Gate-Coupled nMOS (GCNMOS) 138 6.5 Gate Driven nMOS (GDNMOS) 149 6.6 SCR Protection Device 150 6.7 ESD Protection Design Synthesis 155 6.8 Total Input Protection 164 6.9 ESD Protection Using Diode-Based Devices 172 6.10 Power Supply C lamps 176 6.11 Bipolar and BiCMOS Protection Circuits 179 6.12 Summary 183 Bibliography 184 7 Advanced Protection Design 188 7.1 Introduction 188 7.2 PNP-Driven nMOS (PDNMOS) 188 7.3 Substrate Triggered nMOS (STNMOS) 189 7.4 nMOS Triggered nMOS (NTNMOS) 192 7.5 ESD for Mixed-Voltage I/O 200 7.6 CDM Protection 214 7.7 SOI Technology 215 7.8 High-Voltage Transistors 216 7.9 BiCMOS Protection 218 7.10 RF Designs 219 7.11 General I/O Protection Schemes 220 7.12 Design/Layout Errors 221 7.13 Summary 223 Bibliography 224 CONTENTS vii 8 Failure Modes, Reliability Issues, and Case Studies 228 8.1 Introduction 228 8.2 Failure Mode Analysis 229 8.3 Reliability and Performance Considerations 238 8.4 Advanced CMOS Input Protection 239 8.5 Optimizing the Input Protection Scheme 242 8.6 Designs for Special Applications 249 8.7 Process Effects on Input Protection Design 253 8.8 Total IC Chip Protection 255 8.9 Power Bus Protection 256 8.10 Internal Chip ESD Damage 258 8.11 Stress Dependent ESD Behavior 263 8.12 Failure Mode Case Studies 267 8.13 Summary 271 Bibliography 272 9 Influence of Processing on ESD 282 9.1 Introduction 282 9.2 High Current Behavior 284 9.3 Cross Section of a MOS Transistor 287 9.4 Drain-Source Implant Effects 288 9.5 p-Well Effects 293 9.6 n-Well Effects 294 9.7 Epitaxial Layers and Substrates 295 9.8 Gate Oxides 298 9.9 Silicides 300 9.10 Contacts 304 9.11 Interconnect and Metalization 305 9.12 Gate Length Dependencies 306 9.13 Silicon-on-Insulator (SOI) 310 9.14 Bipolar Transistors 312 9.15 Diodes 314 9.16 Resistors 315 9.17 Reliability Trade-Offs 316 9.18 Summary 317 Bibliography 320 10 Device Modeling of High Current Effects 326 10.1 Introduction 326 10.2 The Physics of ESD Damage 327 10.3 Thermal (“Second”) Breakdown 330 10.4 Analytical Models Using the Heat Equation 335 10.5 Electrothermal Device Simulations 339 viii CONTENTS 10.6 Conclusion 344 Bibliography 345 11 Circuit Simulation Basics, Approaches, and Applications 350 11.1 Introduction 350 11.2 Modeling the MOSFET 351 11.3 Modeling Bipolar Junction Transistors 367 11.4 Modeling Diffusion Resistors 371 11.5 Modeling Protection Diodes 375 11.6 Simulation of Protection Circuits 376 11.7 Electrothermal Circuit Simulations 382 11.8 Conclusion 385 Bibliography 389 12 Conclusion 394 12.1 Long-Term Relevance of ESD In ICs 394 12.2 State-of-the-Art for ESD Protection 395 12.3 Current Limitations 396 12.4 Future Issues 398 Bibliography 399 Index 401 Preface In the seven years since the first edition of this book was completed, Electrostatic Discharge (ESD) phenomena in integrated circuits (IC) continues to be important as technologies shrink and the speed and size of the chips increases. The phenom- ena related to ESD events in semiconductor devices take place outside the realm of normal device operation. Hence, the physics governing this behavior are not typ- ically found in general textbooks on semiconductors. Similarly the circuit design issues involve nonstandard approaches that are not covered in general books on electronic design. There has been a large amount of work done in the areas of ESD circuit design and the physics involved, most of which has been published in a number of papers and conference proceedings. This book covers the state- of-the-art in circuit design for ESD prevention as well as the device physics, test methods, and characterization. We also include case studies showing examples of approaches to solving ESD design problems. For the second edition, we have completely revised a number of chapters and brought other chapters up to date with the latest learning. The last seven years have seen many developments in the understanding of ESD phenomenon and the issues related to circuit and transistor design, as well as to modeling and simulation. The book is intended for those working in the field of IC circuit design and tran- sistor device design. In addition, the basics presented in this book should also appeal to graduate students in the field of semiconductor reliability and device/circuit mod- eling. As the problems associated with ESD become significant in the IC industry the demand for graduates with a basic knowledge of ESD phenomena also increases. We hope that this book will help students meet the demands of the IC industry in terms of understanding and approaching ESD problems in semiconductor devices. There are many companies and research institutes that have made it possible to understand and solve the majority of ESD problems in ICs. Some of the companies that have been particularly active in recent years a re Texas Instruments, Philips Semiconductors, Lucent, Rockwell, IBM, Motorola, DEC/Compaq, David Sarnoff Labs, and Intel. Research Institutes that have made significant contributions in recent years are Sandia National Labs, Clemson University, Stanford University, the University of California in B erkeley, the University of Western Ontario in Canada, the University of Illinois at Urbana-Champain, Twente U niversity in The Netherlands, the Technical University of Munich and the Fraunhofer Institute both in Germany, and IMEC in Belgium. We have many people to thank for their contributions to our personal knowledge and understanding in this area. We would particularly like to thank Robert Rountree, x PREFACE Thomas Polgreen, and Amitava Chatterjee for their contributions both at the circuit design and at the device level. Ping Yang and William Hunter have provided excellent technical guidance during the evolution of the work on ESD, and without their management support this work would not have been undertaken in the first place. Many of our colleagues here at Texas Instruments have done the groundwork, which has helped us expand our understanding in this area. We are especially grateful for the contributions of Kuen-Long Chen, David Scott, Vikas Gupta, Mike Chaine, Karthik Vasanth, Vijay Reddy, Tom Diep, Steve Marum, and Julian Chen, in this respect. In the area of device physics and modeling, the contributions of Mi-Chang Chang, Kartikeya Mayaram, Jue-Hsien Chern and Jerold Seitchik have been invaluable. We have had the pleasure of working closely with many academic institutions, and we thank Professors Henry Domingos at Clarkson University, Ken Goodson, Robert Dutton, Kaustav Banerjee at Stanford University, Chenming Hu at UC Berkeley, Elyse Rosenbaum and Steve Kang at University of Illinois at Urbana- Champain, and Jan Verweij, and Fred Kuper at the University of Twente, for their collaboration over the years. We greatly appreciate the significant contributions that Carlos Diaz and Sridhar Ramaswamy (University of Illinois at Urbana-Champain), Kaustav Banerjee (UC Berkeley), Xin Yi Zhang (Stanford), Sungtaek Ju (Stanford), and Gianluca Boselli (University of Twente), during their PhD studentships, have made to our understanding of the many issues related to ESD in silicon integrated circuits. Ajith Amerasekera Charvaka Duvvury Dallas, November 2001. ESD in Silicon Integrated Circuits, 2nd Edition Ajith Amerasekera, Charvaka Duvvury Copyright c  2002 John Wiley & Sons, Ltd ISBNs:0-471-49871-8(Hardback);0-470-84605-4(Electronic) Index Abrupt junction 76, 131, 133, 239, 249, 252, 253, 288, 289, 291, 292, 317 Adiabatic 336, 338 AEC 22, 24, 28, 29 Aluminium-silicon diffusions 304, 334 Aluminum-silicon 304 eutectic temperature 334 Analytical CDM-testing 38 Analytical models 4, 335, 336, 339, 341, 344, 375 Anode 73, 76, 98–100, 150, 151, 157, 164, 218, 240, 297, 314, 315, 319, 373, 374 to cathode spacing 99 Applications 6, 25, 35, 38, 39, 44, 45, 47, 57, 85, 98, 136, 138, 143, 144, 146, 153, 155–157, 162, 170, 171, 179, 183, 189, 192, 215, 216, 218–220, 223, 238, 247, 249, 326, 350, 376, 395–397, 399 automotive 247 industrial 247 special 238 Arsenic implantation 290 ASIC 377, 381 cell 381, 382 library 377 Avalanche 11, 12, 70, 71, 73–76, 81, 83–86, 88–90, 95–97, 100, 101, 123, 131, 133, 138, 139, 141, 150, 152, 157–162, 164, 166, 170, 171, 180, 236, 241, 242, 250, 282, 284, 285, 287, 288, 290, 298, 299, 311, 313, 315, 327, 329, 333, 334, 339, 340, 343–345, 350, 351, 353–357, 359, 364, 367–370, 373, 375, 382, 383, 389 conditions 83, 85 generated current 11 generation 11 multiplication 12 Avalanche breakdown 70, 71, 73, 75, 76, 81, 89, 90, 100, 131, 133, 138, 139, 141, 150, 157, 158, 160, 162, 236, 241, 242, 250, 288, 290, 298, 299, 329, 333, 350, 351, 354, 357, 359, 364, 368, 369, 373, 375, 383, 389 region 351 voltage 71, 75, 76, 90, 100, 133, 139, 141, 157, 160, 236, 250, 290, 298, 354, 357, 359, 364 Background capacitance 23, 34 Bakeable leakage current 238 Ballast resistance 96, 283 Barrier metal 304 Base charge factor 359 Base current 77–79, 84, 86, 89, 95, 120, 175, 207, 212, 282, 284, 285, 292, 310, 327, 344, 355, 369, 370, 376, 386 Base transit time 21, 57, 80, 89, 314, 363 Base transport factor 79, 352, 356 Base-emitter resistance 219 Basic input protection scheme 156 BiCMOS 14, 95, 126, 157, 179–184, 188, 218, 219, 223, 327, 368, 371, 383, 396 BiCMOS protection circuits 184 Bipolar 4, 24, 48, 55, 68, 77, 78, 80, 83–86, 88–92, 95, 96, 98, 101, 126–129, 131, 133, 139, 144, 155, 179–182, 184, 202, 208, 209, 215, 216, 218, 219, 223, 250, 251, 257, 282–288, 292, 295, 299, 301–303, 307, 310–315, 317–319, 327–329, 344, 350–358, 361, 363, 367–369, 371, 382, 383, 385, 386, 389, 396 collector current in the npn 77 efficiency 129 gain degradation 94, 95, 366 lateral 88, 89, 127, 284, 285, 355 [...]... Renaud, ESD in semiconductor wafer processing”, in Proceedings of the 7th EOS /ESD Symposium, pp 6–9, 1985 [Ghandhi77] S.K Ghandhi, in Semiconductor Power Devices, John Wiley & Sons, New York, 1977 [Lindholm85] A.W Lindholm, “A case history of an ESD problem”, in Proceedings of the 7th EOS /ESD Symposium, pp 10–14, 1985 [McAteer79] O.J McAteer, “An effective ESD awareness training program”, in Proceedings... Validation of the Field Induced ESD Model”, in Proc 8th EOS /ESD Symposium, ESD Association, Rome, NY, USA, pp 224–231, 1986 [ESDA-Glossary94] ESD Association, ESD ADV1.0-1994: Glossary of Terms, 1994 [ESDA-TLU] ESD- Association WG5.4, ESD SP5.4: Standard Practice for LatchUp Stressing CMOS/BiCMOS ICs Using Transient Stimulation, Work in Progress 2001 [ESDA-Tribo95] ESD- Association, ESD ADV11.2-1995: Triboelectric... scheme 127, 154–156, 159, 182, 238, 242, 247, 253, 254 Input/output buffer 198, 199, 351 Interconnect parasitics 379 Interconnects 41, 305, 318, 389 INDEX Internal chip ESD damage 256, 257 Internal chip layout 256 Interval between pulses 25 Intrinsic base current 327 Intrinsic carrier concentration, ni 69, 78, 331 Intrinsic temperature, Ti 331 Ionic charging 9, 10 Isolation resistor 127, 145, 148, 152, 156,... the different aspects of ESD and the protection measures in [ESDA-Glossary94], edited and published by the ESD Association After this brief introduction into the charging and discharging mechanisms leading to ESD stress models for integrated circuits, the following Chapter 3 Test Methods will detail how the ESD stress models have been implemented in testers for qualification, and discuss techniques for... future ESD requirements and directions for further work in this area BIBLIOGRAPHY [Amerasekera92] A Amerasekera and J Verwey, ESD in integrated circuits , in Qual Rel Eng Int., 8, 259–272, 1992 [Bhar83] T.N Bhar and E.J McMahon, in Electrostatic Discharge Control , Hayden, New Jersey, 1983 [Dangelmayer85] G.T Dangelmayer and E.S Jesby, “Employee training For successful ESD control”, in Proceedings of... Discharges”, in Proc 14th EOS /ESD Symposium, ESD Association, Rome, NY, USA, pp 68–75, 1992 [Lin94] D.L Lin and M.-C Jon, “Off-Chip Protection: Shunting of ESD Current by Metal Fingers on Integrated Circuits and Printed Circuit Boards”, in Proc 16th EOS /ESD Symposium, ESD Association, Rome, NY, USA, pp 279–285, 1994 [Moss82] R.Y Moss, “Caution — Electrostatic Discharge at Work”, in IEEE Trans Comp Hybr and... and layout for ESD robustness require particular guidelines that have evolved through years of experimental work in this field The same is true for test methods and characterization In this book we have INTRODUCTION 5 attempted to present coverage of all these aspects, which would enable the reader to gain a broad understanding of ESD in ICs and the main issues involved in improving ESD performance... scaled or transferred with minimum impact to the ESD performance The purpose of this book is to provide an introduction to the basic mechanisms involved in ESD events, the physical processes taking place in the semiconductor, and the design and layout approaches to obtain good ESD performance The importance of building -in reliability demands design approaches that include ESD robustness as part of the... provide a basis in this field for circuit design and reliability engineers as well as process and device design engineers who have to deal with ESD in integrated circuits 1.2 THE ESD PROBLEM ESD is the transient discharge of static charge, which can arise from human handling or contact with machines The mathematics of the generation of static electricity has been presented in some detail in previous works... 1st EOS /ESD Symposium, pp 1–3, 1979 [McAteer82] O.J McAteer, R.E Twist and R.C Walker, “Latent ESD failures”, in Proceedings of the 4th EOS /ESD Symposium, pp 41–48, 1982 [Merrill93] R Merrill and E Issaq, ESD design methodology”, in Proceedings of the 15th EOS /ESD Symposium, pp 233–237, 1993 [Wagner93] R.G Wagner, J Soden and C.F Hawkins, “Extent and cost of EOS /ESD damage in an IC manufacturing process”, . 0-470-84605-4 (Electronic) ESD in Silicon Integrated Circuits Second Edition ESD in Silicon Integrated Circuits Second Edition Ajith Amerasekera Charvaka Duvvury Texas Instruments, Inc., USA With Warren. have made to our understanding of the many issues related to ESD in silicon integrated circuits. Ajith Amerasekera Charvaka Duvvury Dallas, November 2001. ESD in Silicon Integrated Circuits, 2nd Edition Ajith. 398 Bibliography 399 Index 401 Preface In the seven years since the first edition of this book was completed, Electrostatic Discharge (ESD) phenomena in integrated circuits (IC) continues to be important as