Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C040 Finals Page 862 29-9-2008 #29 862 Handbook of Algorithms for Physical Design Automation [KL70] B. W.Kernighan and S. Lin, An efficient heuristic procedure for partitioning graphs, Bell System Technical Journal 49: pp. 291–307, 1970. [KR92] A. B. Kahng and G. Robins, A new class of iterative Steiner tree heuristics with good perfor- mance, IEEE Transactions on Computer-Aided Design of Integrated Cir cuits and Systems 11: 893–902, July 1992. [KRW05] A. B. Kahng, S. Reda, and Q. Wang, A Place: A generic analytical placement framework, Pr oceedings of the International Symposium on Physical Design, pp. 233–235, 2005. [KSJA91] J. M. Kleinhans, G. Sigl, F. M. Johannes, and K. J. Antreich, GORDIAN: VLSI placement by quadratic programming and slicing optimization, IEEE Tr ansactions on Computer-Aided Design of Integrated Circuits and Systems 10: 356–365, March 1991. [MH00] M. Murakami and N. Honda, A maze-running algorithm using fuzzy set theory for routing methods of printed circuit boards, Proceedings of the Ninth IEEE International Conference on Fuzzy Systems, Vol. 2, pp. 985–988, 2000. [NWZ02] B. K. Nielsen, P. Winter , and M. Zachariasen, An exact algorithm for the uniformly-oriented Steiner tree problem, Proceedings of the 10th European Symposium on Algorithms (Lecture Notes in Computer Science 2461), pp. 760–772, 2002. [SFH+91] Y. Sekiyama, Y. Fujihara, T. Hayashi, M. Seki, J. Kusuhara, K. Iijima, M. Takakura, and K. Fukatani, Timing-oriented routers for PCB layout design of high-performance computers, Pr oceedings of the IEEE International Conference on Computer-Aided Design, pp. 332–335, 1991. [SDJ91] G. Sigl, K. Doll, and F. M. Johannes, Analytical placement: A linear or quadratic objective function? Proceedings of the ACM/IEEE Design Automation Conference, pp. 57–62, 1991. [SK89] P. R. Suaris and G. Kedem, A quadrisection-based place and route scheme for standard cells, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 8: 234–244, March 1989. [SKK+96] R. Scepanovic, J. S. Koford, V. Kudryavsfe v, A . Andreev, S. Aleshin, and A . Podkolzin, Micro- electronic integrated circuit structure and method using three directional interconect routing based o n hexagonal geometry, Patent No. 5,578,840, November 26, 1996, LSI Logic. [SN02] N.ShenoyandW.Nicholls,An efficientrouting database, P roceedings of the ACM/IEEE Design Automation Conference, pp. 590–595, 2002. [SW92] M. Sarrafzadeh and C. K. Wong, Hierarchical Steiner tree construction in uniform orientations, IEEE Tr ansactions on Computer-Aided Design of Integr ated Circuits and Systems 11: 1095– 1103, September 1992. [T02] S. Te ig, The X architecture: Not your father’s diagonal wiring, Proceedings of the International Workshop on System-level I n terconnect Prediction, 2002, pp. 33–37. [TC04] S. Teig and A. C aldwell, U. S. Patents 6,829,757. [TC05] S. Teig and A. Caldwell, U. S. Patents 6, 877,146; 6, 886,149; 6,889,371; 6, 889,372; 6,898,773; 6,928,633; 6,931,608; 6,931,615; 6,948,144; 6,951,005; 6,951,006; 6,957,408; 6,957,409; 6,978,432. [TC06] S. Teig and A. Caldwell, U . S. Patents 6,986,117; 7,000,209. [TT98] T. Takahashi and N. Shibuya, Development of a support tool for PCB design with EMC con- straint: Reflection and crosstalk noise reduction inmanual design, Proceedings of the A sia-South Pacific Design Automation Conference, pp. 397–402, 1998. [V97] J. Vygen, Algorithms for large-scale flat placement, Proceedings of the ACM/IEEE Design Automation Conference, pp. 746–751, 1997. [WWZ00] D. M. Warme, P. Winter, and M. Zachariasen, Exact algorithms for plane Steiner tree problems: A computational study, in Advances in Steiner T rees , eds. D. Z. Du, J. M. Smith, and J. H. Rubinstein, pp. 81–116, Kluwer Academic Publishers, Boston, MA, 2000. [X01] www.xinitiative.org. [YWES00] X. Yang, M. Wang, K. Eguro, and M. Sarrafzadeh, A snap-on placement tool, Proceedings of the International Symposium on P hysical Design, pp. 153–158, 2000. [ZZJ+05] Q. Zhu, H. Zhou, T. Jing, X. -L. Hong, and Y. Yang, Spanning graph-based nonrectilinear Steiner tree algorithms, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24: 1066–1075, July 2005. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_S009 Finals Page 863 24-9-2008 #2 Part IX Designing Large Global Nets Alpert/Handbook of Algorithms for Physical Design Automation AU7242_S009 Finals Page 864 24-9-2008 #3 Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C041 Finals Page 865 24-9-2008 #2 41 Inductance Effects in Global Nets Yehea I. Ismail CONTENTS 41.1 Historical Perspective 865 41.2 Importance of Inductance in Current and Future Technologies 866 41.3 Extraction and Physical Representations of Inductance 869 41.4 Effects o f Inductance 871 41.4.1 Effects of Inductance on Delay and Signal Rise Time 872 41.4.2 Effects of Inductance on Power Dissipation 873 41.4.3 Effects of Inductive Coupling on Delay Uncertainty 873 41.5 Inductive Noise 874 41.6 Requirements on CAD Tools and Their Performance 876 41.7 Physical Design Including Inductance Effects 877 References 878 41.1 HISTORICAL PERSPECTIVE Historically, the gate parasitic impedances have been much larger than interconnect parasitic imped- ances because the gate geometries (the width and length) were quite large (about 5 µm was a typical minimum feature size in 1980). Thus, interconnect parasitic impedances have historically been neglected and the interconnect was modeled a s a short circuit. With the scalin g of the minimum gate feature size, interconnect capacitances have become comparable to the gate capacitance, requiring the interconnect to be modeled as a single lumped capacitance that is added to the gate capacitance. With th is interconnect model, new design techniques emerged to drive large capacitive loads associ- ated with long global interconnects and large interconnect trees with high fanout. Cascaded tapered buffers are used to minimize the propagation delay of CMOS gates driving these large capacitive loads (e.g., [1,2]). With increasing device densities per unit area, the cross-sectional area of interconnects has been reduced to provide more interconnect per unit area. Also, the improved yield of CMOS fabrica- tion processes permits manufacturing larger chips with higher reliability. Thus, the global wires connecting modules across an IC have increased in length. Both the decreased cross-sectional area and the increased wirelength have caused the global wire resistances to dramatically increase. The interconnect model now includes the resistance of the interconnect. Including resistance in the inter- connect model dramatically changed the design and analysis of integrated circuits, e.g., [3–5]. With a short circuit or a capacitive interconnect model, the interconnect could be treated as a single node. However, by including the series resistance, the interconnect is composed of multiple nodes, each node having a different voltage waveform. This characteristic has g reatly complicated the analysis of circuits with resistive interconnect. Completely new problems and design techniques have emerged due to the transition from a capacitive to an RC model such as RC tree analysis techniques, clock skew problems, repeater insertion techniques, power consumption estimation, model order reduction 865 Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C041 Finals Page 866 24-9-2008 #3 866 Handbook of Algorithms for Physical Design Automation techniques, and IR drops in the power supply, to name a few. Almost every aspect of the design and analysis of integrated circuits was affected by the new interconnect model. The rest of this chapter su mmarizes th e importance, effects, and issues involved in a tra nsition from an RC interconnect model to an RLC model, which includes the inductance of the interconnect. This transition has the potential to change all aspects of the design and analysis of integrated circuits in analogy to the transition from acapacitivetoan RC interconnect model. However,unlike the transition from a capacitive to an RC model, which only resulted into undesirable effects, the increasing inductance effects can have several desirable consequences, which are pointed out later. 41.2 IMPORTANCE OF INDUCTANCE IN CURRENT AND FUTURE TECHNOLOGIES On-chip inductance has currently become more important with faster on-chip rise times and wider wires. Wide wires are frequently encountered in clock distribution networks and in upper metal layers. These wiresarelow-resistance lines that can exhibit significant inductive effects. Furthermore, performance requirements are pushing the introduction of new materials such as copper interconnect for low-resistance interconnect and new dielectrics to reduce the interconnect capacitance. These technological advances increase the importance of inductance. On-chip inductance can cause significant errors in current deep-submicron technologies. For example, three sets of simulation ∗ results are presented based on IBM’s 0.1-µm technology to illustrate the importance of on-chip self and mutual inductances. The first example is a four-bit coupled bus (Table 41.1). The second example is a tree coupled with two lines (Table 41.2). And the third example is a pair of lines coupled with each other (Table 41.3). In all three examples, simulations are done for three cases. In case I, self and mutual inductances are not included. That is, signal lines are considered as standard RC lines with coupling capacitances only. In case II, self-inductance is included, and lines are considered as RLC lines with coupling capacitan ce, but no coupling inductance. In case III, both self and mutual inductances are included and lines are considered as RLC lineswithcoupling capacitance and mutual inductance. Results showthat the error owing to neglectinginductance can be more than 100 percent for the delay calculation and 70 percent in the rise time. What makes these errors even more serious is that neglecting inductance and using an RC model always results in underestimating the propagation delay (e.g., see Figure 41.1). Thus, VLSI circuits designed using an RC interconnect model may not satisfy the assigned performance targets d espite a worst-case analysis being applied in the circuit design process. In general, there are two factors contro lling the error between an RC model and an RLC model. These two factors are the damping factor of an RLC line and the ratio between the input signal rise time to the time of flight of signals across the line [7]. The damping factor of an RLC line is given by ξ = Rl 2 C L (41.1) where R, L,andC are theresistance,inductance, andcapacitance perunitlengthoftheline, respectively l is the length of the line The damping factor of the line represents the degree of attenuation the wave suffers as it propagates a distance equal to the length of the line. As this attenuation increases, the effects of the reflections decrease and the RC model becomes more accurate. Note that the damping factor is proportional to ∗ Circuit simulations in this section a re either performed using HSPICE or IBM’s circuit simulation tool AS/X [6]. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C041 Finals Page 867 24-9-2008 #4 Inductance Effects in Global Nets 867 TABLE 41.1 Circuit Simulation of a 4-Bit Bus All Lines Are Switching in the Same Direction Case Deviation (percent) Bus I II III I–III II–III Delay (ps) 29.32 44.2 58.67 100 33 Rise time (ps) 84.59 25.5 26.81 68.3 5.14 Overshoot (%) 0 10.3 23.79 — 126 Time of overshoot — 115 155.2 — 35.3 TABLE 41.2 Circuit Simulation of a Coupled Tree Network All Lines Are Switching in the Same Direction Case Deviation (percent) Tree I II III I–III II–III Delay (ps) 30.46 43.59 51.98 71.5 18.5 Rise time (ps) 87.1 43.36 37.29 58.6 13.4 Overshoot (%) 0 7.2 15 — 108 Time of overshoot — 113.4 134 — 18.2 TABLE 41.3 Circuit Simulation of a Pair of Coupled Lines All Lines Are Switching in the Same Direction Case Deviation (percent) Line I II III I–III II–III Delay (ps) 63.12 74.13 83.64 32.53 12.83 Rise time (ps) 147.8 85. 36 49 67 43 Overshoot (%) 0 0.74 6.2 — 737 Time of overshoot — 269 221.5 — 17.69 V DD RC RC + self-inductance + mutual inductance RC + self-inductance FIGURE 41.1 Signal behavior on one net of a 4-bit bus. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C041 Finals Page 868 24-9-2008 #5 868 Handbook of Algorithms for Physical Design Automation the length of the line and thus very long lines will exhibit less inductance effects. Alternatively, the damping factor can be expressed as ξ = R t C t 2 √ L t C t = τ RC 2τ LC (41.2) where R t , L t ,andC t are the total resistance, inductance, and capacitance of the line, respectively τ RC and τ LC are the RC and LC time constants of the line This relatio n illustrates the fight between the RC and LC time constants of the line. A reduction in the RC time constant results in a direct increase in the inductance effects exhibited by the line. Note that many of the technological advancements that have been achieved or are still in development target reducing the RC time constant. Examples are copper interconnect, dielectrics with lower ε r , and superconductiveinterconnects. Also, many of the design methodologies used to reduce the delay of critical lines concentrates mainly on reducing the RC time c onstant of the line, such as using wider wires, wider drivers, and repeater insertion. In the lim it, if the RC time constant of a line is sufficiently reduced, the line will behave as a lossless transmission line and signals can be transmitted across the line with the speed of light. The other factor determining inductance effects is the ratio between the input signal rise time to the time of flight of signals across the line and is given by t r 2l √ LC (41.3) where t r is the rise time of the input signal. As this ratio increases, the line can be more accurately modeled as an RC line. Note that in this case the relation implies that shorter lines will suffer less inductance effects mainly b ecause the rise time o f the input signal will override the LC time constant. Hence, there is a range of the length of the interconnect for which inductance effects are significant with very short and very long lines suffering no inductance effects [7]. Note that the rise times of input signals to the interconnect are becoming faster all the time with technology scaling, increasing inductance effects in future technologies. Even if some techniques can be applied today to reduce the effect of inductance allowing the use of the well-developed RC-based CAD tools, inductance effects will be very hard to suppress or ignore in future technologies and CAD tools have to be modified to include the effect of inductance. Equivalent figures of merit for trees were developed in Ref. [8] to characterize the importance of on-chip inductance. These expressions at node i of a tree are given by ζ i = 1 2 k C k R ik k C k L ik (41.4) and t r /2 k C k L ik (41.5) respectively,where R ik (L ik ) is the common resistance (inductance)from the input of the tree to nodes i and k and k runs over all the capacitances in the tree. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C041 Finals Page 869 24-9-2008 #6 Inductance Effects in Global Nets 869 41.3 EXTRACTION AND PHYSICAL REPRESENTATIONS OF INDUCTANCE Each interconnectline has an associated self-inductanceand an associated mutual inductanceto other lines in the circu it. Unlike the resistance and capacitance of interconnect lines, both self and mutual inductances are loop quantities, and they can be determined only if the whole current loop is known; i.e., the exact path in which the current returns to the sourceis known. The self-inductance of a loop is defined as the flux linked through the loop because of the variation in the current flowing in the loop divided by the value of the current. The current loop also has corresponding coupling inductances that couple the current loop to surrounding current loops. The coupling inductance is the flux caused by an aggressor loop linked to a given loop divided by the value of the aggressor current [9]. The current return path is frequency dependent. At low frequency, the inductive impedance (ωL) is less than the resistive impedance (R). Hence, the current tries to minimize the interconnect impedance and thus tries to minimize the interconnect resistance. This causes the current to use as many returns as possible to have parallel resistances, as shown in Figure 41.2 [9]. However, at high frequency ωL > R and the current tries to min imize interconnect imp e dance by minimizing the loop inductance. This causes the current to use the closest possible return path to form the smallest possible loop inductance, as shown in Figure 41.2 [9]. The current would be confined to the nearest possible return only at ultra-high frequencies (higher than 20 GHz) [10]. Therefore, at current clock frequencies, current can spread into a number o f possible current return paths. This behavior makes the extraction of inductance a nontrivial task as it tremendously increases the number of surrounding interconnects that have to be considered. The distribution of the current into different wires as a function of frequency is typically referred to as proximity effects, while the confinement of current in parts of an interconnect, as shown below, is referred to as skin effect. To limit the complexity of the problem, the inductance can be approximated [11] by assuming that the current return path is limited to the nearest power or ground line. Other approaches such as in Ref. [12] incrementally improve the accuracy by adding more ground lines to the return path until the extracted inductance is accurate enough. One way to go around the prerequisite of knowing the actual current return paths beforehand is by using the three-dimensional (3D) field solver. A common approach that is used by 3D solvers is to extract inductance by applying a finite difference or finite element method to the governing Maxwell equations in differential form. Such an approach generates a global 3D mesh for all parts of analyzed structure and for surrounding external space. This causes the number of unknowns to increase significantly, and thus a very large linear system can be generated. Solving this large linear system requires excessive memory and consumes long CPU time, which makes inductance extraction of complex 3D structures using finite element or finite difference methods impractical. The other approach used in inductance extraction employs the partial element equivalent circuit method (PEEC) [13,14]. Using PEEC, only the volume of the conductors needs to be discretized. High frequency GND GND GND GND GND GND GND GND GND GND GND GND Low frequency Signal Signal FIGURE 41.2 Frequency dependence of current distribution across signal and ground lines. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C041 Finals Page 870 24-9-2008 #7 870 Handbook of Algorithms for Physical Design Automation Thus, using the PEEC method produces a fewer number of unknowns than finite elements and dif- ferences. The integral formulation of the PEEC method is used in the widely known MIT inductance extraction program, FastHenry [15]. Hence, inductance extraction is a nontrivial process. However, there are two characteristics of on-chip inductance that can be exploited to simplify the extraction process of on-chip inductance. First, the sensitivity of a signal waveform to errors in the inductance values is low compared to sensitivity to errors in resistance and capacitance values, particularly the propagation delay and rise time. Second, the value of the on-chip inductance is a slow varying function of the width of the wire and the geometry of the surrounding wires [16]. The first characteristic can be explained by the fact that inductance only appears under a square root function in a waveform or timing expression characterizing a signal. The reason for this square root dependence is physical because an LC constant has the dimensions of time squared, where L and C are any inductance and capacitance values in the circuit, respectively. The square root dependence can be compared to the linear dependence of the delay expressions on the resistance because any RC constant has the dimensions of time, where R is any resistance of the circuit. For example, according to the equivalent Elmore delay for RLC trees that was introduced in Ref. [17], the 50 percent delay of the signal at node i of an RLC tree is t pdi = 1.047 · k C k L ik ·e − ζ i 0.85 + 0.695 · k C k R ik (41.6) where ζ i is the damping factor at node i and is ζ i = 1 2 k C k R ik k C k L ik (41.7) Note that inductance only appears under a square root. This fact is also evident in Equations 41.8 and 41.14. As an example, circuit [6] simulations are performed for an RLC tree with no inductance (an RC model), and with all of the inductance values increased by 10, 20, and 30 percent. These simulations are depicted in Figure 41.3. Note in the simulations that using an approximate inductance estimation V o1 (u) 0.00 0.50 1.501.00 2.50 3.00 2.00 1.50 1.00 0.50 0.00 10 percent error in extracted inductance values (a) Time (ns) FIGURE 41.3 Circuit simulations of an RLC tree with the actual inductance values, with no inductance (an RC model), and with all of the inductance values increased by (a) 10 percent. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C041 Finals Page 871 24-9-2008 #8 Inductance Effects in Global Nets 871 V o1 (u ) 0.00 0.50 1.501.00 2.50 3.00 3.50 2.00 1.50 1.00 0.50 0.00 20 percent error in extracted inductance values No inductance (RC) Actual inductance values Rough inductance values (b) Time (ns) V o1 (u) 0.00 0.50 1.501.00 2.50 3.00 3.50 2.00 1.50 1.00 0.50 0.00 30 percent error in extracted inductance values (c) Time (ns) FIGURE 41.3 (continued) (b) 20 percent, and (c) 30 percent. greatly improves the accuracy of the waveform as compared to using an RC model. Even with a 3 0 percent error in the inductance values, the propagation delay differs by 9.4 percent from the actual value as compared to 51 p ercent if an RC model is used. The improvement in the rise time is even greater. The rise time differs from the actual value by 5.9 p ercent with a 30 percent error in the inductance values as compared to a 71 percent error when an RC model is used. The maximum error in the waveform shape occurs around the overshoots (Figure 41.3). However, estimating the overshoot requires less accuracy because the overshoot is usually evaluated to decide if the overshoot is within an acceptable limit. This high tolerance of the delay expressions to errors in the extracted inductance combinedwith the slow variation ofextracted inductancevalues withchangesin geometry encourage the use of simplified techniques with highercomputational efficiencyto extracttheon-chip inductance. 41.4 EFFECTS OF INDUCTANCE This section briefly discusses the effects of inductance on the performance of integrated circuits. The effects of inductance on signal delay and rise time, power consumption, and delay uncertainty are discussed. . Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C040 Finals Page 862 29-9-2008 #29 862 Handbook of Algorithms for Physical Design Automation [KL70] B. W.Kernighan. Large Global Nets Alpert /Handbook of Algorithms for Physical Design Automation AU7242_S009 Finals Page 864 24-9-2008 #3 Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C041. order reduction 865 Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C041 Finals Page 866 24-9-2008 #3 866 Handbook of Algorithms for Physical Design Automation techniques, and