Handbook of algorithms for physical design automation part 29 ppt

Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C013 Finals Page 262 24-9-2008 #7 262 Handbook of Algorithms for Physical Design Automation but again the routing is done flat. In the same spirit, many floorplanners support operations such as edit in context to enable the user to treat a hierarchical design as flat where this is beneficial, without actually flattening the design. 13.3.1 IS HIERARCHICAL DESIGN LESS EFFICIENT? It is sometimes argued that a hierarchical design is intrinsically less efficient than a flat design, in terms of area or performance. While this has some basis in practice, it is not true in theory, if arbitrary rearrangement of the hierarchy is allowed. This can be shown as follows [28]: take the result of the hypothetically more efficient flat tool or procedure. Then divide this flat design, cookie cutter style, to create a hierarchical design. This design, if fabricated, would be exactly the same as the flat design, and have exactly the same size and performance. This exact procedure is only u seful as an existence proof, because there is no point in building a hierarchical design that is exactly the same as an existing flat design. Furthermore, the cookie cutter approach will almost surely result in a completely incomprehensible hierarchy. There may be no easy way to express high-level constraints on the block pins; indeed even the pins may be split into subpieces. But this procedure does show that the problem is the limitations of hierarchical tools, not the use of hierarchy itself. A very similar procedure has been used to limit the scope of changes during ECOs [29]. This showed empiricallythatthisprocedure notonly generate hierarchicaldesignswiththe sameefficiency as the corresponding flat designs, but also that under normal conditions (no huge cells) this can be done even when restricted to slicing floorplans. 13.3.2 LOGICAL VERSUS PHYSICAL HIERARCHY Normally, the input to an industrial floorplanner is a netlist defined in structural Verilog or VHDL. Usually, any hierarchy present in the original Verilog o r VHDL files was developed for ease of proving logical correctness. Often, it not appropriate for physical design. One typical difference is that the input logical hierarchy is deep, whereas the preferred physical hierarchy is shallow, with as few levels as practical. Physical design is typically most efficient when gates are combined into blocks that are relatively large (a million gates or so is typical as of 2006). The usual solution is to match the top level ofhierarchy exactly,with further hierarchy underneath on the logical side but a flat structure on the physical side. Generating this hierarchy automati- cally does not usually work because partitioning the top level design constraints normally requires knowledge of design intent. It is almost always better for the designer to specify the high-level hierarchy decomposition, with the help of the floorplanner One of the most common ways for the floorplanner to assign the designer in finding a good physical hierarchy is based on the relationship between a truly flat design and a corresponding hierarchical design, as discussed above. A floorplanner will typically perform a full flat placement, see w here the cells “want” to be, and use this to help define the partitioning into blocks. Visually, this is often done by displaying the results of a flat placement, coloring each cell according to its source block in the hierarchy, as shown in Figure13.2. Blobs of similar color cells then define a potential partitioning—whichcells should be groupedtogether, and where the resulting blockshould be placed on the chip. Because a good partitioning also needs to take many other factors into account, such as the ease of dividing constraints, divisions into work groups, and so on, the partitioning is normally an interactive operation, using the color map as a guide. In practice, many variations of this idea are used: • Use of an earlier version of the design to decide the partitioning. Assuming the differences are small, this may give a good partitioning for the final design. • Use of a faster, but lower quality, algorithm for the flat design. This may include placement, routing, and extraction. The hope is that if the quickly produced flat design is feasible, and Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C013 Finals Page 263 24-9-2008 #8 Industrial Floorplanning and Prototyping 263 FIGURE 13.2 These figures sho w flat placements of a design, with each cell color coded to show what portion of the input hierarchy it came from. All have similar quality, but are quite different. Note also that cells from the same logical hierarchy are often, but not always, grouped together. (Courtesy of David Shen, Cadence.) then used to generate the hierarchy, then each piece, when fully implemented by the final tool, will be at least as good as the result of the quick tool. This is not guaranteed, but is a reasonable guess, especially when the fast tool is tuned to mimic the behavior of the final production-quality tool. • Use the same principle with routing to decide pin positions. Route it once flat, then use where the routes cross the block boundaries as pin positions. • Use the same principle for timing budgeting. Route the chip (flat or with assigned pins), then look at when the signalspropagate throughthe pin locations, and assign timing budgets based on those times. 13.4 PIN ASSIGNMENT AND TIMING BUDGETING Once the gates have been assigned to blocks, designers often wish to develop the blocks in parallel. This implies making the block into a self-contained unit. Each pin must be assigned a position (often but not always on the periphery), and a layer. This is called the pin assignment problem. This is closely related to the problem of terminal propagation [30], which is an internal decision made by the placer when dividing a large problem into two or more subproblems. Another closely related problem is the assignment of the entire chip’s external IO pins. This is a particularly hard problem because it not only involves the chip physical design but also the package parasitics and logical design (the possibility of simultaneous switching). This chip-packag e codesign problem, and the pin assignments that result from it, are beyond the scope of this chapter, but many discussions and considerable research are available [31–38]. Pin assignment interacts strongly with routing. By definition, a feasible pin position assignment allows both the toplevel and the block routing to complete, so routability must be taken into account. Pin placement also interacts with the router to determine the timing of the global interconnects, the ease o f the implementation of the blocks, and wirelength. Many approaches to combine p in assignment and routing have been tried. Pin assignment was combined with global routing by Cong in Ref. [15], and updated in Ref. [16]. The basic idea is to construct a redundant graph of needed connections and then iteratively remove the worst edges, until only a tree remains for each net. Wang et al. [39] approach the same problem by searching for steiner trees among the graph of possible connections, with capacities on each edge. Pin assignment can also be attacked as part of the even more general problems of floorplanning—deciding the placements and shapes of each block. This approach, studied by Pedram, et al. [17] and Koide et al. [40], has not been followed up in industrial floorplanning, because the scale of the individual problems makes it hard to consider Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C013 Finals Page 264 24-9-2008 #9 264 Handbook of Algorithms for Physical Design Automation them all in combination. An additional complication became evident during the late 1990s—long lines, such as those considered in global routing and pin assignment, almost always require buffer insertion. Albrecht et al. [19] and Xiang et al. [41,42] have combined pin assignment and buffer planning, both by casting the assignment as a flow problem (multicom modity flow and min-cost flow, respectively). However, industrial floorplanners do not typically use any of these methods. More typical is to create a flat instance of the hierarchical design, then place it and (roughly) route it. Then pins are assigned where routes cross the block boundaries. This approach has some practical advantages. Routability and timing are taken into account, provided the flat placement and routing tools do so. The resulting pin assignment is guaranteed to be feasible, because the design was routed at least once with those positions. The main drawback is that often the pin positions cannot be assigned until a complete block design is available, meaning that in practice they are often determined with an early version of the design. The hope is that later changes will not upset the pin assignment too much. Next, the timing constraints for each pin must be specified. Normally this is an arrival time for each input, and a required time for each output. The process of assigning a sufficient and feasible timing constraint to each pin, given the overall constraints on the chip, is called time budgeting. Most of the work is based on the zero slack algorithm (ZSA) as described by Hauge at al. [43,44] and in Ref. [20]. In practice, assigning the timing constraints must be done very carefully. A typical design, as of 2006, many have hundreds blocks, each with thousands of pins. If a single one of these hundreds of thousands of pins is assigned an infeasible objective, the entire design process may fail. Thus, ensuring that all timing constraints are feasible is critically important. If the whole design exists, at least in preliminary form, a procedure very similar to the pin assignment described above is often used. A complete prototype of the design is constructed, with a full placement and at least a rough routing. Then extraction, delay calculation, and static timing will result in, for each signal, a time when the signal is available, and a time when it is required. The difference between these is the slack, and as long as the timing objective is within th is interval, the assignment should be feasible. 13.5 ROUTABILITY ANALYSIS A p lacement is not useful if a design cannot be routed, and a timing budget computed from a placement can be wildly off if the routing is not as expected. Hence floorplanners must have a fairly accurate picture of how the routing will turn out, even though they do not do the routing themselves. Such an understanding is obtained through routability analysis. Commercial detailed routers typically have certain characteristics that need to be taken into account by floorplanners. If the design is un-congested, they can usually route every route in very nearly the theoretical minimum length. As the design becomes congested, the routes increase in length compared with the theoretical minimums, as nets must detour to complete their wiring. Finally, if the congestion is too great, the design becomes infeasible and cannot be routed at all. Importantly, the exact point where a design becomes unroutable is hard to predict. The router can often compensate for a few over-full regions by rerouting other nets. In this case, the wirelength will grow slightly, and the execution time may increase co nsiderably, as many passes of rip-up and reroute are required to complete the routing. Eventually,as the density increases still more, the router will fail and the routes cannot be completed. Estimates of routing congestion may be based on a global route [45], or a trial route [46]. In a global route, all routes are mapped to a coarse grid defined over the chip. Each net is assigned a path through this grid, either by explicit routing or probabilistically (see Chapter 23 or Ref. [45], for more details). After all nets are routed, if all the global cells are under capacity, then the design can almost surely be detail routed. If at most a few percent of the global routing cells are just slightly over Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C013 Finals Page 265 24-9-2008 #10 Industrial Floorplanning and Prototyping 265 capacity, the design is still likely to route. If any cells are far over capacity, or if there are clusters of over-capacity cells, then detailed routing will most likely fail. Because the marginal cases are hard to resolve, onecommon techniqueis to have the floorplanner produce a color map of congestion. Then the user can apply their domain-specific knowledge or experience to decide if the final design is likely to route successfully. Often the decision to accept or try again is determined by the available time to market. 13.6 BUFFER AND FLIP-FLOP INSERTION In modern IC processes, a long wire (or a large wiring tree) cannot simply be driven from the source. As a wire gets longer, both the resistance and capacitance scale linearly with the length. Therefore, the delay in a wire of length L scales as O(L 2 ), and quickly dominates all other sources of delay. Furthermore, the output of such a wire will have a very poor slew rate, leading to noise and power problems. To avoid these problems, buffers are inserted into long wires, dividing them into shorter segments. If done properly, this makes the total delay a linear function of length, and fixes the slew rate prob lems. The questions of where to place these buffers, how they interact with routing tree construction, and how big the buffers should be, have received a great deal of attention (see Refs. [47–53] for just a few examples). On the basis of the original Van Ginneken algorithm [54], most of these algorithms work from the leaves to the root, keeping some combination of the arrival time required, driving point capacitance, slew rate, or power. Each step closer to the root creates new combinations, which are pruned by dynamic programming, heuristics, or both. Even if the desired locations for buffers are known, many purely practical problems remain. Do the buffers go into each block, or are they grouped into buffer banks between the blocks? In a multivoltage chip, are there sites of the right voltage available? If blocks are power-switched, is the domain of a proposed buffer site compatible with the power domain of the source and destination? How do you account for the congestion (especially on lower metal and vias) caused by the buffers that are inserted later? How do you back-annotate d elays on components the front-end design does not know about? Industrial floorplanners spend a lot of time and effort trying to make buffer insertion as painless as possible. One saving grace of buffer insertion is that by and large it does not affect logic function, and therefore does not much affect the front-end design (except for the incorporation of delays, which is needed for all signals in any case). However, a long wire on a fast chip may take more than one cycle to traverse the die, and then it becomes advantageous to pipeline the wire. This is a much more difficult problem, as the insertion of a clocked element requires significant changes to both the logical and physical designs. Although automatic methods have been proposed [55–58], they are seldom if ever used. In practice, the floorplan is used to identif y the long wires, extra clo cked elements are added to those wires in the RTL, and then mapped into available locations in the layout. This manual process is tedious and assumes the existence of a fairly static floorplan, and hence is applied only to the highest performance chips such as microprocessors [59]. 13.7 ESTIMATING PARASITICS AND TIMING One of the most important jobs of a floorplanner is estimating the timing of an implementation. The timing is composed of inher ent gate delays and delays induced by parasitics, including incremen tal gate delay due to loading and delays through the interconnect itself. The gate delay portion o f the total delay is normally well characterized, expressed as functions of output load and input slope, and included as part of a standard cell library or IP block. Therefore, almost all o f the uncertainty to be resolved during the implementation revolves around the interconnect parasitics. The process normally p roceeds in three steps: estimate the route, then estimate the electrical pa rasitics of the route, then estimate the delay from the parasitics. Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C013 Finals Page 266 24-9-2008 #11 266 Handbook of Algorithms for Physical Design Automation Because the level of physical details known varies throughout the process of floorplanning and prototyping, there are many different ways to calculate estimate the parasitics, and hence the timing. • During the first synthesis runs, when no physical design yet exists, parasitics are estimated by wire load models. These are estimates of parasitics based only on features from the logical design—fanout, hierarchy crossings, and so on. Lacking physical data, wire load models are at most statistically correct. They can accurately predict characteristics that are the sum or average over many nets, such as total wirelength or power. They are not very good at predicting the length or delays of individual nets or paths [60]. • Once a placement is available, the accuracy goes up dramatically. The exact pin positions can be determined from the placement, then the parasitic estimator can construct a Steiner tree for each net. Although creating an optimal steiner tree is NP-complete [61], there are many fast approximationsavailable [62,63]. Then the horizontaland vertical connectionsof the Steiner tree can be assigned parasitic values, normally based on the average properties of horizontal and vertical layers. Missing in this formulation is any in teraction between nets, and any effects due to layer assignment. • The next level of detail is global routing. Here the surface of the chip is divided into regions, typically 10–20 tracks on a side and one layer thick. Connections are routed on this course grid, trying to respect the capacity of each edge between regions. The estimates are much better, because layer assignment and net–net interaction are now taken into account. However, effects due to adjacency cannot be estimated, because this is not known at this time. • The next level is a trial route, where each net on the global routing grid is assigned a track, but the portions of each route within a global routing grid cell remain estimated. Now much better capacitance estimates are possible, in particular, the effects of adjacent track occupancyare now accounted for. This may seem minor,but today’srelativelysmart routers often count on these effects when optimizing designs, using such tricks are distributing empty tracks adjacent to c ritical signals. Unless these tendencies are included in the analysis, the timing may be off considerably. • Next, an actual router may be u sed to connect the pins. This gives the most accurate estimates, at the expense of longer runtimes. Even here, however, there are speed/accuracy trade-offs. Often a fast, incremental, but less accurate extractor is used in optimization and ECO loops, even if a real router is used to rewire any changes. Then a slower but sign-off quality extractor may be used once the design is be lieved to be in a near-final state. Driven by the same speed versus accuracy trade-off,many floorplannersalso calculate intercon- nect delay differently at different stages of the flow. Early on, a simple lumped-C approximation may be sufficient. When higher quality estimates are available, Elmore delay can be used. As the design approaches timing closure, accuracy is crucial, and the full arsenal of multimoment methods, detailed consideration of cross coupling, slope propagation, and all the other intricacies of sign-off timing analysis must be employed. 13.8 POWER SUPPLY DESIGN Because of constant changes during the early stages of floorplanning, power supply wiring is usually specified as a power supply plan, which is used to generate an actual power supply network. The plan can be executed (or reexecuted) after changes to regenerate the power supply wires and vias. Power supply wires are normally pushed down from the top, with possible cutouts for memory and other IP cells. A typical sequence includes Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C013 Finals Page 267 24-9-2008 #12 Industrial Floorplanning and Prototyping 267 1. Define a main power supply grid.This will include the layers, spacing of wires, and width of wires. In modern(less than 100 nm processes) the maximum width of wires may be severely restricted. Therefore, wide wires must be implemented as a parallel bundle of smaller wires. 2. Define cutouts in the main grid for IP blocks, and build rings around them. This is needed because most IP blocks have their own power supply defined. 3. Perform stub routing. This routes all IP block power supply pins, and all standard cell rows, to the closest point on the power supply network. This is often done with a specialized line probe or maze router. The advent of chips with multiple different supply voltages has led to new problems, and hence new features, in industrial floorplanners. See, for example, voltage islands in Ref. [64]. A prototyper must also include power supply network analysis, as well as power supply design. Power supply wiring changes are more disruptive than almost any other types of changes—they always involve making the power supply wires larger, which requires rerouting signal lines, which normally causes overcongestionand hence problems with routing,timing, and design closure. Fixing these problems certainly requires extensive routing changes, often placement changes, and maybe even RTL changes if the problem is serious enough. Combined with sign-off tools for IR-drop and electromigration that can only be run at the very end of the design cycle, after all detailed routing is complete, there is the potential for fatal errors, discovered very late and requiring extensivefixes. This is exactly the type of problem prototyping is designed to prevent, so it is crucial that a prototyper construct a power supply network that will survive the scrutiny of the final sign-off tools. This involves doing the same types of analysis as the sign-off tools [65]: estimate the power consumption of the cells/blocks, create an electrical model of the power supply n etwork, and evaluate the voltage drops and branch currents. Because a high-priority goal is quick turnaround, the analysis algorithms often make (conservative) approximations to gain analysis speed. 13.9 ECOs AND ACCOUNTING FOR CHANGES A m ajor constraint on the design and capabilities of industrial floorplanners is that the design is constantly changing as the floorplan is finalized. Every step must be designed with this in mind. The input netlist changes, blocks change size and shape, pins come and go, and timing constraints prove easy or infeasible. Each of these must be accommodated without losing any previous manual work, where possible. This problem is not unique to floorplanning,it also occurs in other steps of the design flow as well, such as synthesis and detailed routing. See Refs. [66,67] for general discussions of the problems of incremental CAD, and Ref. [27] for a discussion of design closure. Some of the more common changes, and their implications, are • Netlist changes: This can range from trivial to extremely difficult, depending on how much work has been done on the original netlist. If the changes are minor, and the synthesis tool cooperates by keeping instance and signal names consistent, then finding the gates to be deleted and added is easy, basically just a text compare. For minor changes, a good location for the new gates can often be determined from the gate’s connections. The placement must then be modified, either using techniques specifically developed for placement ECOs [29], or perhapsusing techniques that havebeen developedby the placement community to create a legal layout from an approximate solution [68–74]. On th e other hand, if buffers and inverters have been inserted and removed, and the clock restructured, or if logic paths have been restructured, then the process of mapping the changes into the existing design is very hard. This problem, trying to determine the smallest set of changes that will turn an existing design A into something with the function of new design B, is a difficult superset of formal equivalence checking [75]. As a result, a more common approach is to try to make all operations replayable. Then the designers Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C013 Finals Page 268 24-9-2008 #13 268 Handbook of Algorithms for Physical Design Automation can start with the new netlist, and reperform all the same optimizations they performed the first tim e. If the circuit is suitably similar, with luck sim ilar optimizations will yield similar results. • Block size changes: Block size changes almost always result in the block getting bigger (if the block gets smaller, it is much less of a problem). In this case, the design will surely require new routing (or new estimated routing for a floorplan), almost surely require a new placement, an d maybe a new floorplan. Again the ability replay previous optimizations and operations is helpful. • Pin changes: Removal of a pin presents no particular problem. Addition of a pin requires finding a location for it and wiring to it. • Constraint changes: These may require anywhere between no changes and massive changes to implement. If the constraint is on a block pin, both the block and the top level must be checked, and if necessary modified. Note that replay options should not depend, in general, on physical coordinates, because these may change if a block size changes. Instance names can often be used, if the proceeding software is careful, but netlist comparison functionality may be needed in the floorp lanner if it is not. 13.10 WORKING WITH INCOMPLETE AND INCONSISTENT DESIGNS Because one of the maingoals ofa floorplanneris to findproblemsearly,itis crucialthat floorplanners work with early versions of a design. These designs may be incomplete, or in an inconsistent state, but designers still expect to find problems in the portions that are com plete, where possible. This strongly implies all operations should be as forgiving as practical, performing as much analysis as they can even in the presence of obvious errors and omissions. Input reading and parsing should continue wherever possible even when errors are found. Analysis of a placed design should continue even though overlapping cells are discovered, though with a warning to the user. Estimated routing parasitics should be available if the net is unrouted, partially routed, completely routed, or even shorted to an adjoining net. This accommodatingspirit, though hard to quantify, is crucial in making a floorplanner a useful tool. One of the most common problems in an incomplete design is inclusion of a block that does not yet exist. This may be an IP block that has not yet been acquired, or a block that has not yet been designed. Such a missing block must have at least an area specified, and perhaps pin locations, layer usage, timing constraints, and other properties. Floorplanners allow the block to be specified as hard (specific dimensions) or soft, where the area is fixed but the floorplanner can determine the aspect ratio. Pin locations and timing constraints, if needed, can be specified through graphic interfaces, spreadsheets, text files, o r scripts. Once the real data is available, the floorplanner will replace the estimated cell characteristics with the real ones. Any estimated cell model is faced with strongly conflictingconstraints. Because it will be thrown away, it should be simple and quick to create. However, because it will factor into the size and cost of the chip, and help determine the implementation of the rest of the design, it should be reasonably accurate. Clearly this a tall order, and experience with similar designs is the only realistic hope for reasonable estimates. However, when coupled with experienced designers, this feature is very helpful, and all industrial floorplanners include this ability. 13.11 CONCLUSIONS AND FUTURE WORK Floorplanning and prototyping have evolved from “nice to have” to crucial parts of today’s (as of 2006) design flows. The gap between RTL and working silicon is quite large, and it is almost impossible to predict the performance or cost of a design expressed in RTL alone without a floorplan Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C013 Finals Page 269 24-9-2008 #14 Industrial Floorplanning and Prototyping 269 or prototype. Probably every large chip today, with the possible exception o f purely memory or analog chips, goes through a floorplanner on its way to production. In the future, we can expect that designs will become even more block dominated. In 2006, for example, a chip can ho ld 100 million gates, but typical schedules only permit designers to desig n perhaps 1 million gates f rom scratch. There are two ways designers can still take advantage of the larger chip capacity. First, they can include many copies of a single subdesign, the path taken by multicore processors and graphics chips. However, only parallelizable designs can easily use th is strategy, so more common is to use a large percentage of prebuilt IP blocks. Memories, processors, and analog blocks are most common. This shift from area dominated by standard cells to area dominatedby blocks has several implica- tions for floorplanners.Some of these implications are shown in Figure 13.3. Placement nowincludes a packing component, not just wirelength and timing. A rigorous treatment of obstacles is required for estimated routes, global routing, buffer insertion, and congestion analysis. If a grid power supply is used, it must be on the layers not used by the blocks. A good placement and partitioning, from a user point o f view, may now need rectilinear blocks, not just rectangles. Floorplanning, partitioning, and placement are now strongly interacting problems and may n eed to be combined. These, and many other points, are discussed in Refs. [25,26,76]. Power is also becoming a much larger issue for many designs. A floorplan does not much influence the total amount of power used by a design (the RTL and the semiconductor processing have much larger impacts), but it does affect issues such as thermal gradients and hot spots. Also, floorplanning must be aware of techniques used to reduce power, such as multiple supplies and voltage islands. A third trend is that as chips get larger, many more chip schedules are dominated by logic verification and not physical design. Because time to market is, if anything, becoming even more important, the goal is then to produce the final physical design as soon as possible after the logic is declared correct. This has two implication for floorplanners. Clearly, the programs must execute quickly—within a d ay is strongly preferred so little time is lost in case of problems. The next implication is that each operation must b e automatic, or can be copied from a similar operation done on a previous version of the design. 7000 6000 5000 4000 3000 2000 1000 0 0 1000 2000 3000 4000 5000 6000 7000 FIGURE 13.3 Block-dominated design, including a few very large blocks that make placement and partitioning very challenging. (Courtesy of Jarrod Roy and the authors of Ref. [26].) Alpert/Handbook of Algorithms for Physical Design Automation AU7242_C013 Finals Page 270 24-9-2008 #15 270 Handbook of Algorithms for Physical Design Automation Finally, floorplanners and prototypers are large and complex programs, working on large and complex designs. Better user-interfaces, able to work at higher levels of abstraction, are always needed, as are better software engineering techniques. ACKNOWLEDGMENTS The author would like to thank Dave Noice of Cadence and Raymond Nijssen of Tabula for helpful conversations. REFERENCES 1. S. Khatri and N. Shenoy. Logic synthesis. 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IEEE Transactions on CAD, 22(7), 2003. . (Courtesy of Jarrod Roy and the authors of Ref. [26].) Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C013 Finals Page 270 24-9-2008 #15 270 Handbook of Algorithms for Physical Design. designers Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C013 Finals Page 268 24-9-2008 #13 268 Handbook of Algorithms for Physical Design Automation can start with the new netlist, and reperform. Alpert /Handbook of Algorithms for Physical Design Automation AU7242_C013 Finals Page 262 24-9-2008 #7 262 Handbook of Algorithms for Physical Design Automation but again the