Scan in d Q/Scan out Scan enable clk a Figure 1.8 Multiplexer Flip Flop [7] Scan Cell type Multiplexer master-slave replaces for master-slave latches: in Figure 1.9 the pins scan-in, sca
INTRODUCTION ABOUT DFT & CONCEPTS
Design for Testability (5556523 2S re 2 1 €1
As we all know, as the size and complexity of integrated circuits (IC) increase, error checking becomes more difficult Design for Testability (DFT) is basically meant for providing a method for testing each and every node in the design for structural and other faults Higher the number of nodes which can be tested through the targeted number of patterns, greater is the test coverage of the design For this to be possible, every node in the design has to be controllable and observable DFT technique allows designers to create products with the highest error checking and most time-saving capabilities.
The ability to check for errors is a property of a design, it determines the possibility of being able to create a program to test all possible errors of the designed design produced Previously, the design and error checking were two separate processes, the inspection was carried out only after completing the design cycle But in today's design cycle, inspections will be combined into the design process that forms an implementation process called DFT in design.
It should be noted that the DFT technique only detect the manufacturing's FAULT (open, short in die), not detect design FAULT (wrong function). However, the highest error checking capacity never reaches 100% because there will always be positions in the design that we will not be able to test.
This section will cover some DFT techniques.
Boundary scan is a DFT technique that simplifies printed circuit board testing using a standard chip-board test interface This standard is known as the IEEE
Standard Test Access Port and Boundary Scan Architecture (IEEE Std 1149.1) The boundary-scan technique is often referred to as JTAG.
Boundary scan enables board-level testing by providing direct access to the input and output pads of the integrated circuits on a printed circuit board Boundary scan modifies the I/O circuitry of individual ICs and adds control logic so the input and output pads of every boundary-scan IC can be joined to form a board-level serial scan chain.
The boundary-scan technique uses the serial scan chain to access the I/O ports of chips on a board Because the scan chain is composed of the input and output pads of a chip’s design, the chip’s primary inputs and outputs are accessible on the board for applying and sampling data.
Although boundary scan addresses several board-test issues, it does not directly address chip-level testability Combine chip-test techniques (such as internal scan) with boundary scan to provide testability at both the chip and board level.
Memory BIST Insertion is a DFT technique, which consists of control logics that use different algorithms to create input test patterns, the purpose is to test the fault of Memory bit in design Target is not touching to function mode, cover at much as fault during manufacturing, try to recover the fault to improve the yield.
Most of the built inseft design now use the JTAG as the standard input/output and connect the “built inseft test circuit” to JTAG modify the design for test purpose.
- To insert the “built-inseft test circuit in design”
- Test the memory and shift the test value off chip
- Tester will read the test-value to know which memory bit is fail.
Note: MBIST just focus on the memory part, so you can see that MBIST path and functional path almost different, timing of MBIST almost has no affect to functional func_clock bist_mode
Figure 1.2 Design using Memory BIST
Simple memory: has 4 words; each word has 4 bits; and | reserve.
Figure 1.3 The operation of MBIST MBIST: shift the value 0,1 to each bit of memory and detect if any memory bit has issue.
MBIST: detect the word | bit 1 has issue and start to repair.
MBIST: after repair, the “reserved word” will be the “word 3”.
This technique is like memory BIST, BIST logic uses the same way but the purpose now is to test the logical parts in the design The BIST Insertion Logic technique uses random test sample creation to perform scan sequences in the design.The output is also compared to the simulated signal to see if the test logic block is at fault.
Figure 1.4 Design using BIST Logic The two memory and BIST logic techniques have the advantage of being test samples created by BIST logic, the designer will not interfere with this process But these two techniques have the disadvantage of having to add logic in the design just to perform the test function, the design area will increase much.
Read a mapped design (read_ ddc, read_verilog).
Scan insertion is performed on mapped designs.
The Test Protocol describes how the design operates in scan mode.
Signals involved in the protocol are declared with the “set_dft_signal” command.The protocol is created by the “create_test_protocol” command.
The dft_ drc command perform DRC checks prior to scan insertion.
DRC violations can be debugged graphically with DesignVision or fixed by DFT Compiler with Autofix.
Various commands control the scan architecture (number of scan chains, how clock domain is handled, etc).
The commands primarily used to control the scan architecture are the
“set_scan_configuration” and “set_scan_path” commands.
The preview_dft command is used to get a preview of the scan architecture before it is actually implemented in the design.
The preview step allows for a quicker iteration cycles when changes need to be made to the scan architecture.
The scan architecture is inserted into the design by the insert_dft command
DFT DRC checks can also be run after scan insertion to validate that the scan chains trace properly.
DFT DRC can also be used to get an ATPG coverage estimate for the scan inserted design.
The design handoff is where files are written to disk that will be needed later on in the design process.
Examples: design DDC, verilog netlist, protocol file (for TetraMax), Test Model (for Bottom-Up flows), Scandef (for backend scan chain reordering), etc.
As a Technique that will be researched in the project, Scan Technique will replace normal cells (non-scan cells) with cells with additional scanning cell function When performing replacement, the function of the design will not change which means that it still works properly and fully functionally but the design that has been made Scan Insertion will have an additional silicon error checking function after production.
Scan Insertion technique is the most used Design for Test technique, it is supported by many synthesis tools (Synopsys ) As mentioned above, the Scan Insertion technique will make it easier to check for errors in sequential circuits (including flip-flops) by replacing non-scan cells with scanning cells, which have been replaced to be resumed into scan registers, also known as scan chains.
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Figure 1.6 Design before and after applying Scan
As we know, the purpose of the Scan Insertion technique is to help the design to check for silicon errors, also known as manufacturer errors, common silicon errors:
- Hits the source, hits the ground.
- Silicone lines touching each other (short error).
The above physical errors will affect the functioning of the design, we must model the above errors to support the error checking to:
- The process of creating test samples and analyzing in the design process will be easier.
- Error checking will be more effective.
Fault Coverage determines the aspect ratio of testable nodes on the total number of nodes in a design.
Number of testable node Fault C Nae Total node
Test Coverage is used to determine the ability to test a design's fault after production has been produced Once all the buttons can be identified for a design and test samples created for testable nodes, chips after production will be tested for silicon errors based on test samples Test Coverage is defined as follows:
Test Coverage = Number of testable node
A manufactured product is a collection of millions of silicon units, so it is necessary to achieve good results on Fault Coverage to lower the number of Chips with faulty components delivered to customers Coverage determines the aspect ratio of testable nodes on the total number of nodes in a design.
ARM CORTEX-M0 & SYSTEM DESIGN OVERVIEW
CORTEX-M0 PROCESSOR 1 Full Cortex-MŨ prOC€SSOT . 5-5555<c<ccccscseceeer
The Cortex-MO processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of embedded applications.
The Cortex-M0 processor is a configurable, multistage, 32-bit RISC processor It has an AMBA AHB-Lite interface and includes an NVIC component It also has optional hardware debug functionality The processor can execute Thumb code and is compatible with other Cortex-M profile processors.
Figure 2.1 shows the functional blocks of the processor Figure 2.2 shows the simplified block diagram of the processor. debug
- Nested Vector Comex to Debug
Interrupts —} ơ] B2 ortex-A j ca nế Processor core
Breakpoint and Watchp oint unit
AHB-Lite Serial Wire or interaface JTAG debug port
Figure 2.1 Functional block diagram of Cortex-M0
Interrupt Nested Vector requests and NMI| Interrupt Processor core
AEB Lite bus interfacce mit
Figure 2.2 Simplified block diagram of Cortex-MO Processor
The Cortex-M0 processor from DesignStart is a fixed configuration of the Cortex-
MO processor, enabling low-cost easy access to Cortex-MO processor technology by using a subset of the full product.
The Cortex-MO processor is delivered as a preconfigured and obfuscated, but synthesizable, Verilog version of the full Cortex-MO processor.
Interrupts Neve Veer Cortex-MO
Bus matrix bets} Deousees mm
AHB-Lite interaface Serial Wire
Figure 2.3 Functional block diagram of DesignStart’s Cortex-MO Processor
Figure 2.4 Simplified block diagram of DesignStart’s Cortex-M0 Processor
The interfaces included in the processor for external access include:
The Cortex-MO DesignStart Kit has two parts: the processor, implemented in two synthesizable Verilog files, and a testbench with a basic program.
Figure 3.1 shows the testbench of the example system which is a simple microcontroller design, based on the example provided with the full SMSDK product It differs in its interrupt connectivity It contains the following:
- A single Cortex-M0 processor (a subset from full Cortex-M0 processor)
- Internal program memory (behavioral model)
- SRAM data memory (behavioral model)
- Peripherals (Timers, GPIOs, UARTs, watchdog timer)
Crystal XTALL Cmsếk men clkel CORTEXMOINTERGRATION tal osillator Í NRST_— bị "
Cmséi_ Cmsék_shb_com ABB infrastructure including clkreset Bootloader [* "| | several AHB components
Data memory controler Cmsdk_ahb le
Cmsdk_ahb_rom k sảng System Poo lE? 72
Program memory i ROM thle pont ap
Crmsdk_mcu_pin_mux J/O pin muttiplexor and tristate buffers
Figure 2.5 Example microcontroller system to)
Table 2.1 describes the items that the system contains. p level view
This design contains behavioral memories The DAP and WIC are not present.
The processor connects to the rest of the system through AHB-Lite interface.
Figure 2.6 shows the block diagram of the Cortex-MO example system.
Table 2.1 Items in DesignStart’s example system
Cmsdk_mcu The top design of the microcontroller.
This level contains behavioral memories and clock generation components.
Cmsdk_mcu_system The synthesizable level of microcontroller design.
CORTEXMOINTEGRATION The Cortex-M0 integration layer.
This is encoded RTL code model.
Cmsdk_apb_subsystem A subsystem of APB peripherals and APB infrastructure.
System controller Containing programmable registers for system control.
SysTick reference clock SysTick reference clock generation logic.
Cmsdk_ahb_gpio A low-latency GPIO with AHB interface.
Each GPIO module provides 16 I/O pins.
Cmsdk_mcu_clkctrl The clock and reset generation logic behavioral model.
Cmsdk_mcu_pin_mux The pin multiplexors and tristate buffers for I/O ports.
Cmsdk_ahb_rom A memory wrapper for the ROM.
Cmsdk_ahb_ram A memory wrapper for the RAM.
Cmsdk_ahb_cs_rom_table An example system level CoreSight ROM table that enables a debugger to identify the system as a Cortex-M0 based system.
Cmsdk_ahb_addr_decode Generates the HSELS signal for each memory map component based on the CMSDK address map.
Cmsdk_clkreset Generates clock and reset signals.
XTALI runs at 50MHz It asserts NRST LOW for 5ns at the start of the simulation.
Cmsdk_uart_capture Captures the text messages from UART2 and display the messages during simulation.
Figure 2.6 Block diagram of DesignStart’s example system
STRUCTURE BLOCK AFTER SYNTHESIS
FPGA top system c5 ợt +e [esse at be ÍCGRSCMO integration 1| CMSDK APS subsystem
BUILD ENVIRONMENT & ANALYZE ECO DFET
THE TECHNIQUE WE USED - c5 cc+cccrrerrrrerrerrrrerrrrrrrev 46 3.2 BUILD ENVIRONMENT [8] c:cccesccsessesessesseseessseeseeessessseesseesseveasenseeense! 46 3.2.1 compile_delete_unloaded_sequential_cells
After synthesis step, memory instance is flattening into flipflops So that we can’t apply MBIST to memory instance, we decide to use Internal Scan to handle that component.
After many cases with different number of flipflop per chain, comparing all case and we see that 300 flipflop per chain is return the best test coverage indicator.
The design that Synthesis team give to us it is small, about 6000 flipflop, number of I/O is small so that we decide to use Internal Scan to handle this design instead of all techniques above to save area of the chip and reduce timing violations.
However, we will apply scan compression to compare with Internal Scan
3.2 BUILD ENVIRONMENT [8] set app var compile delete unloaded sequential cells false set app var compile seqmap identify shift registers false set app var compile seqmap identify shift_registers with synchronous logic false set app var test disable enhanced dft_drc_reporting false set app var auto wire load selection false set_app var verilogout no tri true set_app var verilogout show unconnected pins true set app var compile seqmap propagate constants false set app var compile seqmap enable output inversion false set app var case analysis with logic constants true
3.2.1 compile_delete_unloaded_sequential_cells
By default, the compile command deletes unloaded sequential cells To retain such cells, set the compile_delete_unloaded_sequential_cells variable to false.
During compile, if a design contains sequential cells that do not drive loads, the logic driven by that sequential cell might be optimized away, resulting in an inferred no-load cell, or no path to a primary output.
3.2.2 compile_seqmap_identify_shift_registers
Set the compile_seqmap_identify_shift_registers variable to false if you do not want compile_ultra -scan to identify shift registers, or if you want to rescan the shift registers already identified in the design back to scan cells.
The compile_seqmap_identify_shift_registers_with_synchronous_logic variable does not have any effect when shift-register identification is disabled with the compile_seqmap_identify_shift_registers variable.
3.2.3 compile_seqmap_identify_shift_registers_with_synchronous_logic
Set this variable to false if you do not want DC Ultra to identify shift registers containing synchronous logic between the registers or if your design flow does not permit the insertion of additional logic on the scan-enable signal.
3.2.4 test_disable_enhanced_dft_drc_reporting
This variable prevents the dft_drc command from reporting DRC violations using a new format The default is true, which disables the new format and uses the old DRC format for backward compatibility To use the new format, set this variable to false.
When area_locked, the automatic wire load selection uses the initial area to do the first selection of the wire load model and then adjusts the wire load model down if the area drops When area_reselect, the automatic wire load selection during reporting and at various points in compile updates the wire load model to the current area of the design When false, the automatic wire load selection is off For backwards compatibility, we also support the value true True is the same as area_locked.
Declares three-state nets as Verilog wire instead of tri Use this variable to eliminate assign primitives and tran gates in the Verilog output.
This variable instructs the Verilog writer to write out all of the unconnected instance pins, when connecting module ports by name For example, modb bl (.A(in),.Q(out),.Qn()).
By default, the Verilog writer does not write out any unconnected pins For example, modb b1 (.A(in),.Q(out)).
When the value is true (the default), compile tries to identify and remove constant sequential elements in the design, which improves the area of the design.
3.2.9 compile_seqmap_enable_output_inversion
When the value of this variable is true, the compile command allows the mapping of the sequential elements in the design to library cells whose output phase is inverted This can help improve QoR It is also useful when mapping sequential cells to a target library whose sequential cells have only one type of asynchronous inputs (either set or reset) In this case, the only way to match a sequential cell that uses the missing asynchronous input is to use a library cell with the other type of asynchronous input and to invert the output of that cell.
3.2.10.case_analysis_with_logic_constants
When set to true (the default), this variable enables constant propagation, even if a design contains only logic constants When set to false, constant propagation is not performed unless a set case analysis command ¡is specified The disable_case_analysis variable overrides the case_analysis_with_logic_constants variable If the disable_case_analysis variable is set, no constants are propagated. atensecestencssossnssssssssnssessscsusssasscasseossonsseassconsensssesesesseceaueassesseen
# User-defined variables for logical Library setup in dc_setup.tcl
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/alse/t9o\/5YN8PSY5/0€/M-3817.89-53-3/ Libraries/syn \
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14 Directories containing logic Libraries, '# Logie design and script files. et TARGET LIBRARY FILES saedazhvt_ ss0p9svi25c cb
Set LINK LIBRARY FILES saedazhvt_ss0p9Svi25c.db saedszivt_ssopssvizsc.db saed3zrvt_ssopssvizse db
1# Logie cell Uubrary file set SImOL_LIBRARY FILES se generic.sab*
;# Syabol Library file stunsenasesnneensunsseeesesnsessEesOQisAsss2QNAOUSSOULIROUSEONSUAESEEEUREADEEE ELIE
'# User-defined variables for physical Library setup in dc setup tel
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Ts ddidadadehahadahidahahadadihebididubahabudehidedsdedubihadihuhidadihihedhehiledudididshahuhabedlidaddahehidahilededslihihédsledadahia set_app var search path SADDITIONAL SEARCH PATH" | jset_app var target library “STARGET LIBRARY FILES" | set app var symbol library ”$SYMBOL LIBRARY FILES" jset app var synthetic library "dw foundation sldb" set app var link library * SLINK LIBRARY FILES Ssynthetic_ library"
Figure 3.2 Set up library to use
This variable specifies directories that the tool searches for files specified without directory names The search includes looking for technology and symbol libraries, design files, and so on The value of this variable is a list of directory names and is usually set to a central library directory.
The target_library variable specifies the library that Design Compiler uses to select cells for optimization and mapping It is typically set only to the standard cell library You can specify multiple libraries when synthesis includes multithreshold libraries (such as Ivt.db and hvt.db).
This variable specifies the symbol libraries to use during schematic generation. This variable is a list of symbol library names.
This variable specifies a list of synthetic libraries to use when compiling.
The synthetic_library variable works much like the target_library variable does for technology libraries This variable can be set to be a list of zero or more sldb files that you want to use in the compile or replace_synthetic commands When synthetic operators or modules are processed in compile, the operators, bindings, modules, and implementations of the specified library or libraries are used. Synthetic libraries are processed in order So, if two modules in different libraries have the same name, the module in the first listed library is used.
The link_library variable specifies every library that has cells referenced by the netlist The tool uses the libraries specified in the link_library variable for resolving references (linking) The link_library variable can include memory libraries (RAM,ROM, or any macro) in addition to the standard cell library.
(ca t00000000000000000000006000000 set test default delay 0 set test default bidir delay 0 set test default strobe 40 set test defauLt_period 100
#840////##CREATE PORT TEST MODE####### set dft signa\ -test mode all_dft -view existing dft -type Constant -active state 1 -port TEST MODE