Truyền thông vô tuyến CDMA

Ôn tập phần CDMA trong môn Truyền thông vô tuyến Tóm tắt lý thuyết ôn tập Truyền thông vô tuyến, gồm các kênh fading, pilot, frequency diversity, CDMA, OFDM...

Chegg Home Studytools vy Mycourses ~y Mybooks My folder Career Life

17 A slow FH/MFSK system has the following parameters Number of bits per MFSK symbol = 4

Number of MFSK symbol per hop = 5 What is the processing gain of the system in decibel ?

Show transcribed image text

fxo re € am (Pa) =3

Lot di b He Syrabet ere Noll, 4-bit po fri pse Symbol

puntos, Bandwidth oh unipieaded ©

wo || Po |

c

jgnol e9i4t b€- Ý; J j

Hure}ohe , Bandwids df Spreos Ki

1 A direct sequence spread binary phase-shift keying system uses a feedback shift register of Length 19 for the generation of PN sequence The system

is required to have an average probability of symbol error due to externally

gencrated interfering signals that does not exceed 10~ A The processing gain of system is

B The Antijam margin is (Given, erfc(3)= 2 x 107° )

A pseudo-noise (PN) sequence is generated using a feedback shift register of length m

= 4 The chip rate is 10’ chips per second Find the following:

(a) PN sequence length

(b) Chip duration of the PN sequence

(c) PN sequence period The following figure shows a four-stage feedback shift register The initial state of the register is 1000

1 Find the output sequence of the shift register 2 Demonstrate the balance property and run property of a PN sequence 3 Calculate and plot the autocorrelation function of the PN sequence produced by this

chip vate = 10" chips eể Aetond

The inital slate 4 the rveguer is 1000 -

The Aeguerce length ìa 1S- G0, IS Clock pulres are Given, , Given inihal Atate 1000 por Bs B, EB: Be

‘The ANDed output 2 Bo &B, iw the | zin eved pưÌAe and

be bits jer every pulse are shifted right (one it).

clock 0 > | |

clồckll—> | | clock!2 — O

, clock 13 —? Ô oO

5, ly Atey the 1S clock we are

| | O getting the inital abate ie , 1000

So, the Time ÿeredìA SXT Uy:

O | ,

Where Tey, = Clock period i ¥ The late will repeat for sen I | 1S clock cyclen ,

0

18 A fast FH/MFSK system has the following parameters

Number of bits per MFSK symbol = 4 Number of hops per MFSK symbol = 4 The processing gain of the system is dB

Pk 2 Joe Ke ot Pe LK

: bh per re oi ee a