Carbon Nanotubes – A scientometric study_2 pot

MeasurementofHigh-Frequency CharacteristicsofCNTFETsandEquivalentCircuitModelAnalysis 237 Measurement of High-Frequency Characteristics of CNTFETs and EquivalentCircuitModelAnalysis KaoruNarita 0 Measurement of High-Frequency Characteristics of CNTFETs and Equivalent Circuit Model Analysis Kaoru Narita NEC Corporation Japan 1. Introduction Carbon nanotube field effect transistors (CNTFETs) are high-mobility devices that operate at very high-speeds. Theoretical analyses suggest that the cut-off frequency ( f T ) of an ideal CNT- FET is between 800 GHz and 1.3 THz when its gate length i s 0.1 µm (1; 2). Since this frequency is much higher than that of state-of-the-art Si, GaAs, and InP transistors, CNTFETs are promis- ing candidates for future nanoelectronic devices. Singh et al.(3) measured frequency responses of top-gated CNTFETs up to 100 MHz. Li et al.(4) observed 2.6-GHz ope ration of CNTFETs with an LC impedance-matching circuit. However, as Li et al. pointed out (4), measuring high-frequency performance of high-impedance devices, such as CNTFETs, is quite difficult. This is because their output impedances are much higher ( ∼10 5 Ω) than the impedance of the measurement system (50 Ω) using a network analyzer. To perform accurate high-frequency measurements, especially those to determine f T values of such devices, we must measure S-parameters with a network analyzer even though large impedance mismatches hinder us from obtaining accurate measurement data. Kim et al.(5) measured S-parameters of multi- finger CNTFETs by using a network analyzer and obtained an f T value of 2.5 GHz. They also concluded a maximum oscillation frequency ( f max ) of more than 5 GHz was obtained using the maximum stable gain (G msg ). Le Louarn et al.(6) obtained intrinsic f T value of 30 GHz by measuring a CNTFET the channel of which was fabricated using d ielectrophoresis to increase the CNT density. They also obtained G msg value of more than 10 dB at 20 GHz. This chapter will describe a method for accurately measuring and modeling the high- frequency characteristics of CNTFETs, with reference to our experiment and analysis (7). In the experiment, we first decreased the device impedance to be able to measure the S-parameter using network analyzer. This was achieved by developing a high-density multiple-channel CNTFET structure the output impedance of which is much lower than that of the conven- tional single-channel CNTFETs. Then we used a de-embedding procedure to remove exis ting errors in measured S-parameters of small-signal devices i n order to obtain the current gain and unilateral power gain (U) that can determine accurate f T and f max values. For accurate RF mode ling of CNTFETs, we develope d an equivalent circuit RF model that includes par- asitic resistances and capacitances of the CNTFET. Then the exp ression of the f T ( f max ) was derived as a function of them. Not ignoring the higher orde r parasitic resistances and capac- itances neglected in the cases of current RF transistors, an accurate model was obtained that can fully explain the experi mental results. 13 CarbonNanotubes238 S S D G CNT 20 µm Catalyst A A’ SiO 2 (100 nm) Si Au Au Al SiO 2 (40 nm) CNT 0.2 µm 0.6 µm A A’ a) b) c) d) Fig. 1. Multiple-channel CNTFET structure: a) top view, b) cross section, c) optical micro- graph, d) atomic force micrograph. 2. Multiple-channel CNTFET Structure As shown in Figure 1, the evaluated CNTFET was fabricated on a SiO 2 insulator on a highly resistive (10 kΩcm) Si substrate. Iron was d eposited for a catalyst and was p atterned by electron-beam lithography. Single-walled carbon nanotubes (SWCNTs) were grown from the catalyst islands by chemical vapor deposition. The average density of the SWCNTs was 5 per µm, as observed in the AFM analysis (Figure 1-d). The gate oxide was 40-nm thick SiO 2 , which serves as a passivation layer to retain stable characteristics and suppress hysteresis of the CNTFET I-V curve. The top-gated structure was used to reduce parasitic capacitances. The gate consisted of two 20-µm wide fingers. Thus, approximately 200 SWCNT channels were constructed in the total 40-µm gate width. The drain and source electrodes were formed by evaporation of Au, and ohmic contacts were made with CNT channels. 3. De-Embedding Procedure Using the multiple-channel structure decreases the output impedances of the devices more than those of the single-channel CNTFETs. Therefore, their output signals can be observed Source Source Source Source Drain Gate DUT Z1 DUT Z3 G1 Z2 G2 G3 a) b) Fig. 2. RF test structure: a) pad layout, b) equivalent circuit. directly with the network analyzer. However, output impedances of CNTFETs are still higher than those of conventional RF transistors. This means that the output signal of the device is small and easily disturbed or masked by the parasitic elements. The drain, gate, and source electrodes of the CNTF ET were connected with pads for RF probe contacts. The dimensions of the pad were 100 × 100 µm, and its layout is s hown in Figure 2-a. The areas of the pad and the connective wiring region are much larger than the transistor area (shown as DUT in Fi gure 2-a), and this large area forms p ar asitic elements and causes large errors in CNT- FET S-parameters. Therefore, we applied the de-embedding procedure to effectively elim- inate the parasitic error matrix, and only the S-parameters of the transistor were ex tr acted using open-short-through standards on the substrate. This method is basically the same as that des cribed in Vandamme et al.(8) and Temeijer et al.(9). The equivalent circuit of the RF test-structure, including pads and CNTFETs, is shown in Figure 2-b. In the figure, parasitic elements (Z 1 , Z 2 , Z 3 , G 1 , G 2 , G 3 ) are shown. Z 1 , Z 2 , Z 3 are parasitic impedances, and G 1 , G 2 , G 3 are parasitic admi ttances. To determine the parasitic elements, we made f our standard pat- terns (Open, Short1, Short2, Through) that are the same as the CNTF ET measurement patterns but without CNT channels (Figure 3). The equivalent circuits of the four standard patterns are shown in Figure 4. Each standard pattern contains a different combination of the parasitic elements, and so they can be determined by the measured S-parameters of the four stan- dards. Let us transform the measured S-parameters (s ij : i, j = 1, 2) o f the four standards to the Y-parameter s and express them as y ijop , y ijsh1 , y ijsh2 , y ijthr (i, j = 1, 2). Here, y ijop is the Y-parameters of the Open standard, y ijsh1 is the Y-parameters of the Short1 standard, y ijsh2 is the Y-parameters of the Short2 standard, y ijthr is the Y-parameters of the Through standard. MeasurementofHigh-Frequency CharacteristicsofCNTFETsandEquivalentCircuitModelAnalysis 239 S S D G CNT 20 µm Catalyst A A’ SiO 2 (100 nm) Si Au Au Al SiO 2 (40 nm) CNT 0.2 µm 0.6 µm A A’ a) b) c) d) Fig. 1. Multiple-channel CNTFET structure: a) top view, b) cross section, c) optical micro- graph, d) atomic force micrograph. 2. Multiple-channel CNTFET Structure As shown in Figure 1, the evaluated CNTFET was fabricated on a SiO 2 insulator on a highly resistive (10 kΩcm) Si substrate. Iron was d eposited for a catalyst and was p atterned by electron-beam lithography. Single-walled carbon nanotubes ( SW CNTs) were grown from the catalyst islands by chemical vapor deposition. The average density of the SWCNTs was 5 per µm, as observed in the AFM analysis (Figure 1-d). The gate oxide was 40-nm thick SiO 2 , which serves as a passivation layer to retain stable characteristics and suppress hysteresis of the CNTFET I-V curve. The top-gated structure was used to reduce parasitic capacitances. The gate consisted of two 20-µm wide fingers. Thus, approximately 200 SWCNT channels were constructed in the total 40-µm gate width. The drain and source electrodes were formed by evaporation of Au, and ohmic contacts were made with CNT channels. 3. De-Embedding Procedure Using the multiple-channel structure decreases the output impedances of the devices more than those of the single-channel CNTFETs. Therefore, their output signals can be observed Source Source Source Source Drain Gate DUT Z1 DUT Z3 G1 Z2 G2 G3 a) b) Fig. 2. RF test structure: a) pad layout, b) equivalent circuit. directly with the network analyzer. However, output impedances of CNTFETs are still higher than those of conventional RF transistors. This means that the output signal of the device is small and easily disturbed or masked by the parasitic elements. The drain, gate, and source electrodes of the CNTF ET were connected with pads for RF probe contacts. The dimensions of the pad were 100 × 100 µm, and its layout is s hown in Figure 2-a. The areas of the pad and the connective wiring region are much larger than the transistor area (shown as DUT in Fi gure 2-a), and this large area forms p ar asitic elements and causes large errors in CNT- FET S-parameters. Therefore, we applied the de-embedding procedure to effectively elim- inate the parasitic error matrix, and only the S-parameters of the transistor were ex tr acted using open-short-through standards on the substrate. This method is basically the same as that des cribed in Vandamme et al.(8) and Temeijer et al.(9). The equivalent circuit of the RF test-structure, including pads and CNTFETs, is shown in Figure 2-b. In the figure, parasitic elements (Z 1 , Z 2 , Z 3 , G 1 , G 2 , G 3 ) are shown. Z 1 , Z 2 , Z 3 are parasitic impedances, and G 1 , G 2 , G 3 are parasitic admi ttances. To determine the parasitic elements, we made f our standard pat- terns (Open, Short1, Short2, Through) that are the same as the CNTF ET measurement patterns but without CNT channels (Figure 3). The equivalent circuits of the four standard patterns are shown in Figure 4. Each standard pattern contains a different combination of the parasitic elements, and so they can be determined by the measured S-parameters of the four stan- dards. Let us transform the measured S-parameters (s ij : i, j = 1, 2) o f the four standards to the Y-parameter s and express them as y ijop , y ijsh1 , y ijsh2 , y ijthr (i, j = 1, 2). Here, y ijop is the Y-parameters of the Open standard, y ijsh1 is the Y-parameters of the Short1 standard, y ijsh2 is the Y-parameters of the Short2 standard, y ijthr is the Y-parameters of the Through standard. CarbonNanotubes240 S S D S S D G S S D S S D Open Short1 Short2 Through G contact G contact G Fig. 3. Standard patterns for de-embedding G 3 Z 2 Z 1 G 2 G 1 G 3 Z 2 Z 1 G 2 Z 3 G 1 G 3 Z 2 Z 1 G 2 Z 3 G 1 Z 2 Z 1 G 2 G 1 Open Short1 Short2 Through Fig. 4. Equivalent circuit of standard patterns. Thus the parasitic elements (Z 1 , Z 2 , Z 3 , G 1 , G 2 , G 3 ) can be expressed as follows: G 1 = y 11op + y 12op (1) G 2 = y 22op + y 12op (2) G 3 =  −1 y 12op + 1 y 12thr  −1 (3) Z 1 = 1 2  −1 y 12thr + 1 y 11sh1 − G 1 + 1 y 22sh2 −G 2  (4) Z 2 = 1 2  −1 y 12thr − 1 y 11sh1 − G 1 + 1 y 22sh2 −G 2  (5) Z 3 = 1 2  1 y 12thr + 1 y 11sh1 − G 1 − 1 y 22sh2 −G 2  (6) Using the above parasitic el ements (parasitic impedance and parasitic admittance), the de- embedded matrix can be obtained by the following procedure. Let us transform the measured S-matrix (S meas ) into the Y-matrix and write it as Y meas . First, we subtract G 1 , G 2 from Y meas and obtain Y A as follows: Y A = Y meas −  G 1 0 0 G 2  (7) Transforming the obtained Y A to the Z-matrix (Z A ), we next subtract Z 1 , Z 2 , Z 3 from Z A and obtain Z B as follows: Z B = Z A −  Z 1 + Z 3 Z 3 Z 3 Z 2 + Z 3  (8) Again, tr ansforming the obtained Z B into the Y-matrix (Y B ), we subtract G 3 from Y B and obtain Y DUT as follows: Y DUT = Y B −  G 3 −G 3 −G 3 G 3  (9) Y DUT is the final de-embedded Y-matrix of the DUT part. 4. Measurement Results 4.1 DC Characteristics The DC character istics of the multiple-channel CNTFET were measured with a semiconductor parameter analyzer (Agilent 4156C). Figure 5-a shows the drain current (I d ) versus gate volt- age (V g ) curve when the drain voltage (V d ) was −2 V. I d versus V d curve is shown in Figure 5-b. These characteristics are like p-type FETs but the drain current is not zero even when the gate voltage is small enough. This is due to the metallic carb on nanotubes. Because the metal- lic carbon nanotubes do not affect the high-frequency characteristics of the device, we did not perform a special removal process such as a burn out procedure. From the DC curve (Figure 5), transconductance (g m = ∂I d /∂V g ) of 226 µS and drain conductance (g d = ∂I d /∂V d ) of 1 mS (at V g = 5 V, V d = −2 V) were obtained. The drain current of our multi-channel CNTFET is more than 200 times larger than that of single-channel CNTFETs. We observed hysteresis in the I-V cur ves; however, the width of the hysteresis is much smaller (∆V g < 1 V, ∆V d < 0.1 V) than that of non-passivated CNTFETs. MeasurementofHigh-Frequency CharacteristicsofCNTFETsandEquivalentCircuitModelAnalysis 241 S S D S S DG S S D S S D Open Short1 Short2 Through G contact G contact G Fig. 3. Standard patterns for de-embedding G 3 Z 2 Z 1 G 2 G 1 G 3 Z 2 Z 1 G 2 Z 3 G 1 G 3 Z 2 Z 1 G 2 Z 3 G 1 Z 2 Z 1 G 2 G 1 Open Short1 Short2 Through Fig. 4. Equivalent circuit of standard patterns. Thus the parasitic elements (Z 1 , Z 2 , Z 3 , G 1 , G 2 , G 3 ) can be expressed as follows: G 1 = y 11op + y 12op (1) G 2 = y 22op + y 12op (2) G 3 =  −1 y 12op + 1 y 12thr  −1 (3) Z 1 = 1 2  −1 y 12thr + 1 y 11sh1 − G 1 + 1 y 22sh2 −G 2  (4) Z 2 = 1 2  −1 y 12thr − 1 y 11sh1 − G 1 + 1 y 22sh2 −G 2  (5) Z 3 = 1 2  1 y 12thr + 1 y 11sh1 − G 1 − 1 y 22sh2 −G 2  (6) Using the above parasitic el ements (parasitic impedance and parasitic admittance), the de- embedded matrix can be obtained by the following procedure. Let us transform the measured S-matrix (S meas ) into the Y-matrix and write it as Y meas . First, we subtract G 1 , G 2 from Y meas and obtain Y A as follows: Y A = Y meas −  G 1 0 0 G 2  (7) Transforming the obtained Y A to the Z-matrix (Z A ), we next subtract Z 1 , Z 2 , Z 3 from Z A and obtain Z B as follows: Z B = Z A −  Z 1 + Z 3 Z 3 Z 3 Z 2 + Z 3  (8) Again, tr ansforming the obtained Z B into the Y-matrix (Y B ), we subtract G 3 from Y B and obtain Y DUT as follows: Y DUT = Y B −  G 3 −G 3 −G 3 G 3  (9) Y DUT is the final de-embedded Y-matrix of the DUT part. 4. Measurement Results 4.1 DC Characteristics The DC character istics of the multiple-channel CNTFET were measured with a semiconductor parameter analyzer (Agilent 4156C). Figure 5-a shows the drain current (I d ) versus gate volt- age (V g ) curve when the drain voltage (V d ) was −2 V. I d versus V d curve is shown in Figure 5-b. These characteristics are like p-type FETs but the drain current is not zero even when the gate voltage is small enough. This is due to the metallic carb on nanotubes. Because the metal- lic carbon nanotubes do not affect the high-frequency characteristics of the device, we did not perform a special removal process such as a burn out procedure. From the DC curve (Figure 5), transconductance (g m = ∂I d /∂V g ) of 226 µS and drain conductance (g d = ∂I d /∂V d ) of 1 mS (at V g = 5 V, V d = −2 V) were obtained. The drain current of our multi-channel CNTFET is more than 200 times larger than that of singl e-channel CNTFETs. We observed hys teresi s in the I-V cur ves; however, the width of the hysteresis is much smaller (∆V g < 1 V, ∆V d < 0.1 V) than that of non-passivated CNTFETs. CarbonNanotubes242 Fig. 5. DC characteristics of multiple-channel CNTFET: a) I d -V g curve, b) I d -V d curve. 4.2 RF Characteristics Using RF probes (Cascade Microtech I40-GSG-125), we measured 2-port S-parameters of the device between 100 MHz and 20 GHz with the network analyzer (Agilent PNA N5230A). Standard SOLT-calibration was performe d at the probe ends by using the calibration sub- strate. The measured S-parameters were de-embedded by the previously mentioned error removal procedure, and we obtained current gain ( | h 21 | = | y 21 /y 11 | ) from the de-embedded Y-parameters (Y DUT ) (Figure 6-a). In this figure, the measured and de-embedded data are dis- played. The de-embedded data was 15 dB larger than the measured data. The f T value was determined to be 10.3 GHz by obtaining the frequency when the current gain was unity (0 dB). Also, the unilateral power gain (U) was calculated from the de-embedded Y-parameters (Y DUT ) by the formula below and plotted as a function of frequency in Figure 6-b. U = | y 21 −y 12 | 2 4 [ Re(y 11 ) Re(y 22 ) −Re(y 12 ) Re(y 21 ) ] (10) The f max value was determi ned to be 3.5 GHz by obtaining the frequency when the unilateral power gain was unity (0 dB). 5. Equivalent circuit model analysis Figure 7 shows our proposed equivalent small-signal circui t model for multiple-channel CNT- FET. Here, R s ( R d ) is the resistance of the CNT between the source (drain) and gate, and con- tains the resi stance of the CNT extensions and contact resistances. R s and R d were extracted from the DC measurements, as described in (10) . The extracted values of R s and R d were 420 Ω each for our multiple - channel CNTFET. Note that R s and R d values of usual RF transistors are negligibly s mall (a few ohms); however, for CNTFETs, even when using mul tiple-channel structures, these resistances play a dominant role in the analysis. The g m and g d in Figure 7 are intrinsic transconductance and drain conductance and relate to measured transconductance (g  m ) and drain conductance (g  d ), like in Chow and Antoniadis (11), as follows: g m = g  m 1 − g  m R s − g  d (R s + R d ) and g d = g  d 1 − g  m R s − g  d (R s + R d ) . (11) Using these relations and the DC measurement results, we calculated the intrinsic transcon- ductance and drain conductance as g m = 3.47 mS and g d = 15.4 mS. The intrinsic g m and g d values are one order of magnitude larger than g  m and g  d because of the large R s and R d val- ues. The value C g−cnt (= C g−cnts + C g−cntd ) is the capacitance between the gate electrode and CNTs. We assumed that C g−cnts = C g−cntd because of the symmetry of the device. According to Burke (1), C g−cnt consists of the e lectrostatic capacitance (C ES ) and the quantum capacitance (C Q ) and is g iven by C −1 g −cnt = C −1 ES + C −1 Q . C Q is about 100 aF/µm. C ES is calculated from geometry (as shown in Figure 8-a) and is given by C ES = 2πε r ε 0 / cosh −1 (2h/d). In our case, h = 40 nm and d = 1 nm, s o C ES was estimated to be 42.5 aF/µm. Thus, C g−cnt (one CNT) was calculated to be 30 aF/µm, and taking into account the gate length of 0.2 µm and 200 CNT channels, we calculated C g−cnt = 1.2 fF (C g−cnts = C g−cntd = 0.6 fF). C gs and C gd , as shown in Fi gure 7, are parasitic capacitances between the gate and source and the gate and drain. C gs + C gd can be approximated by the electrostatic capacitance between a coplanar stripline and ground planes on a dielectric (Figure 8-b), like in Collin (12), as f ollows: MeasurementofHigh-Frequency CharacteristicsofCNTFETsandEquivalentCircuitModelAnalysis 243 Fig. 5. DC characteristics of multiple-channel CNTFET: a) I d -V g curve, b) I d -V d curve. 4.2 RF Characteristics Using RF probes (Cascade Microtech I40-GSG-125), we measured 2-port S-parameters of the device between 100 MHz and 20 GHz with the network analyzer (Agilent PNA N5230A). Standard SOLT-calibration was performe d at the probe ends by using the calibration sub- strate. The measured S-parameters were de-embedded by the previously mentioned error removal procedure, and we obtained current gain ( | h 21 | = | y 21 /y 11 | ) from the de-embedded Y-parameters (Y DUT ) (Figure 6-a). In this figure, the measured and de-embedded data are dis- played. The de-embedded data was 15 dB larger than the measured data. The f T value was determined to be 10.3 GHz by obtaining the frequency when the current gain was unity (0 dB). Also, the unilateral power gain (U) was calculated from the de-embedded Y-parameters (Y DUT ) by the formula below and plo tted as a function of frequency in Figure 6-b. U = | y 21 −y 12 | 2 4 [ Re(y 11 ) Re(y 22 ) −Re(y 12 ) Re(y 21 ) ] (10) The f max value was de termined to be 3.5 GHz by obtaining the frequency when the unilateral power gain was unity (0 dB). 5. Equivalent circuit model analysis Figure 7 shows our proposed equivalent small-signal circui t model for multiple-channel CNT- FET. Here, R s ( R d ) is the resistance of the CNT between the source (drain) and gate, and con- tains the resi stance of the CNT extensions and contact resistances. R s and R d were extracted from the DC measurements, as described in (10). The extracted values of R s and R d were 420 Ω each for our multiple - channel CNTFET. Note that R s and R d values of usual RF transistors are negligibly s mall (a few ohms); however, for CNTFETs, even when using mul tiple-channel structures, these resistances play a dominant role in the analysis. The g m and g d in Figure 7 are intrinsic transconductance and drain conductance and relate to measured transconductance (g  m ) and drain conductance (g  d ), like in Chow and Antoniadis (11), as f ollows: g m = g  m 1 − g  m R s − g  d (R s + R d ) and g d = g  d 1 − g  m R s − g  d (R s + R d ) . (11) Using these relations and the DC measurement results, we calculated the intrinsic transcon- ductance and drain conductance as g m = 3.47 mS and g d = 15.4 mS. The intrinsic g m and g d values are one order of magnitude larger than g  m and g  d because of the large R s and R d val- ues. The value C g−cnt (= C g−cnts + C g−cntd ) is the capacitance between the gate electrode and CNTs. We assumed that C g−cnts = C g−cntd because of the symmetry of the device. According to Burke (1), C g−cnt consists of the e lectrostatic capacitance (C ES ) and the quantum capacitance (C Q ) and is g iven by C −1 g −cnt = C −1 ES + C −1 Q . C Q is about 100 aF/µm. C ES is calculated from geometry (as shown in Figure 8-a) and is given by C ES = 2πε r ε 0 / cosh −1 (2h/d). In our case, h = 40 nm and d = 1 nm, s o C ES was estimated to be 42.5 aF/µm. Thus, C g−cnt (one CNT) was calculated to be 30 aF/µm, and taking into account the gate length of 0.2 µm and 200 CNT channels, we calculated C g−cnt = 1.2 fF (C g−cnts = C g−cntd = 0.6 fF). C gs and C gd , as shown in Fi gure 7, are parasitic capacitances between the gate and source and the gate and drain. C gs + C gd can be approximated by the electrostatic capacitance between a coplanar stripli ne and ground planes on a dielectric (Figure 8-b), like in Collin (12), as fol lows: CarbonNanotubes244 Fig. 6. RF characteristics of mul tiple-channel CNTFET: a) current gain (|h 21 |), b) power gain (U), bias condition is V d = −2 V, V g = 5 V. Cgd Cg-cnts Rs gmVg gd Rd Source DrainGate Cgs Rg Ri Vg Cg-cntd Rg Rs Rd Cgs Cgd G S D gd Ri Cg-cntd Cg-cnts Cds Cds CNT gmVg Fig. 7. Equivalent small-signal circuit mod el for CNTFET. MeasurementofHigh-Frequency CharacteristicsofCNTFETsandEquivalentCircuitModelAnalysis 245 Fig. 6. RF characteristics of mul tiple-channel CNTFET: a) current gain (|h 21 |), b) power gain (U), bias conditio n is V d = −2 V, V g = 5 V. Cgd Cg-cnts Rs gmVg gd Rd Source DrainGate Cgs Rg Ri Vg Cg-cntd Rg Rs Rd Cgs Cgd G S D gd Ri Cg-cntd Cg-cnts Cds Cds CNT gmVg Fig. 7. Equivalent small-signal circuit mod el for CNTFET. CarbonNanotubes246 Gate CNT h d a) εr LsLs L b) Fig. 8. Capacitance geometry: a) gate-CNT capacitance, b) co p lanar stripline on d ielectric C gs + C gd = 2(ε r + 1)ε 0 K(k) K( √ 1 −k 2 ) , (12) where k = L/(L + 2L s ), and K is the complete elliptic integral of the first kind. Considering L = L s = 0.2 µm and W = 40 µm, we obtain C gs + C gd = 2.2 fF. Once the equivalent circuit model is constructed like in Figure 7, we can derive f T by calcu- lating the H-parameter s of the circuit (13). f T is given as 1 2π f T = 1 g m C g + g d g m C g (R s + R d ) + C g−cntd (R s + R d ) + (C gs + C gd )R s , (13) where C g = C gs + C gd + C g−cnts + C g−cntd . Substituting the parameters into Equation (13), we obtain f T (model) = 10.6 GHz. This value is consistent with the experime ntal one: f T (experiment) = 10.3 GHz. Similarly, we can derive the expression of f max by calculating the unilateral power gain U (Equation (10)) from the Y-parameter of the equivalent circuit and solving the equation: U = 1. The following formula is the calculation result. f max =     f T 2πR g  g d g m C g + C gd + C g−cntd  + 2π f T g 2 m R g Ψ  (14) where C g and Ψ are defined as fo llows: C g = C gs + C gd + C g−cnts + C g−cntd (15) Ψ = R s R d  g d C g−cnts + g d C g−cntd + g m C g−cntd  2 (16) + R i g d C g−cnts (C g−cnts + g d R s C g−cnts + g d R d C g−cnts + g m R d C g−cntd ) Gate h r V x a) b) 0 5 10 15 20 25 30 35 40 0.0 5.0x10 8 1.0x10 9 1.5x10 9 2.0x10 9 E (V/m) x (nm) CNT Fig. 9. (a) Geometry of gate electrode and CNT, (b) Ele ctric field at x calculated under the condition of V = −5 V, r = 0.5 nm, h = 40 nm. The above formula of f max is more complicated than the expression of f T (Equation(13)). Note that the expression of f max contains not only the parameters included in the expres- sion of f T , but also the parameters R g and R i . R g is the gate resistance and can be estimated from the resistivity of the gate electrode material of aluminum. R g in our case is about 40 ohms. R i is equivalent to the channel resistance (R ch ) in the case of current transistors and can be expressed as R ch = α/g m . Here, α is a coefficient and has a value less than 0.2 (13). If we assume that α = 0.2 and use the g m of the CNTFET, we obtain R i ≈ 60. Us- ing these values of R g , R i and the other parameters used for estimation of f T , we can esti- mate f max as f max | R i =60 =19.2GHz. This value is much larger than the experimental value: f max (experiment)=3.5 GHz. To clarify this discrepancy, we should consider the phenomenon peculiar to the CNT channels, and one consistent model was proposed as shown bel ow. The diameter of the SWCNTs used for the multiple-channel CNTFET is about 1 nm, and S- parameter was measured under the condition that the gate electrode voltage is 5 V. This gate voltage is relatively high enough that the strong electric field exists at the vicinity of the CNTs. To estimate the el ectric field, we assume that the gate e lectrode and the CNT are an infinite conductive plane and an infinite length of conductive cylinder that is separate from the plane at the distance h and has a radius of r, as shown in the Figure 9-a. When the potential of the [...]... conventional Cu material is replaced by a bundle of CNTs Next, the EMC behaviour of two adjacent traces in a stripline is analyzed, checking the high-frequency effects and the crosstalk noise Finally the use of CNTs as pillars for nanopackaging is studied and the introduced parasitics are compared to conventional material realization Carbon nanotube interconnects are shown to have better behaviour with... 1981-1986 [2] S Hasan, S Salahuddin, M Vaydyanathan, and M A Alam, "High-Frequency Performance Projections for Ballistic Carbon- Nanotube Transistors", IEEE Transaction on Nanotechnology, Vol 5, No 1, (2006), pp 14-22 [3] D.V.Singh, K .A Jenkins, J Appenzeller, D Neumayer, A Grill, and H.-S.P Wong, "Frequency Response of Top-Gated Carbon Nanotube Field-Effect Transistors", IEEE Transactions on Nanotechnology,... metallic At the ends of the two horizontal tracts, a lumped contact resistance of 50 k is considered for each metallic CNT For the Cu case, the horizontal tracts are described as striplines, whereas the via is modeled through a series impedance R-L and a pad capacitance to ground (e.g., Chiariello et al., 2009): R via  l via ( d via / 2 ) 2 , C via  1.41 r D P T [ pF ] , L via  5.08  l via D AP... propagation along CNT interconnects is derived from a semi-classical solution of the transport equation All the quantistic and kinetic effects affecting the electrodynamics of charge carriers are taken into account through global parameters (kinetic inductance and quantum capacitance) which have been simply related to the number of effective conducting channel per CNT shell Both the rigorous approach and... field, we assume that the gate electrode and the CNT are an infinite conductive plane and an infinite length of conductive cylinder that is separate from the plane at the distance h and has a radius of r, as shown in the Figure 9 -a When the potential of the 248 Carbon Nanotubes Gate CNT Fig 10 Equivalent circuit between gate electrode and CNT CNT is V, the potential at x is written as the expression below... horizontal traces and a vertical via The electrical and geometrical parameters given in Table 4 are typical values for the intermediate level at 22 nm technology node (ITRS, 2007) The signal traces on the layers and the via barrel may be either constituted by a solid Cu conductor or by a SWCNT bundle In particular we consider the case of traces made by bundles of SWCNTs of D  0.94 nm, with a fraction of... Tang, and P.J Burke, "Carbon Nanotube Transistor Operation at 2.6 GHz", Nano Letters, Vol 4, No 4, (2004), pp 753-756 [5] S Kim, T Choi, L Rabieirad, J.-H Jeon, M Shim, and S Mohammadi, "A Poly-Si Gate Carbon Nanotube Field Effect Transistor for High Frequency Applications", IEEE MTT-S International Microwave Symposium Digest, 12-17 June, (2005), pp 303-306 250 Carbon Nanotubes [6] A L Louarn, F Kapche,... integration between CNTs and ICs, testimonials of this technological trend (a) (b) Fig 2 (a) Vertical CNT bundles as flip-chip bumps (Fujitsu Labs.); (b) carbon nanotubes wiring in an oscillator circuit (Stanford University & Toshiba) Carbon Nanotubes Interconnects for Nanoelectronics Circuits 253 2 Electromagnetic propagation models for CNTs A carbon nanotube is realized by rolling-up a sheet of a mono-atomic... resistance makes useless an interconnect made by a single CNT shell For practical application purposes, bundles of SWCNTs or MWCNTs are proposed as material to be used in fabricating interconnect traces (ITRS, 2007): all the CNT shells are fed in parallel, so lowering the total resistance Following the stream of what done in paragraph 3.1, we can model the propagation along a CNT bundle in the frame of... future nanoelectronics (a) (b) (c) Fig 1 Some real-world nanotubes: (a) AFM image of chiral tube of 1.3 nm diameter (Technical University, Delft); (b) TEM image of a crystalline nanotube bundle (Rice University); (c) a single nanotube as interconnect between gold electrodes (IBM) 252 Carbon Nanotubes Due to the potential applications of CNTs in nanoelectronics, many efforts have been made in literature . 7, are parasitic capacitances between the gate and source and the gate and drain. C gs + C gd can be approximated by the electrostatic capacitance between a coplanar stripline and ground planes. 7, are parasitic capacitances between the gate and source and the gate and drain. C gs + C gd can be approximated by the electrostatic capacitance between a coplanar stripli ne and ground planes. cases of current RF transistors, an accurate model was obtained that can fully explain the experi mental results. 13 Carbon Nanotubes 23 8 S S D G CNT 20 µm Catalyst A A’ SiO 2 (100 nm) Si Au