Content of the project: Present and evaluate the performance of some popular clock gating designs - Designed the 4-bit ripple counter and applied these clock gating techniques to evaluat
OVERVIEW
Introduction
The main goal in designing circuits is to produce a small-sized device that consumes minimal power and has a long battery life To achieve this objective, designers must optimize the design parameters of efficiency, speed, power, and area CMOS technology is one such technology that employs integrated circuit techniques
In CMOS circuits, power consumption is determined by two critical components: static power and dynamic power
In contemporary circuit design, a range of methods are applied to reduce power consumption, such as Power gating and Clock gating Among these techniques, Clock gating is a widely utilized method for enhancing power efficiency in CMOS circuits A successful approach for achieving power efficiency in Clock gating is RTL Clock gating, which can be implemented at various levels, such as the system level, gate level, and RTL level
There have been articles discussing the overall view of Clock Gating technique worldwide The main purpose of implementing the Clock Gating technique is to eliminate the provision of unnecessary clock pulses to circuitry that would not result in any output change The techniques presented in the article demonstrate a clear understanding of the theory, block diagrams, and comparisons between the techniques However, there is still a lack of specific numerical evaluation to draw a conclusion and the overall perspective of the techniques
In this project, the team will present the basic theories of each technique based on the previous research papers Additionally, the team will simulate different Clock Gating techniques to provide specific numerical results Through this, a comparison and evaluation of the results of each technique when applied in digital circuit design will be conducted
Objective
The project aims to provide the fundamental concepts of Clock gating techniques
In addition, the project will clearly define the design of each technique and perform simulations The project will apply the techniques and incorporate them into digital circuit designs Then, the performance and differences between the techniques will be evaluated and analyzed.
Project Limit
The project will not delve deeply into the specific design of Clock gating techniques on an integrated circuit or a microprocessor Instead, the project will focus on comparing and evaluating Clock gating techniques on the same circuit structure and conducting an analysis of their efficiency and power consumption.
Research Methodology
The research methods used in this project are:
➢ Analysis and synthesis of theoretical knowledge: analyzing the difficulties and synthesizing all the relevant theories before selecting and applying them
➢ Simulation-based research: using simulation software to observe and analyze the processes.
Research Subject and Research Scope
The research subject of this project is Clock gating methods, which are techniques used to control clock signals These methods are used to reduce power consumption and improve the performance of circuit designs
The research scope of this project includes evaluating the performance of Clock gating methods on electronic circuits Performance evaluation methods will be used to measure power consumption, size, and operating speed of electronic circuits
Thesis Outline
The project will consist of 5 main chapters, details of each chapter include:
BACKGROUND
Overview of Low Power Technology
2.1.1 Introduction about Low Power Technology
The development of chip design has gone through over 20 years with various changes In the 1980s, the emergence of language-based design and synthesis increased productivity and enabled the design of circuits with millions of gates In the 1990s, the reuse of designs and the use of IP to design complex large-scale circuits were applied
In the following years, power-saving designs began to be considered to enable engineers to access complex SoC designs
There are three important factors that any chip design must consider: area, speed, and power consumption Each factor needs to be optimized to ensure that a design operates as efficiently as possible With the demand for modern designs, there is a need for more functions, smaller size, high speed, and minimal power consumption
2.1.2 Power consumption of logic inside a chip
The functioning of a chip's CMOS components is the main factor affecting its energy consumption When creating a system-on-chip design, the overall power usage can be divided into two categories: dynamic power and static power Dynamic power refers to the energy consumed during device operation when signals are frequently changing Static power, on the other hand, is the energy consumed when the device is powered but not actively processing any signals For CMOS devices, static power consumption arises from current leakage This project will concentrate on investigating dynamic power consumption
• 𝑃 𝑡𝑜𝑡𝑎𝑙 which is the total power consumption in the circuit
• 𝑃 𝑑𝑦𝑛𝑎𝑚𝑖𝑐 which is the dynamic power consumption
• 𝑃 𝑠𝑡𝑎𝑡𝑖𝑐 which is the static power consumption
The dynamic power consumption includes:
• Switching power consumption (𝑃 𝑠𝑤𝑖𝑡𝑐ℎ𝑖𝑛𝑔 ), is the energy required to charge or discharge power when the gate switches
• Short-circuit power consumption (𝑃𝑠ℎ𝑜𝑟𝑡 𝑐𝑖𝑟𝑐𝑢𝑖𝑡), is the energy consumed when a short-circuit current flows from the power supply to ground while both the pMOS and nMOS are on, or it can be said, while the CMOS is switching states
Switching power consumption is calculated according to the following formula:
• 𝛼 is the activity factor, and if there is only a single-bit switching 𝛼 = 1
• 𝑓 is the operating frequency of the switching
Using the above formula, the activity factor can be easily leveraged to reduce power consumption When a circuit is entirely deactivated, both the activity factor and dynamic power consumption are reduced to zero One approach to deactivating blocks
6 is to halt the clock signal, which is known as the Clock gating technique When a block is active, the activity factor is 1 for the clock signal, but it is lower for nodes inside the logic circuit
There have been many power-saving techniques developed over time, and they are all important techniques that help humans continually advance in the field of chip design Some commonly used techniques for reducing power consumption include:
❖ Clock gating: By turning off or reducing the clock signal of inactive logic gates, this technique reduces power consumption because there is no power switching activity in the turned-off gates
❖ Power Gating: This technique involves turning off or activating the power supply for active blocks in the circuit When a block is not active, its power supply is turned off to save power
❖ Multi-clock domain: This technique uses multiple clock sources, which can be synchronous or asynchronous, with different frequencies within a single circuit
❖ Multi-power domain: This technique provides different voltages to different logic components High voltage is only supplied to domains that require high processing frequency Domains that use lower frequencies can be supplied with lower voltages, which can significantly reduce power consumption
There are many other power-saving techniques that can effectively reduce power consumption in a circuit, but in this section, the focus will only be on the Clock gating technique Based on Clock gating designs, the team will analyze and compare the performance differences of each method within the Clock gating technique.
SYSTEM DESIGN
Design of a 4-bit Ripple counter circuit
A 4-bit Ripple counter circuit is a digital circuit that counts from 0 to 15 (in binary) using 4 T flip-flops Each flip-flop represents 1 bit and increases its value after each clock pulse, until it reaches 15 and then returns to counting from 0 This counter circuit is called a Ripple counter because the output of the previous flip-flop is used as the clock pulse for the next flip-flop
Figure 3.2 Block Diagrams of 4-bit Ripple Counter
The figure 3.2 shows the circuit diagram of a 4-bit Ripple counter using 4 T flip- flops The input signals to the circuit are a falling edge clock pulse and a high-level active reset signal, and the output is a 4-bit result that represents the count
The state table below for the 4-bit Ripple counter circuit shows that when the reset signal is at a low level, nothing happens However, when the reset signal is at a high level and the clock pulse is at a falling edge, the counting state starts
Table 3.1 Truth table of 4-bit Ripple Counter clk rst q[3] q[2] q[1] q[0]
The figure 3.3 above shows the circuit diagram for a T flip-flop using a D flip-flop and a NOT gate The circuit has two input signals: a falling edge clock pulse and a high- level active reset signal The design of the D flip-flop is based on the state table shown below:
Table 3.2 Truth table of Flip-flop D clk rst d q
Design of a Gate-based Clock gating circuit
This is the basic and easiest-to-use Gate-based Clock gating technique with abasic AND gate with two inputs is utilized for implementing clock gating One of the inputs is the clock signal of the circuit, whereas the other input is utilized to control the output
Figure 3.4 Gate based Clock gating
The figure 3.4 above shows an AND gate with two input signals: one input signal is used to control the output and is labeled as "en" (short for ENABLE), and the output signal is the gated clock labelled as "gated_clk" Because the AND gate is being used, it is not necessary to consider which edge the clock signal is triggering When the "en" signal is set to '1' and the clock signal is high, the clock signal is passed through to the designated circuitry
Figure 3.5 Schematic of Ripple Counter using Gate based CG
The 4-bit Ripple counter circuit will use the clock signal generated by the AND gate with a control signal as shown in the figure As mentioned in Chapter 2, the counter circuit has an input signal that is a falling edge clock pulse controlled by an AND gate
If a rising edge clock pulse is used instead, then some common issues with this Clock gating technique may arise
Figure 3.6 Example for fail case of Gate base CG
The "en" (enable) signal transitions from a low level to a high level on a rising edge and remains high until the next rising edge of the clock signal In the figure 3.6, due to the slower transition time of the "en" signal, the output may experience logic errors.
Design of a Latch-based Clock gating circuit
The Latch-based Clock gating technique is designed with a Latch and an AND gate The output Q of the Latch, along with the clock signal, will be the input signals for the AND gate to generate the clock signal that is supplied to the designated circuitry
Figure 3.7 Latch based Clock gating
The figure 3.7 above shows a Clock gating circuit based on a Latch with input signals including an "en" (enable) signal, a high-level active reset signal ("rst"), and a falling edge clock signal ("clk")
By using a Latch, the "en" signal can be held for clock gating, the "en" signal must remain stable from the active edge to the inactive edge of the clock signal As the Latch retains the state of the "en" signal throughout a complete clock cycle, it is only necessary for the "en" signal to be stable during the active edge of the clock signal
The figure 3.8 above shows a simulated waveform of a D Latch with a falling edge clock signal The issue with the Gate-based Clock gating technique is addressed in the Latch-based Clock gating technique, as the delay issue is handled by using a latch
Figure 3.9 Schematic of Ripple Counter using Latch based CG
As shown in the figure 3.9, the 4-bit Ripple counter circuit will use the input clock signal generated by the Latch-based Clock gating circuit instead of using the common clock signal of the design The design will be based on the previous circuit and then the performance of the Latch-based Clock gating technique will be compared with other Clock gating techniques.
Design of a Flip-flop based Clock Gating circuit
The Flip-flop based Clock gating technique is similar to the Latch-based Clock gating technique, but instead of using a D Latch, it uses a D flip-flop The Flip-flop
17 based Clock gating technique also uses a single D flip-flop with a falling edge clock signal and is used to control the clock signal that is supplied to the designated circuitry
Figure 3.10 Flip-flop based Clock gating
The figure 3.10 above shows a Flip-flop based Clock gating circuit with three inputs: an "en" (enable) signal, a high-level active reset signal ("rst"), and a falling edge clock signal ("clk"), similar to the Latch-based Clock gating technique The enable signal is used to control the output of the circuit, while the reset signal is used to reset the output to a known state The clock signal is used to trigger the flip-flop to capture the data on its input The output of the flip-flop is then used as the input signal for the
AND gate to generate the gated clock signal
Figure 3.11 Schematic of Ripple Counter using Flip-flop based CG
The figure 3.11 above shows a circuit design for a 4-bit Ripple counter that uses the input clock signal generated by the Flip-flop based Clock gating technique However, D flip-flops have a long sleep time and are susceptible to the same issues as the Gate-based Clock gating technique Additionally, due to a higher capacitance is needed for both charging and discharging, this circuit consumes significant power This, of course, affects the design and performance of the circuit As a result, there is an increase in area and the Flip-flop based Clock gating technique should not be used extensively
The actual area overhead of a gated clock gating technique compared to a flip- flop based clock gating technique depends on the specific implementation and design requirements For example, a gated clock gating technique that uses complex logic gates or requires additional routing resources may have a higher area overhead compared to a flip-flop based clock gating technique that uses simpler gating circuitry.
RESULTS AND EVALUATION
Results
4.1.1 The result of designing a 4-bit ripple counter circuit
The initial design of the ripple counter circuit would typically use a common clock signal for all flip-flops However, the performance of the circuit can be analyzed by comparing it with circuits that use clock signals generated using clock gating techniques
Figure 4.1 Top Level Schematic of 4-bit Ripple Counter
Figure 4.1 is the RTL schematic of the 4-bit Ripple counter Based on the operation of the signal is reset and clock pulse, the corresponding output is obtained
Figure 4.2 below is the RTL Schematic of the counter It shows a counter circuit composed of T Flip-flops and these T Flip-flops are composed of NOT and Flip-flop D gates
Figure 4.2 RTL Level Schematic of 4-bit Ripple Counter
The figure 4.3 below shows the waveform result of a 4-bit counter circuit The waveform result is completely accurate with the original design When the reset signal is at level '0', nothing happens When the reset signal is at level '1' and right before the falling edge of the clock signal, the counter starts counting up and when it reaches the highest value, it returns to counting from 0
Figure 4.3 Waveform Output of 4-bit Ripple Counter
The resulting waveform is completely accurate to the original design And get the information table about the power consumption of the counter circuit at the duty cycle of 1ns
4.1.2 The result of designing Gate based Clock gating
Figure 4.4 is the resulting Top-Level schematic of the counter using the clock generated by Gate based Clock gating There is an output of gclk because the operator wants to give the state of the clock to be initialized
Figure 4.4 Top Level Schematic of Counter using Gate based CG
Figure 4.5 is the RTL schematic of the circuit with 3 inputs clock (global), reset signal and enable signal (en) The clock is controlled by the AND gate based on the enable signal (en) which is then applied to the counter
Figure 4.5 RTL Level Schematic of Counter using Gate based CG
Figure 4.6 Waveform Output of Counter using Gate based CG
The simulation result shows the corresponding output waveform signals based on the input signals When using the 4-bit Ripple counter with a falling-edge clock signal, the glitches will be avoided, resulting in more accurate output signals
Figure 4.7 Example for fail case of Gate based CG
The figure 4.7 below is an example showing the logic error in the output of a counter circuit with a rising-edge clock signal.
4.1.3 The result of designing Latch based Clock gating
Figure 4.8 below is the Top-Level Schematic of a 4-bit Ripple counter using a clock signal controlled by Latch based Clock gating
Figure 4.8 Top Level Schematic of Counter using Latch based CG
Figure 4.9 RTL Level Schematic of Counter using Latch based CG
The figure 4.9 above is the RTL Schematic of the circuit By using Latches and an AND gate to manage the clock signal, the issues in Gate based Clock gating can be avoided The waveform result of the 4-bit counter using Latch based Clock gating is presented below The waveform shows the system design simulated equivalent to the input and output signals
Figure 4.10 Waveform Output of Counter using Latch based CG
4.1.4 The result of designing Flip-flop based Clock gating
Figure 4.11 Top Level Schematic of Counter using Flip-flop based CG
Figure 4.11 above is the Top-Level Schematic of the counter using Flip-flop based Clock gating
Figure 4.12 RTL Level Schematic of Counter Using Flip-flop based CG
Figure 4.12 is the RTL Schematic of the circuit This Clock gating technique uses 1 Flip-flop D and 1 AND gate to generate the clock for the specified circuit With input and output signals, the figure below is a waveform that describes the operation of the circuit
Figure 4.13 Waveform Output Counter Using Flip-flop based CG
The output waveform results are consistent with the design description After simulation, you will get a table showing the performance of the counter using Flip-flop based Clock gating at 1ns duty cycle
4.1.5 The result of designing New Gated Clock gating
Figure 4.14 Top Level Schematic of Counter using New Gated CG
Figure 4.14 above is the Top-Level Schematic of the counter using New Gated Clock Gating
Figure 4.15 RTL Level Schematic of Counter using New Gated CG
Figure 4.15 is the RTL Schematic of the circuit Using multiple logic gates is time consuming but very efficient in terms of performance And the resulting output waveform as shown below is equivalent to the input and output signals
Figure 4.16 Waveform Output of Counter using New Gated CG
The output waveform results are true to the original design description After simulation, you will get a table showing the performance of the counter using New Gated Clock Gating at a duty cycle of 1ns.
Compare Results
4.2.1 Power consumption without Clock gating technique
Tables 4.1 and 4.2 respectively are tables of information about power consumption parameters of elements such as Clocks, Signals and IOs and a summary table of two power parameters that are dynamic power and static power
Table 4.1 Power consumption of Counter without Clock gating
Without Clock Gate Clock Period Static Power Dynamic Power Total Power
Table 4.2 Power consumption of Counter without Clock gating
Without Clock Gate Clock Period Clocks Signals IOs Static Power Total
1ns 1.39mW 0.07mW 156.65mW 83.02mW 241.15mW
2ns 0.70mW 0.03mW 78.20mW 81.99mW 160.92mW
3ns 0.46mW 0.02mW 52.13mW 81.65mW 134.27mW
4ns 0.35mW 0.02mW 39.02mW 81.48mW 120.87mW
5ns 0.28mW 0.01mW 31.07mW 81.38mW 112.74mW
The total power consumption is calculated by adding the dynamic power and static power of the circuit Specifically, in the table evaluating the total power consumption, when the clock period is 1ns, the dynamic power is 158.13mW and the static power is 83.02mW, and when the clock period is 5ns, the dynamic power is 31.36mW and the static power is 81.38mW It can be seen that power consumption is inversely proportional to the clock period, specifically, the dynamic power decreases significantly as the clock period increases, while the static power decreases insignificantly
4.2.2 Power consumption with Gate based Clock gating
Below are tables of power consumption information of counters using Clock gating techniques
Tables 4.3 and 4.4 respectively are tables of information about power consumption parameters of elements such as Clocks, Signals and IOs and a summary table of two power parameters that are dynamic power and static power
Table 4.3 Power consumption of Counter with Gate based CG
With Clock Gate (Gate based CG) Clock Period Static Power Dynamic Power Total Power
Table 4.4 Power consumption of Counter with Gate based CG
With Clock Gate (Gate based CG) Clock
1ns 0.03mW 0.14mW 7.54mW 81.08mW 88.78mW
2ns 0.03mW 0.07mW 6.63mW 81.07mW 87.79mW
3ns 0.03mW 0.05mW 6.33mW 81.06mW 87.46mW
4ns 0.03mW 0.04mW 6.17mW 81.06mW 87.29mW
5ns 0.03mW 0.03mW 6.08mW 81.06mW 87.19mW
The total power consumption is calculated by adding the dynamic power and static power of the circuit Specifically, in the table evaluating the total power consumption, when the clock period is 1ns, the dynamic power is 7.70mW and the static power is 81.08mW, and when the clock period is 5ns, the dynamic power is 6.13mW and the static power is 81.06mW It can be seen that power consumption is inversely proportional to the clock period, specifically, the dynamic power decreases significantly as the clock period increases, while the static power decreases insignificantly
4.2.3 Power consumption with Latch based Clock gating
Tables 4.5 and 4.6 respectively are tables of information about power consumption parameters of elements such as Clocks, Signals and IOs and a summary table of two power parameters that are dynamic power and static power
Table 4.5 Power consumption of Counter with Latch based CG
With Clock Gate (Latch based CG) Clock Period Static Power Dynamic Power Total Power
Table 4.6 Power consumption of Counter with Latch based CG
With Clock Gate (Latch based CG) Clock
1ns 1.37mW 0.00mW 7.54mW 81.09mW 90.01mW
2ns 0.71mW 0.00mW 6.63mW 81.07mW 88.41mW
3ns 0.49mW 0.00mW 6.33mW 81.07mW 87.89mW
4ns 0.38mW 0.00mW 6.17mW 81.06mW 87.62mW
5ns 0.31mW 0.00mW 6.08mW 81.06mW 87.46mW
When the clock period is 1ns, the dynamic power is 8.92mW and the static power is 81.09mW, and when the clock period is 5ns, the dynamic power is 6.40mW and the static power is 81.06mW It can be seen that power consumption is inversely
32 proportional to the clock period, specifically, the dynamic power decreases significantly as the clock period increases, while the static power decreases insignificantly
4.2.4 Power consumption with Flip-flop based Clock gating
Tables 4.7 and 4.8 respectively are tables of information about power consumption parameters of elements such as Clocks, Signals and IOs and a summary table of two power parameters that are dynamic power and static power
Table 4.7 Power consumption of Counter with Flip-flop based CG
With Clock Gate (Flip-flop based CG) Clock Period Static Power Dynamic Power Total Power
Table 4.8 Power consumption of Counter with Flip-flop based CG
With Clock Gate (Flip-flop based CG) Clock
1ns 1.37mW 0.00mW 7.54mW 81.09mW 90.01mW
2ns 0.71mW 0.00mW 6.63mW 81.07mW 88.41mW
3ns 0.49mW 0.00mW 6.33mW 81.07mW 87.89mW
4ns 0.38mW 0.00mW 6.17mW 81.06mW 87.62mW
5ns 0.31mW 0.00mW 6.08mW 81.06mW 87.46mW
The total power consumption, when the clock period is 1ns, the dynamic power is 8.92mW and the static power is 81.09mW, and when the clock period is 5ns, the dynamic power is 6.40mW and the static power is 81.06mW It can be seen that power consumption is inversely proportional to the clock period, specifically, the dynamic power decreases significantly as the clock period increases, while the static power decreases insignificantly
4.2.5 Power consumption with New Gated Clock gating
Tables 4.9 and 4.10 respectively are tables of information about power consumption parameters of elements such as Clocks, Signals and IOs and a summary table of two power parameters that are dynamic power and static power
Table 4.9 Power consumption of Counter with New gated CG
With Clock Gate (NewGated CG) Clock Period Static Power Dynamic Power Total Power
Table 4.10 Power consumption of Counter with New gated CG
With Clock Gate (NewGated CG) Clock
1ns 0.04mW 0.46mW 7.54mW 81.08mW 89.13mW
2ns 0.04mW 0.23mW 6.63mW 81.07mW 87.97mW
3ns 0.04mW 0.16mW 6.33mW 81.06mW 87.59mW
4ns 0.04mW 0.12mW 6.17mW 81.06mW 87.39mW
5ns 0.31mW 0.10mW 6.08mW 81.06mW 87.28mW
The total power consumption, when the clock period is 1ns, the dynamic power is 8.04mW and the static power is 81.08mW, and when the clock period is 5ns, the dynamic power is 6.22mW and the static power is 81.06mW It can be seen that power consumption is inversely proportional to the clock period, specifically, the dynamic power decreases significantly as the clock period increases, while the static power decreases insignificantly
Evaluation
Figure 4.17 Power Comparison of Clock gating technique at clock period 1ns
The figure 4.17 above is a comparison chart of the dynamic power consumption of a counter circuit with and without Clock gating techniques at a clock period of 1ns
It can be seen that the dynamic power consumption decreases significantly when using Clock gating techniques This is because in the normal state, the clock signal changes state continuously, causing power consumption regardless of whether the circuit uses the clock signal or not, leading to high power consumption Conversely, when using Clock gating techniques, the circuit can only use the clock signal when necessary or allowed, thus significantly reducing power consumption
Figure 4.18 Power Comparison of Clock gating technique at clock period 5ns
Without CG Gate based CG Latch based CG Flip-flop based CG New gated CG
Without CG Gate based CG Latch based CG Flip-flop based CG New gated CG
The figure 4.18 above is a comparison chart of power consumption when the clock period is 5ns
In summary, through the design and comparison of Clock gating techniques, the advantages and limitations of each design depend on the specific requirements and usage The table below summarizes the characteristics of different Clock gating techniques:
Gated based CG Latch based CG Flip-flop based CG New gated CG Affected by glitches
Glitches are avoided High switching activity
Less area Large area Large area Large area
CONCLUSION AND FUTURE WORK
Conclusion
After evaluating the results and performance of Clock gating techniques, this topic has several advantages, including:
❖ In general, there is a specific evaluation of clock period, clock frequency, and performance of each Clock gating technique
❖ Based on existing designs to demonstrate clear information and operations
❖ Able to verify the correctness and integrity of the techniques
❖ Can only be simulated by software, unable to verify the correctness of the design by running it on a real FPGA kit
❖ In terms of design, it has not been designed on complex circuits to demonstrate the performance of the techniques clearly
❖ In addition, there are many more complex Clock gating techniques.
Future Work
To serve the purpose of learning, researching, and developing in the field of circuit design, the report suggests some directions for further development of this topic, such as:
❖ Further research on new Clock gating techniques Due to the continuous development of technology, new research may bring significant improvements in performance
❖ Implement real-world simulations on FPGA kits to provide a more comprehensive evaluation of system functionality and performance
❖ Apply real − world designs such as IoT, artificial intelligence, etc Because these fields also have constraints on performance requirements for efficient and power
[1] Neil H E Weste and David Money Harris, “CMOS VLSI Design - A Circuit and System Perspective”, 2011 - Fourth Edition, page - 181
[2] Mahendra Pratap Dev, Deepak Baghel, Bishwajeet Pandey, Manisha Pattanaik and Anupam Shukla, “Clock Gated Low Power Sequential Circuit Design”, VLSI Design Lab – Indian Institute of Information Technology, 2013
[3] Jagrit Kathuria, M Ayoubkhan and Arti Noor, “A Review of Clock Gating Techniques”, MIT International Journal of Electronics and Communication Engineering Vol 1 No 2 Aug 2001 pp 106-114
[4] Saurabh Kshirsagar and Dr M B Mali, “A Review of Clock gating Techniques in Low Power Applications”, IJIRSET – Vol 4, June 2015
[5] Michael Keating, David Flynn, Robert Altken, Alan Gibbons and Kaijian Shi, “Low Power Methodology Manual for System-on-Chip Design”, 2008
[6] Tamil Chindhu S and Shanmugasundaram N, “Clock Gating Techniques: An Overview”, Mahendra Engineering College – India, 2-3 March 2018
Code Gate based CG module GateBasedClockGating( output [3:0]q, input en, input clk, input rst ); and(gCLK,en,clk); ripplecounter rp1(q,gCLK,rst); endmodule
Code Latch based CG module LatchBasedClockGating( output [3:0]q, output gclk, input en, input clk, input rst ); wire out_latch; wire gCLK; dLatch dLatch1(out_latch,en,clk,rst); and(gCLK,out_latch,clk); ripplecounter rp1(q,gCLK,rst); assign gclk = gCLK; endmodule
Code Flip-flop based CG module FlipflopBasedClockGating( output [3:0]q, input en, input clk, input rst ); wire out_dff; dff dff1(out_dff,en,clk,rst); and(gCLK,out_dff,clk); ripplecounter rp1(q,gCLK,rst); endmodule
Code NewGated based CG module NewGatedClockGating( output [3:0]q, output gclk, input en, input clk, input rst ); wire cclk; wire x; wire out_latch; wire gCLK; dLatch dLatch1(out_latch,en,cclk,rst); xnor(x,en,out_latch); or(cclk,x,clk); and(gCLK,out_latch,clk); ripplecounter rp1(q,gCLK,rst); assign gclk = gCLK; endmodule