nghiên cứu thuật toán điều khiển thích nghi luồng tham chiếu để nâng cao tốc độ cho các hệ xử lý song song chuyên dụng bản tóm tắt tiếng anh

MINISTRY OF EDUCATION AND TRAINING THAI NGUYEN UNIVERSITY CHU DUC TOAN STUDY ADAPTIVE CONTROL ALGORITHMS WITH REFERENCE FLOWS TO IMPROVE THE SPEED OF SPECISLIZED PARALLEL PROCESSING SYSTEMS Major: Control Engineering and Automation Code: 62.52.02.16 SUMMARY OF ENGINEERING THESIS THAI NGUYEN - 2013 This work has been published in: Thai Nguyen University Instructor(s): Ass Prof Dr Do Xuan Tien Ass Prof Dr Nguyen Huu Cong Defender 1: Defender 2: Defender 3: Thesis will be defended at supervisory board at university level meeting at …………………………………………………………… At hour, ….date month year This thesis can be found in the library: Library of Industrial Engineering University - Thai Nguyen University; Learning materials Center of Thai Nguyen University, National Library of Vietnam nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh SUMMARY OF THESIS The necessary of the topic Many new areas such as computer graphics, artificial intelligence, number analysis, parallel calculating in the petroleum industry, the unmanned equipment, equipment of identifying monitoring mobile targets , require to process very large volumes of data with high speed Most of this problem, the sequential computer does not meet the actual requirements Research on parallel processing systems now focus two main researching directions are as follows: The one is to study multi-processor systems as supercomputers (Suppercomputer) [45], [54], large computer (Mainframe), minicomputer (minicomputer) make versatile: the hardware structure and software function of the computer that must be multi-functional organized are complex Mathematical model is very complex, beyond ordinary calculating structure Therefore, when applied to specialized applications, their processing speed is often slower than the ability of the micro processing; real-time parameter is not controlled correctly Parallel multi-processing system has a big scale together with operating structural software is very complicated Therefore, the computer system has a very expensive price This is a difficult problem to solve specific problems required high speed, low cost consistent with economic conditions in Vietnam The second is to study parallel multi-CPU processing system such as: parallel-specialized processing system for one or one class of specific math, the same function Therefore, manipulation methods, nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh structure of data group need to be processed; the structure of resulting data are defined before, so it is more easy to decompose functions , easy to select data organization and appropriate processing methods with speed requirements With specific tasks and defined data structures, the optimal processing algorithm can be made, appropriate hardware structure, utilizing system resources reasonably Due to the function of parallel specialized processing systems is limited and explicit, the Monitor program is built in the most optimal, highly scalable and more importantly is to response fast requirements of operational processes in the system Through the above analysis, the thesis selects the second direction that is parallel-specialized multi-CPU processing system In parallel specialized multi-CPU processing system, shared storage space (SSS) is very important: the storage of the database to be processed, the operating program When many reference flows accessed to shared memory at the same time that can lead to conflict, then the system may hang or low access speed, the performance of shared memory is reduced and does not meet the speed requirements of this problem The importance of SSS is the control set of reference flow On that basis, the problem to be solved is to synthetic the structure of adaptive controlling of reference flow to SSS to minimize the probability of conflicts when accessing shared resources, improving computing speed is very important From the above analysis, the research poses the problem for parallelspecialized multi-CPU processing system met the fast and reliable processing speed, reasonable price is very necessary and as a basis to form thesis’s topic: "Study adaptive control algorithms with nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh reference flows to improve the speed of specialized parallel processing systems” Object and scope of research - Object of the thesis is SSS in parallel-specialized multi-CPU processing system - The researching scope of the thesis is the limitation in making the mathematical model in reference flow to SSS in parallel-specialized multi-CPU processing system; specify the binding conditions between these parameters and the changeable parameters to synthesize optimal controlling system (adaptation) in reference flow to SSS to improve the efficiency and reduce the probability of conflicts when accessing shared resources The researching method of the thesis - Based on the classic theory as a queuing theory, probability theory namely Morkov process stops, distributes Poat-xông to build and calculate the performance for reference mathematical model to SSS in parallel Multi-CPU processing system - Describe mathematically model of shared memory in the parallel multi-CPU processing system - Study to control the system by using emulation and practical technology that is FPGA modern technology The scientific meaning and practice of the thesis 4.1 In the science nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh The scientific meaning is to study and apply the optimal controller (adaption) in reference flow to SSS for parallel-specialized multiCPU processing system to improve the performance, the speed, and minimize the probability of conflict when accessing shared resources 4.2 In the practice The research result will be references for students and graduate students as well as researchers interested in research on multi-CPU parallel processing dedicated From the results of this research, topic as the basis for many further studies aimed to apply widely the parallel-specialized multi-CPU processing system in the practice in Vietnam, especially the system has high requirement for speed The structure of thesis The thesis consists of three chapters namely explanation, conclusion and references Chapter Architecture of parallel multi-CPU processing system 1.1 System Resources 1.1.1 Hardware Resources 1.1.2 Software Resources 1.2 The definition of parallel processing system 1.3 Classification of parallel processing system nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh - Michel J.Flynn gave architecture models of parallel processing system are: (i) SISD model, (ii) SIMD model, (iii) MISD model, (iv) MIMD model - Handler classifies parallel processing system based on parallel level and processing level according to the pipeline mechanism of the hardware structure 1.4 Overall architecture of parallel multi-CPU processing system 1.4.1 Model 1.4.2 The issues related to performance 1.5 The architecture of parallel- specialized multi-CPU processing system 1.5.1 The characteristics of parallel- specialized multi-CPU processing system a Specialized function Specialized function is also reflected in the data structure that the system must process This data structure is largely the vector data due to the similar structure of elements and they are arranged in the order (such as the structure: range-azimuth-height) that allows to vector easily the basis of this data The consequence is to perform data processing operations as the pipeline mechanism easily - a mechanism to improve the performance of processing system b The structure of minimal hardware nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh Due to parallel- specialized processing system performs a defined task and this task is established only in a math class so structural parameters must be determined quite accurately As a result, the hardware organization will ensure minimal with standard partitioning algorithm c The high speed and performance d The high reliability This is a requirement, as well as a characteristic of the parallelspecialized processing system At first view, it seems to conflict to the requirement of high speed’s system However, unlike generalpurpose computers, parallel-specialized processing system is largely the system which is difficult to maintenance, even impossible to maintenance (such as processing systems mounted on satellites, on the self-led missile, or in the early warning system under the sea ) so it must require high reliability 1.5.2 The architecture of parallel- specialized multi-CPU processing system a Model of parallel- specialized multi-CPU processing system b These factors affect the performance of parallel- specialized multi-CPU processing system c Branch instruction 1.6 Commentary, research-oriented of the topic nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh Through the analysis and introduction about parallel multi-CPU processing system and parallel- specialized multi-CPU processing system in section (1.4) and (1.5) With parallel - specialized multi-CPU processing system, the performance largely depends on the accessing speed into common resources, but the most importance is SSS because the highest possibility of conflict is here (because the frequency of using SSS is much higher than other resources such as I/O port, peripherals ) One of the tasks of the synthesis stage of the system is to minimize the possibility of conflict in reference to SSS of CPU unit that is a critical task For example, the monitoring system of aircrafts The aircrafts are such as: (i) at different distances (ii) the speed is also very different The parameters must be monitored for an aircraft: (i) distance (ii) azimuth and (iii) height, when the parameters are controlled, we are able to draw the flying orbits Then we can make other decisions (to kill, not to kill ) nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh Outermost range doughnut N1024 Range doughnut N1023 Range doughnut N1 U Surge generator 375 Hz Pulse reflection from the target on theother ranges other range t t The cycle of pulse Figure 1.14: Observation distance of the system - The situation of researching in the country: The researching of "Solving level problem for Radar intelligence information” scientific research at the level of Department of Defense, Dr Nguyen Van Lien (2008-2012) nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh 10 adaptive controlling of reference flow to SSS to minimize the probability of conflicts when accessing shared resources On the basis of preliminary studies of parallel-specialized multiCPU processing system, in Chapter the thesis will study farther, analysis, make mathematical model refer to SSS Chapter Making mathematical models refer to common memory in parallel multi-CPU processing system 2.1 Theoretical Basic To build the mathematical model for optimal controlling mechanism of reference flow in parallel-specialized multi-CPU processing system based on the requirements of the functional processing system described in chapter that was done with SSS, the thesis need to use: - Queuing theory is used to describe the n reference flow to SSS with queuing mechanism at the entrance / exit - Probability theory, namely the Markov process is used to uniform referring mechanism of n reference flows to SSS with synchronization mechanism in the operation of the parallelspecialized multi-CPU processing system That means the state of the system established after clocking the system Moreover, there used stopping Markov process only to confirm that the future state of the system depends only on the current state of the system (which does not depend on the previous states) - Use the distribution of the reference to SSS of the parallelspecialized multi-CPU processing system that is Poat-xong nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh 11 distribution: The parallel- specialized multi-CPU processing system has good disintegrate in functions so the time for reference is much less than the time for working in single-CPUs system of the system 2.2 Building mathematical model referenced the shared memory in parallel multi-CPU processing system 2.2.1 The traditional reference model to the shared memory in parallel multi-CPU processing system MUX Control Shared memory + Address channel + Controlling channel Figure 2.1: Refering the shared memory in parallel processing system 2.2.2 Building the improved reference model to the shared memory in parallel multi-CPU processing system To build a mathematical model, the thesis determined from the definitions of the performance E The E-assessing performance is defined here as the ratio of: E  N acc / N acc0 In which : Nacc - Total number of successful reference nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh 12 Nacc0 - Total number of reference launched by the system If we call the probability of reference to SSS as E to ensure referring successfully, we need 1/ E test Call P is the probability of the entrance reference registers is unoccupied (P is the conditional probability of entrance register is unoccupied), even when you are Q =1- P To refer successfully, we need 1/E1 test with a conditional probability P (E1 – the performance of entrance reference register is unoccupied) The probability of occupied entrance reference registers is - P to ensure a successful reference, we need 1/Ep test (Ep – The performance of busy entrance reference register) So we turn to the problem of conditional probability, with a relationship: N acc 1  P Q  N acc0 El Ep E The expression of performance is rewritten as follows: E El E p PE p  QEl (2.1) This is a mathematical model to determine the performance of shared memory’s architecture with a buffering as role of queuing at the entrance and exit of the physical memory module To determine this model and appear controlling parameters, we need calculate three components: (i) P – the probability of unoccupied entrance reference register, (ii) Ep – The performance of occupied entrance reference register, (iii) El - The performance of unoccupied entrance reference register These quantities are complex and highly dependent on parameters related to the system’s structure nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh 13 2.2.2.1 Determine the quantity P - Probability for entrance reference registers unoccupied - To examine P we need to model the entire process of referring CPUs to the shared memory On the basis of queuing theory model [4], [46] described in Picture 2.2.a, combined with the characteristic of parallel-specialized multi-CPU processing system, can see the architecture of shared memory as a system consisting of k independent queues according to M/D/1/m rule That means: the reference process to the shared memory is the Poission process and Markov distribution (M), the service life of the memory is determined (D); memory space for references is and queue size of each memory module is m - The probability of unoccupied entrance reference register will be determined: m P  PN i  n n0 m  1    n n i  e i  1 n 0 i 0 i  n i 1 i  n  1 n  i ! (2.15) 2.2.2.2 Identify Ep - The performance when the queue of memory modules is full Considering the case of the performance when the queue of the memory modules is full: When launching a reference from any single CPU, there is still the probability served (reference with certainly successful probability) So we compute Ep when the memory module is full, Ep is calculated as follows: nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh 14 EP  2q (2.18) 2q    2nq TP (TP  1) / b 2.2.2.3 Identify El – The performance of unoccupied entrance reference register Considering the performance when entrance reference register into unoccupied memory: When launching a reference, an unsuccessful probability still exists So we need to calculate El (the performance when entrance reference register into unoccupied memory), is calculated as follows: each flow reference will be in one of three states: (i) Free state; (ii) Reference flow state implementing will be successful; (iii) Reference flow state implementing will be successful Supposing there exists quantities: q - the probability that a free reference flow initials a reference;  - the probability that a free reference flow;  - the probability of reference flow made successful reference;  - - the probability of reference flow made unsuccessful reference;  - the probability to refer successfully  2q  q  (1  2q  q )  4q(1  q ) (2.25) El    2(1  q) 2.3 Conclusion of Chapter In Chapter 2, the thesis solved the following issues: - Having built a mathematical model referring to SSS for parallelspecialized multi-CPU processing system, binding parameters can be calculated and controlled as the queue size m, b nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh 15 - Mathematical model (2.1) will be used in Chapter in building the system with adaptive controlling of reference flow to SSS for parallel-specialized multi-CPU processing system Chapter Simulation and controlling model 3.1 Building simulation software 3.1.1 Building the main simulation software module Figure 3.1: Software interface calculating the performance of the multi-CPU processing system 3.1.2 Building software module calculating the performance of the multi-CPU processing system in relation to the Tc shared memory’s cycle Figure 3.2: Software interface calculating the performance of the multi-CPU processing system in relation to the Tc shared memory’s cycle nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh 16 3.1.3 Building software module calculating the performance of the multi-CPU processing system in relation to the number of reference number n Figure 3.3: The software interface calculating the performance of the multi-CPU processing system in relation to the number of reference number n 3.1.4 Building software module calculating the performance of the multi-CPU processing system in relation to to the Tc shared memory’s cycle with values ρ = 0.5 Figure 3.4: The software interface performance calculating the performance of the multi-CPU processing system in relation to to the Tc shared memory’s cycle with values ρ = 0.5 3.2 Survey and evaluate the performance of controlling model by simulation nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh 17 Using the software program has been built and surveyed the performance of system according to the relationships established, we have the correlation graph among them The results are as follows: Logic memory model consistent with the results from scalar simulation to achieve the performance which is over 0.6 In particular, when T = Tc = 16, the simulation result without queue (m = 0) the result is 0.27; and the performance is 0.65 when using the queue E 0.8 0.6 0.4 0.2 Mơ hình Bailey (m=0) m=2 11 T 13 15 17 19 21 Figure 3.5: Efficiency of random reference of logic memory bandwidth according to T is compared in the two cases when m = and without logic memory bandwidth (m = 0, Tl = Td = 0) Figure 3.6: The dependence of E according to the physical cycle of Tc memory modules when m changes nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh 18 E E 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 m=6 m=4 m=2 m=0 0.2 0.0 m=6 m=4 m=2 m=0 0.2 n 10 15 20 25 30 35 40 45 n 0.0 50 10 15 a) 20 25 30 35 40 45 50 b) Figure 3.7: E graph according to the number of reference flow n a) Tc = 10, b) Tc = According to the survey‘s results, the more the performance increased, the more the queue’s size increased However, we can not design the buffering with too big size, because after writing data only a few cycles referenced may be asked to read data immediately So if the larger queue’s size is, the longer the waiting time for writing to memory and other reference flows can misread data 1.0 0.8 0.6 m=6 m=4 m=2 m=0 0.4 0.2 0.0 Tc 10 15 20 25 30 35 40 45 50 Figure 3.8: Egraph according to physical cycles of Tc memory modules while keeping fixed ρ = 0.5 With a system composed n reference flows, l logical memory bandwidths, Tl =1, m= 4 and q=1.0 (full loading) To achieve the performance E> 0.90 with   0,1 , with m =2, need to choose  open-circuit 111-> nothing Input D2 Output D1 001 Output D2 Input D3 Input in next 010 011 100 101 Output D3 110 Order of controlling code pipe floor Step Step nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh Step nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh 22 3.6 Conclusion of Chapter Chapter has solved the following problems: - Develop algorithms, simulation diagram in the Delphi environment - Take out the simulation results showing that in the case of a mathematical model referring to SSS when not using buffering of queue’s size m have lower performance than the case of using the buffering of in/out queue’s size m # - Size of m is an important parameter to optimize the structure of memory according the problem class, parallel multi-CPU processing system will have not only high performance but also high reliability That is the basis for adaptive controlling structure Now size of m will be a function of the reference’s frequency of the system into SSS If you use more structures to detect and determine the frequency of accessing, it will be controlled to change queue’s size of FPGA’s structure for the memory bank to match this frequency Conclusions and recommendations The conclusions: Parallel multi-CPU processing system is increasingly widely applied in many fields, including civil and military With advanced engineering and technology currently, designing studies’ towards of parallel-specialized multi-CPU processing system has highperformance, optimal and flexible structure with class of application problem, is a correct direction The process of researching thesis has contributed new issues as follows: - Have been found and proven mathematical model allowing us to identify the accessing performance of the shared memory of parallelspecialized multi-CPU processing system as a function of memory cycles and indicates the in/out queue’s size m and the other parameters involved - The obtained results allow to calculate the configure of shared memory in parallel multi-CPU processing system It also pointed out that the more the queue m increases, the less E performance is and it is dependent on the number of reference flow that means we can increase the number of CPUs up to multi-processing systems to solve the problem of large numbers such as problems with large databases nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh 23 but high designate coefficients Using technical solution to resize queues m by FPGA technology to suit every math class - Gather the results of the thesis is used as a supporting tool for integrated design for parallel-specialized multi-CPU processing system, to meet practical requirements The technical solutions given are feasible and the advanced technology allows to implement Recommendations Stopped in the dissertation new model adaptive control system as a parameter is the queue size m should be flexible and yet highly flexible So further research directions of the thesis is to integrate a number of other parameters in adaptive control mechanisms such as duty cycle of Tc memory, memory bandwidth numbers of KGNDC b nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh nghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anhnghien.cuu.thuat.toan.dieu.khien.thich.nghi.luong.tham.chieu.de.nang.cao.toc.do.cho.cac.he.xu.ly.song.song.chuyen.dung.ban.tom.tat.tieng.anh