Giáo trình kỹ thuật lập trình plc

NGO THANH QUYEN (Chu bien) - NGUYEN ANH TUAN Giao trinh ,,,., - - ,, KY THUAT LAP TRINH • • PLC TRUONG DAI HOC CONG NGHt~P Tf'.HC~ NHA xuAT BAN D~I HQC CONG NGHIE:P THANH PHO HO CHI MINH Loi n6idau Liri n6i d~u Nh& l?i thoi toi dang hQC d?i hQC va sau tnrang giai do di~u khi~n logic kha trinh muc d(> don gian va rfrt h?n ch~ K~ tu nam 2003 cho d~n nay, b(> di~u khien logic kha trinh dugc su dµng hfru nhu tfrt ca cac linh vi,rc khac d?ng hay d?ng khac, d~ dap ung dugc xu th~ phat tri~n chung, hiu h~t cac truang d?i h9c xem b(> di~u khi~n · logic kha trinh la mon h9c cho sinh vien nganh di~n d~c bi~t khong th~ thi~u cho sinh vien di~u khi~n ti,r d(>ng D~ phµc vµ cho vi~c dao t?o ben canh trang thi~t bi phfrn cung, giao trinh la m(>t phfrn khong th€ thi~u qua trinh dao t?O Cho d~n nay, rfrt nhi~u giao trinh dugc xufrt ban nhfim cung dp cho nguai hQC cai nhin toan di~n v~ ly thuy~t, l~p trinh (mg dµng thi,rc t~ C(J ban va nang cao Nhin chung hiu hSt cac giao trinh chu cung dp cho nguai d9c cac ki~n thvc lien quan v~ kSt n6i, l~p trinh di~u khi€n cho·tirng hang PLC khac chfing h?n nhu Siemens, Mitsubishi, ABB, Schneider, V &i each ti~p c~n nay, uu di€m giup nguoi d9c co th€ d~ dang ung dµng hang PLC da gi&i thi~u vao ung dµng thi,rc t~ Tuy nhien, v&i each ti~p can se khong cung dp cho nguai d9c co cai nhin toan di~n v~ ly thuy~t, ung dt,mg thvc t~ v~ tfrt ca cac khia c?nh chung c~a PLC va cac thi~t bi lien quan Trong giao trinh nay, chung toi mu6n cung dp cho nguoi dQC co cai nhin t6ng quan v~ tit ca cac khia c?fih lien quan v~ PLC chfing h?n nhu: t6ng quan, du true phk cung, S(J d6 k~t n6i giao ti~p ngon ngfr l~p trinh va t~p l~nh cua PLC theo tieu chu.ln IEC Cu6i cung d€ cho nguai dQc hi€u ro them ung dµng cµ the cua PLC thong qua hai hang thong dµng Mitsubishi va Siemens thong qua vi dµ va hinh anh minh hQa cv th~ 0€ co giao trinh la m(>t trai nghi~m nhi~u nam linh vµc giao dµc, h9c hoi nhfrng tai li~u nu6c va nu&c ngoai cua nhfrng nguai tham gia Vi vfry chung toi mu6n cam an cac cong ty va cac tac gia da giup cho chung toi co cu6n giao trinh horn nay: Tai li~u dugc cung cfrp bai PLC hang Mitsubishi, Siemens, d~c bi~t tac gia Luis Bryan va Eric Bryan da cho phep chung toi su dµng m(> phin tai nguyen Programmable controllers: theory and implementation Chung toi hy v9ng rfing cu6n sach la m9t cong cµ hQc t~p va tham khao guy gia Chung toi da c6 gAng trinh bay m(>t each co th~ d~ hi~u nhfrt, nhien, v6i sv thay d6i khong gi&i h?n M th6ng dieu khi~n, chung toi chAc chAn khong th~ cung dp diy du cac ung dµng PLC Chi b?n, dugc trang bi ki~n thuc thu dugc qua cu6n sach nay, m&i co th~ kham pha gi&i h?n thµc sv cua b◊ dieu khi€n logic kha trinh ii Loi n6idau Lam th~ nao ll~ sfr d~1ng cufm giao trinh Chao mung b~ d~n v&i B(> dieu khi~n c6 th6 l?p trinh: Ly thuy~t va Tri~n khai Tru&c b va dugc tai su dµng d\l' an bi lo?i bo ho~c ma r9ng M~c du cac chuc nang cua PLC nhu: t6c d◊ ho?t d9ng, giao ti~p va kha nang ly dfr li?u da dugc cai ti~n nhiSu nam, nhung cac y~u t6 ky thu~t co ban cua PLC v~n dm;rc gifr nguyen nhu ban dAu, d6 la: d~ SU dµng, lAp d~t, bao duong va v~n hanh xu 1.2.3 B9 diiu khiin kha trinh Nhi~u ti~n b◊ cong ngh? nganh cong nghi?p di~u khi~n l~p trinh duqc 'ti~p tµc phat tri~n cho t&i Nhfrng ti~n b9 khong chi cai ti~n thi~t k~ b◊ diSu khi~n l~p trinh, ma la each ti~p c~n m&i d~ ki~m soat du true h~ th6ng Thay d&i bao g6m ca ph!n cung (cac phfrn v~t ly) va phfrn m~m (chuong trinh diSu khi~n) Sau day la m◊t s6 cai ti~n phfrn cung gfrn day cua PLC: • Thai gian quet nhanh hon bAng each su d\lllg vi xii ly m&i, tien ti~n hon va ung dà!}g cac cong ngh? di~n tu ã Ca~ PLC nho, chi phi th~p dugc minh hQa a hinh 1.2, c6 th~ thay th~ d~n 10 role, c6 nhi~u kha nang hon so vm tm6c day • Cac Mo-dun· ngo vao/ra (1/0 - Input/Output) (xem hinh 1.3) cung dp cac giai phap hi~u qua vm chi phi thip (cac mo-dun 1/0 nho lam giam di~n tich) • Cac mo-dun I/0 thong minh, d\lllg b9 vi xu ly mm Cac tinh nang di~n hinh bao g6m PIO (ti l~ - tich phan - vi phan), M?Ug, CANbus, fieldbus, giao ti~p ASCII, dinh vi, may tfnh luu trfr va cac mo-dun ngon ngfr (vi dà Basic, Pascal) su ã Cai ti~n thi~t k~ co bao g6m vo b9c I/0, cac module mo rc)ng • Giao ti~p d~c bi~t cho phep cac thi~t bi khac k~t n6i tf\l'c ti~p v6i b◊ di~u khi~n Cac thi~t bi di~n hinh bao g6m cac c~p nhi~t di~n, b◊ l\l'C va dAu vao dap ung nhanh cua b◊ d~m t6c d◊ cao (Hight speed counter) • Phin cung va giao di~n di~u hanh 265 Ph1,1 /1,1c 1: System Programming and Implementation 4011 High limit alarm decimal °C 4100 4101 4102 Analog input counts (temperature) Used in multiplication temp result Result temperature in °C Table Internal output assignment Device Internal Description 1000 1001 1002 1003 1004 1005 1006 1007 1010 11 00 Xfer in TWS (MUX) enabled (TWS Read BCD-to-binary conversion enabled (BIN Done Xfer in analog input enabled (Temp Read Compare temp with low alar Low alarm condition (Temp < Low Low temp alarm PL Compare temp with high alar High alarm condition (Temp > High High temp alarm PL Subroutine to check for valid ranges (CMP for Low Low temp input more than 10 °C Compare for high range (CMP ~or High High temp input less than 85 °C Range OK, = Range not Go to subroutine to linearize input counts t °C Addition of 500 enabled-reg 4102 has temp val 1101 11 02 11 03 11 04 1200 1201 Table 1/0 address assignment 1/0 Address Module Type Input Output Egister Input (Low byte) Rack Group Terminal 0 0 0 0 0 0 0 0 0 0 I I I I Description Start analog reading and TWS input Not used Least significant two digits oflow alarm and high alarm set points; register multiplexes in both inputs - 266 Phu !'l,lc 1: System Programming and lmplementalion 0 0 Egister Input (High byte) 0 0 0 0 Output 0 0 Analog Input 0 0 1 I I 2 2 2 2 ,.,_, _,,., _,,., ,.,_, I ,.,_, 7 7 ,.,_, Most significant two digits of low alarm and high alarm set points; both are multiplexes in Low alarm PL indicator High alarm PL2 indicator Channel I analog input temp Channel Spare Channel Spare Channel Spare 267 Phl,l il,lc I : System Programming and Implementation St art 000 XFER I N TWS Read 1000 ~ -1 Slot I Rack Length Reg 4000 T WS Read 1000 BCD-BIN ~ -1 B IN Done 1000 Range OK 1104 -l Check TWS Ranges Go Sub 1100 Rang OK 11 04 Temp Read 1002 Rang OK 11 04 XFERIN Temp Read 1002 Reg 40 I >= Reg Kl 00 Reg 40 11 = l 00oCTWSes Virtual Posi110f1 !V P.! Counts +4095 Virtual Position 6:~:fi'.~.fi·~E'.tJ TWS @ Start PB -L (-0 ( r ) @ @ Reset PB -L (-0 Cr) Stop PB (-a LO-) Djch chuy~n (inches) Ycounts = mX + b -4095 Ycounts = I90xXcoun1/ 20 - 4095 Ycounts = (4095)x(I 0· )Xcounts - 4095 Figure 12 LVDT nalog position reading system When the start push button starts the machine, the moving piece must move to the virtual starting position (Y.P.) defined by the set of 4-digit TWS The TWS settings range from 00.00 to 20.00; the decimal point will be implemented in the controller When the machine finishes its cycle, the moving piece must return to the virtual position The machine cycle may end at either side of the virtual starting position Figure 13 illustrates the flowchart for this system, while Tables 9, 10, and 11 show the I/0 address assignment, register assignment, and internal assignment, respectively Figure 14 presents the PLC program solution for this example 269 Ph1;1 l1;1c 1: System Programming and Implementation START Read LVDT analog input continously Go back to V.P after end of machine cycle If stop is pushed, stop NO all machine activity If reset is pushed, stop activity and go back to O' position GO SUB to ensure that position is at O inches END Once at Oinches then go to V ,P Read TWS and convert to counts After V.P is read, start machine cycle Issue end of cycle Figure 13 Flowchart of the L VDT reading and virtual position calculations Table 1/0 address assignment 1/0 Address Module Type Input Egister Input (High byte) Rack Group Terminal 0 0 0 0 0 0 0 0 Egister Input (Low byte) 0 I I I I I I I I 2 Description Start analog reading and TWS input I I Most significant two digits ofTWS channel I (virtual position in decimal points) Least significant two digits of TWS channel I (virtual position in decimal points) Phu 17,iC I: System Programming and Implementation 270 0 0 0 0 0 0 0 Output Analog Input 2 2 2 ,., ) ,., ) 3 7 7 ,., ) I I Forward command Reverse command Channel LVDT analog input Channel Spare Channel Spare Channel Spare Table 10 Register assignment Register 4000 4001 4002 4003 4100 Description TWS value in BCD; virtual position TWS value in binary after conversion Subtraction of 4095 (-4095) Virtual position in counts (equation) LVDT analog value in counts Subroutines are used to implement the flowchart, to facilitate interlocking and programming Latch instructions enable the subroutines, allowing the program to go to a subroutine until its operation has been performed Once a subroutine finishes its function , it sends an unlatch signal signifying the end of the subroutine This unlatch signal triggers the execution of the next subroutine Table 11 Internal output assignment Device Internal Description 1000 1001 1100 1150 1151 1152 1153 1200 1250 1251 1252 1253 1254 1255 1256 1257 Start machine command LVDT analog input established (LVDT Read) Latch for enable to go to subroutine Compare LVDT position with O inches Position reached-0" position Energize reverse motor command from this sub One-shot position O" found Latch to enable to go to subroutine (TWS Read) Read TWS block enable (TWS Read Sub) Convert output from BCD to binary (decimal) Multiply (according to equation) enable Subtract enabled Compare enabled V.P found-1254 ON (Pos ::: V.P.) Energize forward motor from this sub One-shot position V.P found Latch to enable to go to subroutine to return to V.P Compare LVDT with V.P (:::)-Return to V.P sub (Pos Ph1:1 l1:1c 1: System Programming and Implementation 1300 1350 1351 1352 1353 1354 1355 1356 1357 1360 1361 1362 1400 1700 1750 1777 271 > V.P.) Position~ V.P.- reverse motor (Ahead of V.P.) Compare LVDT with V.P (:S) (Pos < V.P.) Position :S V.P.-forward motor (Behind V.P.) Latch found V.P from Pos 2: V.P (Reverse ahead of V.P.) One shot found V.P from reverse Latch found V.P from Pos :S V.P (Forward behind V.P.) One shot found V.P from forward Reverse motor from this sub Forward motor from this sub One shot found V.P from :Sor from ~ after cycle Latch a reset to go to sub for O" position after reset Latch to go to machine cyc le Go sub machine cycle End of cycle signal (Cycle Done) Figures 15, 16, and 17 present the subroutine codes In Figure 15 (check for 0-inch position), the compare instruction checks for the L VDT count to be less than or equal to the compare constant -4090, rather than strictly equal to the value -4095 If the instruction checked for the value to be strictly equal to -4095, then fluctuations inherent in the LVDT's count output could cause the PLC to not latch this value So, once the LVDT passes -4090 counts, it latches this value and assumes that the position is at O inches In Figure I 6, scale multiplication allows the virtual position, which has two dec imal points (I 0-2 ) to be multiplied by the multiplication constant (4095 x 10- = 409.5); thus, the final scale is 10-3 _ This routine allows the motor to move the part to the virtual position as specified by the LVDT Once the virtual position has been reached, the system is ready to start the machine cycle (one-shot output 1257) The machine cycle subroutine will return an end-of-cycle signal (output 1777) when fini shed, which disables the cycle subroutine (see Figure 14) When the end of cycle has occurred, the PLC will tell the motor to move either forward or backward, depending on the moving part position at the end of cycle The interlocking performed by output rungs 1354 and 1355 (refer to Figure 17) allow the motor to move in reverse if the patt is farther than the virtual position (current position > V.P.) Rungs 1356 and 1357 perform the opposite function if the position of the part is c loser than the virtual position (current position < V.P.) The one-shot circuits used in the LVDT application prevent the system from mov ing the motor fonvard or backward until the part is at exactly the virtual position in counts Analog count signal s may jump one or two counts in e ither direction (up or down) This can result in instability, causing the forward and reverse signals to clash The logic that is employed in this subroutine will detect, once the part crosses the virtual position (one-shot outputs 13 55 and 1357 in Figure 17), whether the part is coming from a reverse motor or forward motor operation Once the part is detected (i.e., when the one-shot is triggered), a minor jump in analog counts w ill not affect the operation, since the program has a lready determined that the part has just passed the virtual position After the part stops at the virtual position, both the fonvard and reverse motor commands from the subroutine are inhibited Phu h,Jc 1: System Programming and Implementation 272 Start 000 Stop 001 Start Mach 1000 Reset 002 Start~ 100µ XFERIN Start Mach 1000 Enable GO SUB 1100 Rack Slot Reg 100 Length LVDT Read 1001 Enable GO SU B 1100 C MPLVDT=O' GO SUB 1150 Stop 001 Reset 002 Back to V P 1300 Cycle Done 1777 Sub Return to V P GO SU B 1350 Back to V.P 1300 Disable Sub 1100 Found V.P After Cycle 1326 0' Found 1153 Stop 001 Stop 001 Reset 002 Reset 002 Enable Read TWS Sub 1200 0' Found 1153 Enable Read TWS Sub 1200 At V.P Ready 1257 Read TWS Sub GO SUB 1250 Deactiva te 1100 Stop 00 Go to 0' after reset 1400 Reset 002 CMP L VDT = 0' GO SUB 11 50 Go to 0' after reset 1400 O' Found 1153 Go Fwd I 1256 Reset 002 1400 REV 03 FWD Motor 030 GoFwd2 136 At V.P Ready 1257 Cycle Ready 1700 Disab le Cycle 11 00 Cycle Done 1777 Cycle Ready 1700 Cycle Machine GO SUB 175 Go Rev I 115 FWD 30 Go Rev 1360 Figure 14 PLC implementation of the LVDT analog position reading example REV 031 273 Ph1,1 l1,1c I : System Programming and Implementation CMP Reg 4100